The most commonly used grid synchronisation technique in 3 phase power converters is the synchronous-reference-frame Phase-locked loop (SRF-PLL) [6, 67]. The simplicity in design, application and tuning has made SRF-PLL a pop-ular choice.
A diagram of a SRF-PLL is shown in Fig.5.1, which summarises the function of phase-locking. As can be seen, conventionally the 3-phase input voltage
CHAPTER 5: COMPARISON OF METHODS FORACCURATEFREQUENCY TREND
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signal is transformed in to d−q rotating reference frame, by employing Park’s Transformation. If the rotating d−q axis is synchronised and aligned to the d-axis, the q-axis voltage will be zero. Therefore, the q-component of the resulting d−q axis voltage is considered the error signal, which is minimised by the feedback loop. By doing so, the d-axis voltage will represent the amplitude of the fundamental input voltage signal. The only modification required to obtain the voltage signal amplitude is to reverse the scaling factor of 3/2 introduced in the Park-Transformation.
Figure 5.1:The model of an SRF-PLL
In the following mathematical discussion, the input voltage is assumed to be normalised, so that the amplitude of each phase is unity. The open-loop transfer function can be written using estimated θ′as,
GOL(s) = θ′
Hence, the closed-loop phase transfer functions,
Gθ(s) = θ′
θ = Kps+Ki
s2+Kps+Ki (5.3.2) Since θ′ = ωs′ and θ = ωs, the closed-loop frequency transfer function is also the same as (5.3.2) , from which the second-order characteristic equation can be derived,
s2+Kps+Ki =0 (5.3.3)
By equating coefficients with a characteristic second-order system of a damping factor, ζ and a natural frequency, ωn;
s2+Kps+Ki ≡s2+2ζωns+ω2n (5.3.4)
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the tuning criteria for Kpand Kifor a normalised PLL can be obtained as,
Kp=2ζωn (5.3.5)
Ki =ω2n (5.3.6)
Also, from control theory [6, 87], the settling time, ts of a second-order system can be approximated as,
ts ≈ 3.9
ζωn (5.3.7)
By substitution and rearrangement, Kp, Kiin (5.3.5) can be obtained, using the approximated function of settling time ts as shown below,
Kp ≈ 7.8
Another key parameter that needs considering in tuning a PLL is the lock range.
The lock range is defined as the frequency range within which the PLL is able to stay locked. (5.3.10) gives an approximation for the lock range ∆ωL, based on the design parameters ζ and ω [6].
∆ωL ≈2ζωn ≈Kp≈ 7.8
ts (5.3.10)
From the restriction of ∆ωL > 20Hz (from frequency range requirement), a restriction for the settling time can be set as ts <390 ms. This requirement must be met, otherwise SRF-PLL would not be able to function.
5.3.1 SRF-PLL Response to Step Change
The response of SRF-PLL for a balanced and undistorted signal undergoing a step frequency variation is considered in this section. The PLL was tuned for various settling times ts, while keeping the damping factor, ζ at 0.707 for fast detection with minimal oscillations - see Fig.5.2a. For each designed settling time ts, the actual settling time (i.e. within 2%) measured from the graph is shown in Fig.5.2b.
According to Fig.5.2b, one can see that for smaller settling times, the measured is close to the designed settling times. It differs slightly for longer settling times,
CHAPTER 5: COMPARISON OF METHODS FORACCURATEFREQUENCY TREND
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(a)Frequency step down (b)Measured Settling Time Figure 5.2:Frequency responses to step frequency change and measured
set-tling times for varying design setset-tling times
but the measured settling time and the design settling time has a linear relation-ship. The exact reason for the difference in two settling times is the effect of the zero in the closed-loop transfer function. The approximation of the design set-tling time given by (5.3.7) is for an ideal second-order system with no zeros.
From the results, the design settling time parameter can be restricted such that ts <56 ms in order to adhere to the requirements.
5.3.2 SRF-PLL Response to Ramp Change
The next frequency variation considered is a ramp of 100Hz/s. The input volt-age signal remains clean and balanced, while the ramp frequency variation was applied. For each design settling time ts, the derivative of the ramp frequency response was calculated to obtain the rate of change of frequency. The maxi-mum ROCOF obtained in each case was recorded against the design settling time as shown in Fig.5.3b. In order to illustrate the settling for a ramp, the frequency response for three settling times are shown in Fig.5.3a.
According to Fig.5.3a, the SRF-PLL converges to the ramp at about its settling time. This naturally will make the estimated ROCOF at some point higher than the actual value. The longer the settling time, the smaller the overestimation of ROCOF as can be seen in Fig.5.3b. According to Fig.5.3b, the settling time needs to be at least 200 ms, in order for SRF-PLL to not overestimate ROCOF by more than a 15%.
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(a)Frequency ramp (b)Measured maximum ROCOF Figure 5.3:Frequency responses to ramp frequency change of 100 Hz and
mea-sured maximum rocof for varying design settling times
5.3.3 SRF-PLL Response to Harmonics and Unbalance
In a weak grid, the voltage waveform is usually contaminated by harmonics especially when connected to a grid with switching power converters. Recall that the experimentally measured harmonic content was THD =6.07%. Com-pared to the undistorted case, the SRF-PLL clearly shows a rippled response in detected frequency when the input signal is distorted, even though, there has not been a frequency change as shown in Fig.5.4a. Therefore, the average value of the ripple frequency matches the expected value. This means that additional filtering can attenuate the ripple further by tuning the loop-filter with a higher settling time, at a cost of longer delay. Moreover, from Fig.5.4a, the ripple fre-quency could be seen as approximately 300 Hz. The formation of 300Hz can be accounted to the mixing of 7th harmonic (350 Hz) and the fundamental as well as mixing of−5thharmonic (−250Hz) and the fundamental.
An unbalance in the voltage input is caused by a sudden dip in the amplitude(s) of one or two phases. Even though the main concern does not include dealing with severe unbalance, the selected method must be able to tolerate relatively small unbalances. Hence, an unbalance of 5% was assumed by reducing phase-A by 5%. When the voltage experiences a 5% dip in one of the phases, the de-tected frequency becomes oscillatory with a double frequency ripple as shown in Fig.5.4b. The figure shows the response for three different settling times. This is caused by the frequency mixing effect of the Park transformation. Hence, the q-axis voltage contains a double frequency component caused by the frequency summation in addition to the error component (frequency difference) already present in the q-axis voltage. Since, the PLL is designed to minimise the error
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(a)Frequency Response with Harmonics (b)Frequency Response with Unbalance Figure 5.4:Frequency responses of a constant frequency with a) added
har-monics to replicate the weak grid voltage and b) unbalance.
in the q-axis voltage by minimising the phase difference, the double frequency component appears as a double frequency ripple in the detected frequency [6].
In order to obtain a measure of error in estimated frequency due to ripple caused by both harmonics and voltage unbalance, the ramp response was ob-served from 60 Hz to 40 Hz with 2 Hz/s. This slow ramp rate was chosen in order to capture the ripple at all frequencies in a single simulation. The error at each point in time relative to the actual frequency is recorded. By doing so, one can find the maximum error throughout the entire frequency range, if there ex-ists any variation in ripple due to variations in the fundamental frequency. The maximum error at each design settling time provides a measure of uncertainty in the context of the weak grid facility. The maximum error is recorded for several SRF-PLLs with varying settling times and is shown in Fig.5.5a, where frequency estimation error due to harmonics and unbalance are shown sepa-rately and in Fig.5.5b, where a combined error is shown.
According to Fig.5.5a, one can see that the error due to 5th and 7th harmonics dominate the error due to the 5% unbalance. As expected, longer settling times attenuate the ripple better. Also, Fig.5.5b shows that the design settling time must at least be 230 ms in order for the steady state error to be less than 0.5 Hz as per the requirements. Note that this is for the specific harmonics and unbalance present in the weak grid considered. A higher harmonic distortion and a larger unbalance in the voltage would require one to increase the settling time further.
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(a)Error due to harmonics and unbalance (b)Combined error
Figure 5.5:Error in the frequency measurement due to ripples in the steady state due to harmonics and voltage unbalance.
5.3.4 SRF Bandwidth Considerations
In the previous sections, the main design parameter of the SRF-PLL was the settling time (ts), which is the traditional technique followed [6]. However, the linearised transfer function given in (5.3.2) shows that there is a zero in the closed loop system. Usually, a closed-loop zero quickens the response, while lessening the damping (i.e. more overshoot) [87]. Therefore, one can expect to see a difference between the SRF-PLL response and a typical second-order system response with no zeros. The bandwidth of the SRF-PLL can be derived by evaluating the transfer function (5.3.2) in the frequency-domain as follows, Using s= jω, (5.3.2) becomes,
Gθ(jω) = 2ζωnjω+ω2
−ω2+2ζωnjω+ωn2 (5.3.11) The magnitude of this is,
|Gθ(jω)| =
(ω2n)2+ (2ζωnω)2 (ωn2−ω2)2+ (2ζωnω)2
12
(5.3.12)
The bandwidth of the system is defined as the frequency at which the magni-tude response crosses over −3dB. Therefore, at the bandwidth frequency the magnitude is,
|Gθ(jω−3dB)| = √1
2 (5.3.13)
By solving for the resulting quadratic equation in(ω−3dB)2and taking its
posi-CHAPTER 5: COMPARISON OF METHODS FORACCURATEFREQUENCY TREND
ESTIMATIONFOLLOWING LOAD TRANSIENTS IN WEAKELECTRICAL GRIDS
tive square root, the bandwidth of the SRF-PLL can be derived as,
ω−3dB =ωn
1+2ζ2+ q
(1+2ζ)2+1
1/2
(5.3.14)
Because ζ =0.707, and ωn ≈3.9/ζts, the bandwidth is given by,
ω−3dB ≈ 1.185
ts (5.3.15)
This confirms that the bandwidth is inversely proportional to the settling time as expected. This relationship is graphically shown in Fig. 5.6, which is to be used in section 5.6 to compare all three frequency detection techniques with the same bandwidth.
Figure 5.6:Bandwidth of SRF-PLL for varying settling times.
5.3.5 Optimum SRF-PLL Parameters For Energy Storage Control
The Table 5.2 summarises the requirements of the application (Energy storage control) and the design parameter ts restrictions that must be adhered to, if one should satisfy the requirements.
Parameter Requirement Restriction frequency range 40Hz−60Hz ts <390 ms ROCOFmax 100Hz/s ts >200 ms transient delay 10ms≤tdelay ≤50ms ts <56 ms
accuracy ∆ f ≤ ±0.5Hz ts >230 ms Table 5.2:SRF-PLL Design Parameter Restrictions
Immediately, from Table 5.2, it can be seen that a SRF-PLL is unable to satisfy all the requirements together. Out of all the requirements, only the frequency
CHAPTER 5: COMPARISON OF METHODS FORACCURATEFREQUENCY TREND
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range and the accuracy requirements are mandatory, so that both the SRF-PLL and the ES control can function. (The others increase the performance of the ES control and are thus essential.) Therefore, a design settling time of ts =230 ms has to be selected, in order to satisfy the mandatory requirements.
5.3.6 Summary
So far, the effective use of SRF-PLL for frequency detection purposes in a weak grid was demonstrated. The SRF-PLL tuning is relatively straight forward, be-cause the equivalent second-order system allows tuning based on the required settling time. As observed, the transient response and the steady state response are coupled and one can tune the PLL to obtain a compromise for the desired outcome. Even though the SRF-PLL can be tuned to achieve individual require-ments, not all the requirements can be met at the same time. Therefore, its use in a weak grid, where voltage unbalances and high harmonic distortion is com-monplace, is not recommended.