generation followed by simulation of the ALU circuit studied.
In this lab we will do the Synthsesis and Physical Design of ALU Design for which Synthesis will be done using RTL Compiler and Physical Design will be done using Encounter Digital Implementation System.
Lets do the Synthesis first.
Move to lab6 . Do listing to see the directories ‗ls‘.Then move to the work directory.
cd work.
Here you will find setup.g file.
Open setup.g by typing below command nedit setup.g
1. Set the library directory path where library files are stored.
set_attr lib_search_path ../lib
2. Give the path of the RTL files with respect to the local directory
―set_attr hdl_search_path ../rtl‖
3. Read the library from the directory specified in giving the path for the library files in step 2 using the command:
―set_attr library slow.lib‖
―slow.lib‖ is the name of the library file in the directory ―library‖. There is another library there in that directory with name ―fast.lib‖. Any one of these two libraries could be used at a time.
4 Read the RTL files from the directory specified in the path in step 3. The RTL files are in the directory name ―rtl‖:
―read_hdl alu.v
5 Elaborate the design using ―elaborate‖ command.
6 Give the command to see the circuit in Tool window:
The terminal window after the step 7 will look like The Tool window looks like image on next page
7. Give the standard delay constraints using:
―read_sdc ./constraints.g‖.
8. Synthesize the circuit using the command:
―synthesize -to_mapped‖.
9. Report the critical path of the design.
―report timing‖
10. Now synthesize the design by executing below command in the terminal/
Execute the script by typing ―rc –f setup.g‖ on your terminal window as given below
Type ― gui_show‖ in the terminal to see graphic window .
Report power by using below command in terminal
―report power‖
What do find for the below column
11. Write the hdl code in terms of library components for the synthesized circuit using the command:
―write_hdl >> alu.v‖
―alu.v‖ is the name of file in which the code gets write.
12. Similarly write the constraint file using
―write_sdc > > alu.sdc‖.
14. Timing could be check using ―report timing‖.
15. Similarly for Gates ―report gates‖.
16. Check area using ―report area‖.
17. Check Power dissipation using ―report power‖.
After the Synthesis ,Physical Design can be done by invoking the tool ―Encounter Digital implementation‖.
18. Invoke the tool using ―encounter‖ .The tool starts as below image:
The terminal window and tool window can be seen as similar to images on next page
Go the Tool window and click on the File and select Import Design. A new window will open.
19. Select the verilog files using browse button. A new window ―Netlist files‖ will open.
20. Click on the arrow button >> and select the verilog File ―alu_netlist.v‖ and click the Add button and then click the close
button.
21. Click on Auto assign after top cell.
22. Similarly select the lef file by clicking the browse button and then add the lef file with name ―all.lef‖ in the lef directory.
23. Select the timing libraries. For maximum timing libraries select all libraries with
―slow‖ in their name and for minimum timing libraries select all libraries with fast in their names. Alternatively, instead of selecting all the libraries for Maximum timing libraries, type ―../lib/*slow*.lib‖ in space in front of Maximum Timing Libraries. This will select all the slow libraries. Similarly in front of Minimum Timing Libraries write
―../lib/*fast*.lib‖.
24. Similarly select ―alu.sdc‖ for timing constraint file.
25. In the Design Import window click on Advanced Tab. Select Power out of the list on the left side of window. Enter the power nets as VDD and Ground nets as VSS.
The screen shot is shown in the next page.
26. Select OK. The tool window will look like image on next page.
This is floorplan view of the design.
27. Click on Floorplan and select ―Specify Floorplan‖.
Select the Aspect Ratio as per the requirement. Set aspect ratio to 1. Give some
dimension in ―Core to left‖, ―Core to right‖, ―Core to top‖,―Core to bottom‖. e.g. give 20 to each. This is to create the space for Power rings which will be created in power
planning. Click OK and the Tool window will be look like as below.
28. Next step is to do global net connect .Click on Power - Connect Global Nets A browser opens as shown in the next page
In the ―To Global Net‖ Column type VDD
Select ―Pin‖ button from Connect and in Pin Names(s) type VDD , then click on
―Add to in list‖ ,so that it is added in Connection List column as shown next page . Similarly global net connect has to created to VSS as described above .After crating global net connect for VSS , click Apply button close the Global Net Connection window.
29. Equivalent tcl command :
globalNetConnect VDD -type pgpin -pin VDD -inst * -module {}
globalNetConnect VSS -type pgpin -pin VSS -inst * -module {}
Next step is power planning. Click on Power, select power planning and click on Add Rings.
30. Select the top and bottom layer as Metal5, Left and Right as Metal6. Set the width as per the requirement ex 5 and taking the space between core boundary and I/O pad considerations. Select the option for offset as ―center in channel‖ and click OK.
The power ring will get created in between the channel. The image on the next page is showing the power ring created.
31 After the power planning, go to ―Place‖ and click Place Standard Cells. A new Window Place will appear.
32 Click OK on Place window and in physical view the blue coloured standard cells can be seen as a result of placement of standard cells.
33 Click OK with all default settings. This is done to provide power to standard cells.
The horizontal blue coloured metal1 stripes created as a result of Special Route.
34 Now we power routing has to be done for the placed standard cells.For power routing , click on Route and select Special Route .When the window opens unckeck the Block Pins Pad Pins and Pad Rings ,because we are doing Sroute for standard cells as shown in the next page.
Click on OK to power route for the standard cells.
35 Before CTS, timing analysis has to be done for any setup violations. Click on Timing, and select Report Timing. A Timing analysis window will get open. In the window select the ―Pre-CTS‖ as Design Stage and select the ―Setup‖ as Analysis Type.
36 Click OK to complete the Timing analysis. The timing information will get display on terminal in tabular form. In the table displayed on the terminal under
―timeDesign Summary‖, check for any negative value under WNS(Worst Negative Slack) and TNS(Total Negative Slack). The terminal will look as the image below and Tool window as on next page.
The multi-coloured lines visible in the tool window are the connections between standard cells using metal layers. If any part of this design is Zoom-in, metal layers can be viewed easily.
Different colours show different metal
37 If there is any of the negative slack value under WNS or TNS, click Optimize in Tool window and Select Optimize Design. A new window ―Optimization‖ will get open. Select ―Pre-CTS‖ as Design Stage and ―Setup‖ as optimization type and click OK. The tool will optimize the design and the optimized timing results will be displayed over terminal again.
In this case we did not get any negative slack, so this step is skipped here.
38 Go to Clock, click ―Synthesize Clock Tree‖, a new window ―Synthesize Clock Tree‖ will get open.
39 Click on Gen Spec and a new window ―Generate Clock Spec‖ will open.
40 From Cells List, Select all clocks starting with ―CLK‖ and click on Add button to add them to the Selected Cells. Select a name for Output specification.
41 Click OK. Then specify a name for Results Directory. and click OK. The tool window looks like the image below.
42 Again Perform the Timing by clicking on Timing and selecting Report Timing.
Select ―Post-CTS‖ under Design Stage and do the select ―Set-up‖ as Analysis Type.
43 Click Ok to perform the timing. The timing information will be displayed over the terminal window. Again check for any negative slacks under WNS or TNS.
44 If there is any negative value found for either of WNS or TNS then perform the Optimization Technique to reduce the negative slack. No negative slack is found in the terminal image on previous page so this step is skipped here.
45 Timing Analysis for ―Setup‖ as Analysis Type is done. Repeat Step 42 for
performing timing for ―Post CTS‖ as Design Stage and ―Hold‖ as Analysis Type.
The tool will show the timing results in the terminal window.
46 After Timing Analysis is performed, the timeDesign Summary is showing the
negative slack values for both TNS and WNS. Perform the Optimization. Go to Optimize and click on Optimize Design. Select ―Post-CTS‖ and ―HOLD‖ as the Optimization Type.
47 Click OK to perform the Optimization and Tool will perform the optimization and displays the optimized results in the terminal window under timeDesign
Summary. The results of Optimization can be seen on the next page in tabular form for both Setup and Hold mode. As compare to the Timing Results performed for Hold mode in Step 46, the design has been optimized and tabular results shows that all slack values are now positive values and no more negative values for slack.
Now we have to connect all new cells to VDD/GND Type below commands in the terminal
globalNetConnect VDD -type tiehi
globalNetConnect VDD -type pgpin -pin VDD -override globalNetConnect VSS -type tielo
globalNetConnect VSS -type pgpin -pin VSS -override
48 Perform Routing by clicking Route, and select NanoRoute and then click Route.
A window NanoRoute will open.
Equivalent tcl command
# Run global Routing
# utilizes the nano router globalDetailRoute
49 Click Ok to Perform Routing. The tool will Perform the Routing and the Routing statistics can be seen on terminal window including DRC violations.
After routing tool window looks like the below image.
50 Perform the timing again. Go to Timing, select Report Timing and a Timing Analysis window will get open. Select ―Post-Route‖ as the Design Stage and
―Setup‖ as Analysis Type. Click Ok. The timing results will be displayed in terminal window for Set up mode.
Since there is no negative value of slack so design does not require optimization for Set-up mode in Post-Route stage.
51 Repeat step for ―Post-Route‖ as Design Stage and ―Hold‖ as the Analysis Type.
Click OK. The timing results can be seen in the terminal window for hold mode.
As there is no negative value of slack, the optimization is not required to perform. The final view of the circuit is as below:
Write the final gds file
Go to File – Save – GDS/OASIS
Equivalent tcl command:
streamOut final.gds -mapFile streamOut.map -libName DesignLib -units 2000 -mode ALL