System Configuration

The components discussed above were synthesized into a high-level system design for the dynamic data acquisition system, whose block diagram is shown in Figure 3-4. The Atxmega1284AU runs code written in C/C++ to control the device. Software is flashed onto the Atxmega128A4U using the on-board PDI interface and an Atmel ICE Debugger. The Atmel ICE

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debugger is a powerful development tool for programming and debugging Atmel SAMTM _and Atmel AVRTM _{microcontrollers (Atmel, 2016).}

Figure 3-4: Dynamic data acquisition system device hardware diagram.

The on-board UART interface is used to transmit/receive data from the FT232R chip, which transmits/receives data from a serial terminal on a computer. The serial connection and 5 V power are supplied by a computer through a microUSB socket. The low-dropout regulator (LDO) LD1117S33TR was selected to regulate the supply voltage to 3.3 V. This device is the same LDO used in the RFduinoTM _{USB Shield, and was proven to function at low temperatures during the} quasi-static device testing. To provide a 32.768 kHz clock frequency for both the Atxmega128A4U and the AD7708, the MC-405 crystal was selected due to its high precision and stability at low temperatures (EPSON, n.d.). One crystal is used to drive the internal PLL of the AD7708, and another is used to drive the internal RTC of the Atxmega128A4U. To control the AD7708, the SPI interface on port C is used in 4-wire mode at a frequency of 4 MHz. The SPI interface on port D is

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used in 4-wire mode at 8 MHz to write data to a microSD card. Separate SPI interfaces were used for interfacing with the AD7708 and a microSD card so that the device may communicate with both devices at once if necessary. The pinout for the Atxmega128A4U with pin descriptions and utilizations is displayed in Table 3-2.

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Table 3-2: Atxmega128A4U chip pinout for dynamic data acquisition system.

Number Pin Name Description Use

1 PA5 Port A GPIO 5 NC

2 PA6 Port A GPIO 6 NC

3 PA7 Port A GPIO 7 NC

4 PB0 Port B GPIO 0 Status LED

5 PB1 Port B GPIO 1 Status LED

6 PB2 Port B GPIO 2 Status LED

7 PB3 Port B GPIO 3 Status LED

8 GND Ground GND

9 VCC Supply voltage VCC

10 PC0 Port C GPIO 0 NC

11 PC1 Port C GPIO 1 Wheatstone bridge toggle

12 PC2 Port C GPIO 2 AD7708 reset

13 PC3 Port C GPIO 3 AD7708 status

14 PC4 Port C GPIO 4 AD7708 CS

15 PC5 Port C GPIO 5 SPI MOSI

16 PC6 Port C GPIO 6 SPI MISO

17 PC7 Port C GPIO 7 SPI SCK

18 GND Ground GND

19 VCC Supply voltage VCC

20 PD0 Port D GPIO 0 NC

21 PD1 Port D GPIO 1 NC

22 PD2 Port D GPIO 2 NC

23 PD3 Port D GPIO 3 SD card detect

24 PD4 Port D GPIO 4 SD card CS

25 PD5 Port D GPIO 5 SPI MOSI

26 PD6 Port D GPIO 6 SPI MISO

27 PD7 Port D GPIO 7 SPI SCK

28 PE0 Port E GPIO 0 NC

29 PE1 Port E GPIO 1 NC

30 GND Ground GND

31 VCC Supply Voltage VCC

32 PE2 Port E GPIO 2 RXD

33 PE3 Port E GPIO 3 TXD

34 PDI_DATA PDI data pin Programming/Debugging 35 PDI_CLK Reset/PDI clock pin Reset/Programming/Debugging 36 PR0 External clock/crystal pin 0 External crystal

37 PR1 External clock/crystal pin 1 External crystal

38 GND Analog ground GND

39 AVCC Analog supply voltage AVCC 40 PA0 Port A GPIO 0 3.0V Reference

41 PA1 Port A GPIO 1 ADC CH1

42 PA2 Port A GPIO 2 ADC CH2

43 PA3 Port A GPIO 3 ADC CH3

44 PA4 Port A GPIO 4 Wheatstone bridge toggle

Three channels on the AD7708 are wired to read voltage across three different Wheatstone bridges. To test different Wheatstone bridge configurations, a quarter-bridge, half-bridge, and full- bridge are connected to each of the three ADC channels. The quarter-bridge configuration is shown

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in Section 2.1.2, and the half-bridge and full-bridge configurations are shown below in Figure 3-5. Equations 3-1 and 3-2 are used to calculate strain from the voltage output of the half-bridge and full-bridge, respectively (Omega Engineering, 1999). The 120 Ω resistors utilized in the quasi- static device were switched with 350 Ω precision resistors to reduce the power draw of the Wheatstone bridges (Vishay, 2015).

Figure 3-5: Wheatstone half-bridge (left) and full-bridge (right) configurations.

𝜀 = −2𝑉𝑟𝑛𝑒𝑡

𝐺𝐹 (3-1)

𝜀 = −𝑉𝑟𝑛𝑒𝑡

𝐺𝐹 (3-2)

The excitation voltage for the Wheatstone bridges was supplied using the AD780R, an ultrahigh precision band gap reference voltage IC that supplies 3.0 V from the 5 V device supply (Analog Devices, 2017). The measurement from each bridge is electronically filtered by a 0.1 µF bypass capacitor between the differential signals.

Additionally, three channels on the on-board ADC interface are used to measure voltage across three 350 Ω half-bridge configurations. The half-bridges are excited by a 3.0 V reference voltage supplied by an additional AD780R. Because the on-board ADC has no analog filter capabilities, differential first-order passive, first-order active, and second-order active low-pass filters are used to filter the measurements acquired by each of the three ADC channels. The

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operational amplifier used in the first and second-order active filters is the LMV321ILT, a general- purpose rail-to-rail amplifier (STMicroelectronics, 2015). Downstream of the differential filters, a differential amplifier circuit is used to amplify and offset each signal, which is then converted using the on-board ADC. The differential filters and differential amplifier specifications will be presented in Section 3.1.3.2.