Temperature Variation

For temperature variation, we compare the intra-FHD at 20◦C and between 20◦C and 75◦C, which is the reliability of the PUF if it is enrolled at 20◦C but verified at 75◦C.

Figure 3.16 shows the intra-FHD weak UNBIAS PUF using bit14 as the inspection bit.

The figure shows that for most PUFs, the intra-FHD at the extreme temperature is less than 15% except for two PUFs with about 18%. The instability of the weak UNBIAS PUF is relatively large and similar to the results presented in [42] for the standard RO PUF.

Figure 3.16: Weak UNBIAS PUF intra-FHD.

For the strong UNBIAS PUF, we use bit10 as the inspection bit for the measurement.

The results are presented in Figure 3.17. The averaged intra-FHD at high temperature is about 8% and the worst case is still less than 10%, which is within conventional ECC margin with error reduction techniques for PUFs [46, 47]. One possible explanation of smaller intra-

FHD for the strong UNBIAS PUF is that with multiple RO delay units, the overall delay variation is canceled out, where for the weak UNBIAS PUF, the variation of each RO is directly compared.

Figure 3.17: Strong UNBIAS PUF intra-FHD.

3.6

Conclusions

The proposed UNBIAS PUF effectively reduces PUF implementation efforts by mitigating the impact of biased delay paths and metastability issues. Without complex post-layout analysis or hand-crafted physical design effort, the proposed measurement can still extract local device randomness. The inspection bit can be determined efficiently from the intra- FHD and inter-FHD prediction models.

Two UNBIAS PUFs, a weak and a strong PUF, are implemented on 11 FPGAs without imposing any physical layout constraints. Experimental results show that the intra-FHD of the strong UNBIAS PUF is 5.1% and the inter-FHD is 45.7%, and the prediction models are closely fitted to the measured data for both UNBIAS PUFs. The intra-FHD of the strong UNBIAS PUF at high temperature is about 8%, which is still within the margin of conventional ECC techniques. The fact that the proposed scheme is immune to physical im- plementation bias would allow the UNBIAS PUF to be integrated in a high-level description of the design, such as during RTL design.

CHAPTER 4

LEDPUF: Stability-Guaranteed Physical Unclonable

Functions through Locally Enhanced Defectivity

Instability has been an Achilles heel for physical unclonable functions (PUF) requiring com- plex error correction or other stability enhancement approaches. This instability originates from parametric nature of variations leveraged as a source of randomness, which constraints PUF from being put in widespread practical use. In this chapter, we propose several weak PUFs and strong PUFs that are completely stable with 0% intra-distance. These PUFs are called Locally Enhanced Defectivity Physical Unclonable Function (LEDPUF). A LEDPUF is a pure functional PUF which eliminates the instability of conventional parametric PUFs, therefore no helper data, fuzzy comparator, or any kinds of correction schemes are required. We propose two sources of randomness for LEDPUFs. The first is to use the Directed Self Assembly (DSA) process to form random connections that are permanently closed or opened. The weak DSA LEDPUF is constructed by forming arrays of DSA random connec- tions, and the strong DSA LEDPUF is implemented by using the weak LEDPUF as the key of a keyed-hash message authentication code (HMAC). Our simulation and statistical results show that the entropy of the weak LEDPUF bits is close to ideal, and the inter-distances of both weak and strong LEDPUFs are about 50%, which means that these LEDPUFs are not only stable but also unique. The second source of randomness is extracted using two random gate oxide breakdown mechanisms: plasma induced damage during semiconductor manufacturing and voltage stressed damage post manufacturing. These gate oxide break- down LEDPUFs can be easily implemented in commercial silicon processes without extra cost on PUF manufacturing and design, and they are stable and resistant to physical at- tacks. We fabricated bit generation units for the stable PUFs on 99 testchips with 65nm

CMOS bulk technology. Measurement results show that the plasma induced breakdown can generate completely stable responses for all 2871 bits (29 bits from each of the testchip) and significant area reduction compared with SRAM PUF can be achieved by eliminating the error correction code (ECC) hardware implementation. For the voltage stressed breakdown, the area cost is further reduced, and its 0.12% bit error rate at a worst case corner can be effectively accommodated by taking the majority vote from multiple measurements without ECC. We show that the responses of gate oxide breakdown PUFs are unique. In addition, we analyze the data of our testchips and show through various statistical distance measures that the bits of our fabricated PUFs are independent.

4.1

Introduction

A Physical Unclonable Function (PUF) is a small piece of circuitry such that its behavior, or Challenge Response Pair (CRP) [3], is uniquely defined and it is hard to be predicted and replicated because of the intrinsic random physical nature and the uncontrollability of process variations. As a security primitive, PUF can enable low overhead hardware identification, tracing, and authentication during the global manufacturing chain. The first PUF was introduced more than a decade ago [9]. Since then, many silicon PUF implementations have been proposed, such as Arbiter PUF [10], Ring Oscillator (RO) PUF [11], SRAM PUF [12], and many other variations. However, since the key commonality between all current silicon PUF implementations is their use of parametric manufacturing variations as the source of randomness, there exist several limitations that can cost expensive implementation overhead.

4.1.1 Limitations of Parametric PUFs