The AT89S8253 Microcontroller Memory Organization Program Memory (ROM)

2.9 8051 Microcontroller Power Consumption Control

XTAL 1 This is internal oscillator input It is used for the purpose of synchronizing the operation of the

4.3 The AT89S8253 Microcontroller Memory Organization Program Memory (ROM)

Program memory (ROM) with a capacity of 12Kb is designed in FLASH technology, which enables programs to be loaded and erased a large number of times. It is programmed via embedded SPI module (Serial Peripheral Interface). If necessary, it is possible to add external ROM memory chip, although 12Kb of ROM is usually more than enough.

Random Access Memory (RAM)

RAM memory consists of 3 blocks containing 128 registers each. Its structure falls into the 8051 standard:

128 general-purpose registers;

128 memory locations reserved for SFRs. Even though only some of them are trully used, free locations shouldn‟t be used for storing variables; and

128 additional registers available for use (have no special purpose). Since they have the same addresses as SFRs, they are accessed by indirect addressing.

EEPROM Memory

EEPROM is a special type of memory having features of both RAM and ROM. The contents of the EEPROM may be changed during operation, but remains permanently saved even after the loss of power. The AT89S8253 microcontroller has in total of 2K of EEPROM, that is 2048 locations.

Memory Expansion

All mentioned above about ROM and RAM memory expansion remains in force when it comes to the AT89S8253 microcontroller as it is based on the 8051 core. In other words, both memories can be added

as external chips with the capacity of up to 64Kb. The process of addressing is also the same as in the 8051 standard.

Types of addressing

Similar to all microcontrollers compatible with the 8051, there are two ways of addressing: Direct addressing (for example: MOV A,30h); and

Indirect addressing (for example: MOV A,@R0).

4.4 Special Function Registers (SFRs)

The AT89S8253 microcontroller has in total of 40 Special Function Registers. For the sake of the compatibility with the previous 8051 models, the core registers (22 in total) are the same for all of them, while the others were added later for the purpose of controlling upgraded functions of the microcontroller.

As shown in the table above, each of these registers has its name and specific address in RAM.

Unoccupied locations are intended for the future upgraded versions of the microcontroller and shouldn‟t be used. As their name suggests, these registers are mostly in control of one specific circuit within the microcontroller such as timers or SPI etc. and they will be discussed later in the book. This chapter covers only those SFRs controlling more than one circuit within the microcontroller.

Accumulator (ACC)

The accumulator, otherwise marked as ACC or A, belongs to the core registers of the 8051 microcontroller. Its contents is not modified.

B register

operands upon which these operations are performed.

PSW register (Program Status Word Register)

The PSW register belongs to the core registers of the 8051 microcontroller. Bits of this register are not modified.

SP registar (Stack Pointer Register)

The SP register belongs to the core registers of the 8051 microcontroller. Bits of this register are not modified.

Registers P0, P1, P2, P3

Each bit of these registers corresponds to one of the port pins having the same name. These registers are therefore used for comminication with peripheral environment which is carried out by sending data from registers to the corresponding pins and vice versa. They belong to the core registers of the 8051

microcontroller and their bits are not modified.

They belong to the core registers of the 8051 microcontroller. Their bits are not modified.

AUXR register (Auxiliary register)

The AUXR register contains only two active bits:

DISALE

o 0 - ALE is activated at a constant rate of 1/6 the oscillator frequency. o 1 - ALE is active only during execution of MOVX or MOVC instructions. Intel_Pwd_Exit

o 0 - When the microcontroller is in Power Down mode, the program proceeds with

execution on high-to-low transition (1-0).

o 1 - When the microcontroller is in Power Down mode, the program proceeds with

execution on low-to-high transition (0-1).

CLKREG register (Clock Register) X2

0 - The oscillator frequency (the XTAL1 pin) is divided by 2 before used as a clock (machine

cycle lasts for 6 such periods).

1 - Quartz oscillator is used as a clock generator. This enables the quartz crystal of two times

lower frequency (for example 6MHz instead of 12MHz) to be used for the same operating rate of the microcontroller.

Data Pointers

Data Pointers are not true registers as they don‟t physically exist. They consist of two separate registers: DPH (Data Pointer High) and DPL (Data Pointer Low). All 16 bits are used for addressing external and internal EEPROM memory. The DPS bit of the EECON register determines the registers to be used as

DPS=0 -> Data pointer consists of DP0L and DP0H registers and is marked as DPTR0.

DPS=1 -> Data pointer consists of DP1L and DP1H registers and is marked as DPTR1.

Handling EEPROM memory

2 Kb of on-chip EEPROM memory enables this microcontroller to store data created during operation which must be permanently saved. In other words, all data stored in this memory remains permanently saved even after the loss of power. Minimum 100 000 writing cycles can be executed. This memory is easily used since there are only a few control bits enabling it.

EEPROM write and read is under control of the EECON special function register. Since the process of programming EEPROM is relatively slow (write to one register takes approximately 4mS), a small hardware trick is done in order to speed it up. When the EELD bit of the EECON register is set, the data is not directly written to the EEPROM registers, but loaded in a small buffer (temporary memory) with a capacity of 32 bytes. When this bit is cleared, the first data following it will be normally written to the EEPROM (takes 4 mS) along with all registers currently loaded in the buffer. Thus, it takes only 4mS to write all 32 bytes instead of 128mS otherwise required in a single byte writing.

EEPROM memory is handled in the same way as external memory. For this reason, a special instruction for additional memory chip (MOVX) is also used for EEPROM write and read. The EEMEN bit of the EECON register determines whether the data is to be written/read from additional memory chip or on- chip EEPROM memory.

EECON register

Bits of the EECON register controls the operation of EEPROM memory:

WRTINH

The WRTINH bit is read-only. When the power supply voltage is too low for programming EEPROM, hardware automatically clears this bit, which means that write to EEPROM cannot be completed or is aborted if in progress.

RDY/BSY

The RDY/BSY bit is read-only.

0 - Write in progress (takes approximately 4mS). 1 - Write complete (data is written to EEPROM). DPS

0 - Address for EEPROM write/read is stored in the DP0H and DP0L registers. 1 - Address for EEPROM write/read is stored in the DP1H and DP1L registers. EEMEN

0 - Instruction MOVX is used for accessing external memory chip.

1 - Instruction MOVX is used for accessing internal EEPROM memory. If the register address is

larger than 2K, the microcontroller will access external memory chip.

EEPROM write, the bit must be cleared from within the program.

EELD

When set, the EELD bit enables up to 32 bytes to be written simultaneously. The bit is set and the MOVX instruction writes data to EEPROM (buffer is loaded). The bit is cleared before writing the last data. When the last MOVX is executed, the entire buffer is automatically loaded to EEPROM for 4mS.

4.5 Watchdog Timer (WDT)

The watchdog timer uses pulses generated by the quartz oscillator for its operation. It is disabled after reset and during Power Down Mode, thus having no effect on the program execution. If enabled, every time it counts up to the program end, the microcontroller reset occurs and program execution starts from the first instruction. Reset condition indicates that the program doesn‟t work properly for some reason. The point is to prevent this from happening by setting instruction to reset the watchdog timer at the appropriate program location. Practically, the whole this process is in control of several bits of the WDTCON register.

Three bits (PS2, PS1 and PS0), which are in control of the prescaler, determine the most important feature of the watchdog timer- nominal time, i.e. time required to count up a full cycle.

The values contained in the table below are applied only when the 12MHz quartz oscillator is used.

Prescaler Bits Nominal Time PS2 PS1 PS0 0 0 0 16ms 0 0 1 32ms 0 1 0 64ms 0 1 1 128ms 1 0 0 256ms 1 0 1 512ms 1 1 0 1024ms 1 1 1 2048ms

WDTCON Register (Watchdog Control Register)

PS2,PS1,PS0

These three bits are in control of the prescaler and determine the nominal time of the watchdog timer. If the program doesn‟t clear the WSWRST bit during that time, the watchdog timer will reset the

microcontroller. When all three bits are cleared to 0, the watchdog timer has a nominal period of 16K machine cycles. When all three bits are set to 1, the nominal period is 2048K machine cycles.

WDIDLE

The WDIDLE bit enables/disables the watchdog timer in Idle mode:

0 - Watchdog timer is enabled in Idle mode (low-consumption mode). 1 - Watchdog timer is disabled in Idle mode.

DISRTO

The DISRTO bit enables/disables reset of peripheral circuits connected to the RST pin:

0 - Watchdog controls the state of the input reset pin. At the moment of reset, this pin acts for a

moment as an output and generates a logic one (1). It causes the microcontroller and all other circuits connected to the RST pin to be reset.

1 - Reset triggered by the watchdog timer doesn‟t affect the state of the reset pin. At the moment

the watchdog timer resets the microcontroller, the reset pin remains configured as an input.

HWDT

The HWDT bit selects hardware or software mode for the watchdog timer:

0 - Watchdog is in software mode and can be enabled or disabled by the WDTEN bit.

1 - Watchdog is in hardware mode. To enable it, the sequence 1E/E1(hex) should be written to the

WDTRST register. Only reset condition can disable the watchdog timer. In order to prevent the WCDT from resetting the microcontroller when the nominal time expires, the same sequence 1E/E1hex must be constantly repeated.

WSWRST

When set, this bit resets the watchdog timer in software mode (bit HWDT=0). In order to enable the microcontroller to operate without being interrupted, this bit must regularly be cleared from within the program. After being set, the watchdog timer is cleared by hardware, counting starts from zero and the bit is automatically cleared.

If the watchdog timer is in hardware mode, setting this bit has no effect on the watchdog timer operation.

WDTEN

The WDTEN bit enables/disables the watchdog timer in software mode (HWDT=0):

0 - Watchdog disabled. 1 - Watchdog enabled.

When the watchdog timer is in hardware mode (HWDT=1), this bit is read-only and reflects the status of the watchdog timer (whether it is enabled or disabled).

The WDTEN bit doesn‟t clear the watchdog timer, it only enables/disables it. This means that the current state of the counter remains unchanged as long as WDTEN=0.

4.6 Interrupts

The AT89S8253 has in total of six interrupt sources, which means that it can recognize up to 6 different events that can interrupt regular program execution. Each of these interrupts can be individually enabled or disabled by setting bits of the IE register, whereas the whole interrupt system can be disabled by clearing the EA bit of the same register.

Since this microcontroller has embedded Timer T2 and SPI (they don't fall under the “8051 Standard”) which can generate an interrupt, it was necessary to make some changes in registers controlling interrupt system. Besides, there is a new interrupt vector (address 2B), i.e. program memory address from which

made on the previously unused bits. This enables all programs written for the previous versions of the microcontrollers to be used in this one too without being modified. This is why the 8051-based microcontrollers are so popular.

IE register (Interrupt Enable Register)

EA bit enables or disables all interrupt sources (globally):

0 - disables all interrupts (even enabled). 1 - enables specific interrupts.

ET2 bit enables or disables Timer T2 interrupt:

0 - Timer T2 interrupt disabled. 1 - Timera T2 interrupt enabled.

ES bit enables or disables serial communication (UART and SPI) interrupts:

0 - UART and SPI interrupt disabled. 1 - UART and SPI interrupts enabled.

ET1 bit enables or disables Timer T1 interrupt:

0 - Timer T1 interrupt disabled. 1 - Timer T1 interrupt enabled.

EX1 bit enables or disables external interrupt through the INT0 pin:

0 - Interrupt on the INT0 pin disabled. 1 - Interrupt on the INT0 pin enabled.

0 - Timer T0 interrupt disabled. 1 - Timer T0 interrupt enabled.

EX0 bit enables or disables external interrupt through the INT1 pin:

0 - Interrupt on the INT1 pin disabled. 1 - Interrupt on the INT1 pin enabled. Interrupt Priorities

When several interrupts are enabled, it may happen that while one of them is in progress, another one is requested. In such situations, the microcontroller needs to know whether to proceed with the execution of current interrupt routine or to meet a new interrupt request. For this reason, there is a priority list on the basis of which the microcontroller knows what to do. The previous versions of the microcontrollers differentiate between two priority levels defined in the IP register.

As for the AT89S8253 microcontroller, there is an additional SFR register IPH which enables all the interrupts to be assigned 1 out of 4 priorities (excluding reset). Here is a list of priorities:

1. Reset. If a reset request arrives, all processes are stopped and the microcontroller restarts. 2. The high priority interrupt (3) can be disabled by reset only.

3. The low priority interrupt (2, 1 or 0) can be disabled by any high priority interrupt and reset. It is usually defined at the beginning of the program which one of the existing interrupt sources have high and which one has low priority level. According to this, the following occurs:

If two interrupt requests, at different priority levels, arrive at the same time then the higher priority interrupt is always serviced first.

If the both interrupt requests, at the same priority level, occur one after another, the one which came later has to wait until routine being in progress ends.

If two interrupt requests of equal priority arrive at the same time then the interrupt to be serviced is selected according to the following priority list :

1. External interrupt INT0 2. Timer T0 interrupt 3. External interrupt INT1 4. Timer T1 interrupt

5. Serial communication interrupt 6. Timer T2 Interrupt

IP register (Interrupt Priority Register)

Bits of this register determine the interrupt source priority. PT2 Timer T2 interrupt priority: