The parallelism or multiplexing techniques

The parallelism technique is a technology independent technique which reduces power consumption and maintains the throughput of logic blocks and processors by decreasing the operating frequency and supply voltage [27,28]. At a reduced Vdd, this method is used to maintain the throughput of logic devices that are placed on the critical path. Parallelism as shown in Figure 2.6 accommodates M parallel units which are clocked at f/M. Each unit can compute its results in a time slot M times longer and can therefore be supplied at a reduced supply voltage. f Input f f/2 f/2 _f/2 Datapath 1 Datapath 2 M U X 1 2 Flip-flop Flip-flop

Figure 2.6: The architecture of parallelism technique [8].

Multiple instances are needed if the units used are datapaths or processors which results in an

M times area increase and switching capacitance. However, if the units used consist of

smaller transistors and the operating frequency is reduced, a power reduction can be achieved. In addition, some parallelized logic units do not require M-unit replication such as memories. In parallelized memories, each unit contains 1/M bits of data or instruction, resulting in the same total area to store the information and the same total switching capacitance. Parallelized circuits such as memories, shift registers and serial-parallel

34 converters are a few examples that accommodate parallelism at low Vdd and incurring a small overhead [29].

The parallelism technique can be applied to on-chip signalling schemes through the use of transceivers. Parallelism in transceivers obviates the need for high frequency clocks to achieve high bit-rates [30,31]. High bit-rates can be supported while both transmitter and receiver operate at a lower frequency. The technique comprises multiple transmitters connected in parallel converting low frequency parallel data streams into a single high frequency stream on the channel through a multiplexer. The parallel receivers will then convert the high frequency data stream back to the low frequency parallel data streams [31]. The parallelism technique lowers the clock frequency needed to support a certain bit-rate and thus provides opportunities for saving power. This is mainly due to the voltage being adaptively scaled down for the lower clock frequency. However, without the voltage scaling, the power reduction cannot be achieved because the power reduction due to the lower frequency is cancelled by the increased switched capacitance.

The parallelism technique with multiplexed transceivers can be divided into two categories, namely, the output and input multiplexed transmitters. The output multiplexed transmitter proposed by Yang [30] has multiple drivers connected in parallel with each driver consisting of two PMOS transistors in series, as shown in Figure 2.7. Each driver is only active when the inputs, namely dclk(n) and qclk(n), are low. The inputs are aligned with the clock phases that are one phase apart, Φ(n) and Φ(n+1). The pre-driver shown in Figure 2.7 controls the input clock frequency depending on the data being transmitted to match the delays between the two inputs. However, there are factors that limit the potential of this driver circuit which is mostly Vth-related problems. Increased driver sizing is necessary to support the desired swing at low Vdd as Vdd approaches Vth. However, this reduces the power savings benefits of low voltage operation since increasing the driver size means higher driver current, thus increase in power. In addition, lower Vdd will result in a narrower pulse width at the output [30].

35 D(n) Vdd Vdd Vdd Φ(n+1) Φ(n) Vdd dclk(n) qclk(n) out on-chip termination Vdd D clk Pre-driver

Figure 2.7: The output multiplexed transmitter by Yang et al [30].

Alternatively, the problems with the output multiplexed transmitter shown in Figure 2.7 can be solved by implementing the multiplexed transmitter with the level shifting pre-driver circuit [32]. The level-shifting pre-driver shown in Figure 2.8, shifts the voltage level of input driver down by Vth so that the PMOS driver inputs swing between –Vth and V-Vth which subsequently mitigates the previous driver‟s problem with Vdd as the PMOS driver behaves as if its Vth is 0. In addition, this driver is less sensitive to supply voltage variation because the turn-on and turn-off points of the driver are now independent of Vdd [32]. However, the power savings benefit might be compromised by the need for negative pulse generator to assist the PMOS driver in switching down to –Vth for full output swing. Power saving is achieved with increased data rates without increasing the size of the driver but instead requires additional circuitry, i.e. the negative pulse generator. The power savings benefit of the output multiplexed transmitter scheme with level-shifting pre-driver circuit is significantly affected as the negative pulse generator is required for each driver at every data stream input. Subsequently, this also results in the silicon area overhead.

36 D(n) Φ(n+1) Φ(n) Vdd dclk(n) qclk(n) out on-chip termination Vdd Vdd Vdd level-shifting pre-driver V(n) V(n) !V(n) !V(n) Negative pulse generator

Vdd V(n)

!V(n) clk

!clk

Figure 2.8: The output multiplexed transmitter with level-shifting [32].

The input multiplexed transmitters shown in Figure 2.9 [33] provides speed improvement over the output multiplexed architecture as well as significantly lower power and area overheads. The input multiplexed transmitter reduces the clock load by a significant amount by multiplexing signals before amplification. It also reduces area by requiring only a single copy of the output driver rather than one copy for each multiplexer input. The transmitter comprises a dual pseudo-NMOS multiplexer, a pre-amplifier and an output driver, and also employs a delay-locked loop circuit with regulated supply voltage, which further reduces the power consumption as well as achieving better supply noise rejection [33].

The main problem with the parallelism or multiplexing technique is its stringent matching requirement among the parallel components to avoid degradation of signal quality. To add to its complexity, each multiplexed transmitter is required for every data stream input which may include additional circuitry such as level shifter as in [32]. This leads to increase in power consumption and silicon area overhead. Even though input multiplexed transmitter has several advantages over the output multiplexed transmitter in terms of power, area and speed, its characteristic of having a full swing signalling capability, which is like the bootstrapped techniques, results in the increase in power consumption. In addition, the power saving of the parallelism or multiplexing techniques are strongly dependent on the voltage scaling.

37 Di Φi-1 Φi Φi-1 Φi Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd 50Ω outn outp

4:1 multiplexer Pre-amplifier Output driver Di

Figure 2.9: The input multiplexed transmitter [33].

Compared to the full-swing signalling schemes such as the bootstrapping technique and the parallelism technique, there are several low-power high-speed on-chip signalling schemes which have better power-delay performance; these are the low-swing on-chip signalling schemes, which will be discussed in the next section.