The satellite integrated receiver decoder

The block diagram in Figure 8.2 represents the main functional blocks of a 1995/96 satellite IRD and their interconnection. It does not necessarily correspond to the partitioning used by all chip mak-ers for manufacture of the ICs. This partitioning can vary substan-tially from supplier to supplier, and depends on the integration level, which increases quickly between two successive hardware generations.

The signals received from the satellite (frequencies ranging from 10.7 to 12.75 GHz) are amplified and down-converted (in two bands) into the 950–2150 MHz range by the low noise converter (LNC) located at the antenna focus, and applied to the IRD’s input.

DigitalTelevision

Figure 8.2 Block diagram of a DVB satellite receiver (1995/96 generation) (the dotted lines represent functions which are sometimes combined).

147

MPEG transport (188 byte packets)

8

16/32 bits or RISC processor

Tuner

The tuner (sometimes called the front end), generally controlled by an I²C bus, selects the required RF channel in the 950–2150 MHz range, converts it into a 480 MHz IF and achieves the required selec-tion by means of a surface acoustic wave filter (SAW); the signal is amplified and coherently demodulated according to the 0^ and 90^ axes to obtain the analog I and Q signals. Recovery of the carrier phase required for demodulation is carried out in combination with the next stages of the receiver which lock the phase and the fre-quency of the local oscillator by means of a carrier recovery loop.

Satellite tuners are nowadays of the zero IF (ZIF) type: the I/Q demodulation is directly performed at the input frequency from the LNB without frequency down-conversion, which allows a significant cost reduction mainly due to the removal of the SAW filter, the required selectivity being performed by means of a low-pass filter integrated in the IC.

Analog-to-digital converter (ADC)

The ADC receives the analog I and Q signals which it converts at twice the symbol frequency F_SYMB(of the order of 30 MHz in Europe).

In most cases, this is done by means of a dual ADC with 6-bit resolution which has to work with a sampling frequency of more than 60 MHz. Here again, the sampling frequency is locked to the symbol frequency by means of a phase locked loop (clock recovery loop).

QPSK

The QPSK block, in addition to its functions of carrier and clock recovery loops mentioned before, carries out the half-Nyquist filter-ing complementary to that applied on the transmitter side to the I and Q signals. Digitized I and Q signals are delivered on 2× 3 or 2× 4 bits of the next functional block (FEC).

Forward error correction (FEC)

The FEC block distinguishes, by means of a majority logic, the 0’s from the 1’s and achieves the complete error correction in

the following order: Viterbi decoding of the convolutional code, interleaving, Reed–Solomon decoding and energy dispersal de-randomizing; the output data are 188 byte transport packets which are generally delivered in parallel form (8 bit data, clock and control signals, of which one generally indicates uncorrectable errors).

The three blocks—ADC, QPSK, and FEC—now form a single integrated circuit (single chip satellite channel decoder).

Descrambler

The DESCR block receives the transport packets and communi-cates with the main processor by a parallel bus to allow quick data transfers. It selects and descrambles the packets of the required pro-gram under control of the conditional access device. This function is sometimes combined with the demultiplexer.

Demultiplexer

The DEMUX selects, by means of programmable filters, the PES packets corresponding to the program chosen by the user.

MPEG

The audio and video PES outputs from the demultiplexer are applied to the input of the MPEG block, which generally combines MPEG audio and video functions and the graphics controller functions required, among other things, for the electronic program guide (EPG). MPEG-2 decoding generally requires at least 16 Mbits of DRAM (sometimes more for decoding 625-line signals, depending on the capabilities of the memory management).

Digital video encoder (DENC)

Video signals reconstructed by the MPEG-2 decoder (digital YUV signals in CCIR 656 format) are then applied to a digital video encoder (DENC) which ensures their conversion into analog RGB+ sync. for the best possible quality of display on a TV set via the

SCART/PERITEL plug and PAL, NTSC, or SECAM (composite and/or Y/C) mainly for VCR recording purposes.

Digital-to-analog converter (DAC)

Decompressed digital audio signals in I²S format or similar are fed to a dual digital-to-analog converter (DAC) with 16 bits or more res-olution which delivers the analog left and right signals.

Microprocessor

The whole system is controlled by a powerful 32 bit RISC micro-processor (P), which controls all the circuitry, interprets user commands from the remote control, and manages the smart card reader(s) and the communication interfaces which are generally available. The software amounts to many hundreds of kilobytes, which are partly located in a flash EPROM in order to permit optional updates during the lifetime of the product (off air or via the communication ports).

The four blocks—DEMUX, MPEG, DENC, and P—are now inte-grated in a single IC, often referred to as a single chip source decoder.

Smart card readers

The conditional access device generally includes one or two of these (one might be for a banking card, for instance). In the case of a detachable conditional access module using the DVB-CI common interface (manifested in the shape of PCMCIA slots), the conditional access circuits and the descrambler are located in the detachable PCMCIA module. The demultiplexer integrated into the IRD receives the packets “in the clear” (descrambled).

Communication ports

The IRD can communicate with the external world (PC, modem, etc.) by means of one or more communication ports. The traditional RS232 (serial) and IEEE1284 (parallel) ports tend to be progressively

replaced by a much quicker USB port. These ports, as well as a telephone line interface (via an integrated modem), are the neces-sary connection points required for interactivity and access to new services (pay per view, teleshopping, access to networks).

8.2.2 The cable integrated receiver decoder