The 32-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter. This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows. The Prescale Counter is incremented on every PCLK. When it reaches the value stored in the Prescale Register, the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK. This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, etc.
14.5.7 Match Registers (MR0 - MR3)
The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register.
3:2 Count Input
Select 00
When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
CAPn.0 (CAP0.0 for TIMER0 and CAP1.0 for TIMER1)
00
01 CAPn.1 (CAP0.1 for TIMER0 and CAP1.1 for TIMER1) 10 CAPn.2 (CAP0.2 for TIMER0 and CAP1.2 for TIMER1) 11 CAPn.3 (CAP0.3 for TIMER0 and CAP1.3 for TIMER1)
Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
7:4 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
NA
Table 176: Count Control Register (CTCR, TIMER0: T0CTCR - address 0xE000 4070 and TIMER1: T1CTCR - address 0xE000 8070) bit description
Bit Symbol Value Description Reset
14.5.8 Match Control Register (MCR, TIMER0: T0MCR - 0xE000 4014 and
TIMER1: T1MCR - 0xE000 8014)
The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. The function of each of the bits is shown in Table 177.
14.5.9 Capture Registers (CR0 - CR3)
Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture Control Register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on
Table 177: Match Control Register (MCR, TIMER0: T0MCR - address 0xE000 4014 and TIMER1: T1MCR - address 0xE000 8014) bit description
Bit Symbol Value Description Reset
value
0 MR0I 1 Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 0 This interrupt is disabled
1 MR0R 1 Reset on MR0: the TC will be reset if MR0 matches it. 0
0 Feature disabled.
2 MR0S 1 Stop on MR0: the TC and PC will stop and TCR[0]=0 if MR0 matches the TC. 0 0 Feature disabled.
3 MR1I 1 Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 0 This interrupt is disabled
4 MR1R 1 Reset on MR1: the TC will be reset if MR1 matches it. 0
0 Feature disabled.
5 MR1S 1 Stop on MR1: the TC and PC will stop and TCR[0]=0 if MR1 matches the TC. 0 0 Feature disabled.
6 MR2I 1 Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 0 This interrupt is disabled
7 MR2R 1 Reset on MR2: the TC will be reset if MR2 matches it. 0
0 Feature disabled.
8 MR2S 1 Stop on MR2: the TC and PC will stop and TCR[0]=0 if MR2 matches the TC. 0 0 Feature disabled.
9 MR3I 1 Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 0 This interrupt is disabled
10 MR3R 1 Reset on MR3: the TC will be reset if MR3 matches it. 0
0 Feature disabled.
11 MR3S 1 Stop on MR3: the TC and PC will stop and TCR[0]=0 if MR3 matches the TC. 0 0 Feature disabled.
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
14.5.10 Capture Control Register (CCR, TIMER0: T0CCR - 0xE000 4028 and
TIMER1: T1CCR - 0xE000 8028)
The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below, n represents the Timer number, 0 or 1.
Table 178: Capture Control Register (CCR, TIMER0: T0CCR - address 0xE000 4028 and TIMER1: T1CCR - address 0xE000 8028) bit description
Bit Symbol Value Description Reset
value
0 CAP0RE 1 Capture on CAPn.0 rising edge: a sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
0
0 This feature is disabled.
1 CAP0FE 1 Capture on CAPn.0 falling edge: a sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
0
0 This feature is disabled.
2 CAP0I 1 Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event will generate an interrupt. 0 0 This feature is disabled.
3 CAP1RE 1 Capture on CAPn.1 rising edge: a sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
0
0 This feature is disabled.
4 CAP1FE 1 Capture on CAPn.1 falling edge: a sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
0
0 This feature is disabled.
5 CAP1I 1 Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event will generate an interrupt. 0 0 This feature is disabled.
6 CAP2RE 1 Capture on CAPn.2 rising edge: A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC.
0
0 This feature is disabled.
7 CAP2FE 1 Capture on CAPn.2 falling edge: a sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC.
0
0 This feature is disabled.
8 CAP2I 1 Interrupt on CAPn.2 event: a CR2 load due to a CAPn.2 event will generate an interrupt. 0 0 This feature is disabled.
9 CAP3RE 1 Capture on CAPn.3 rising edge: a sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC.
0
0 This feature is disabled.
10 CAP3FE 1 Capture on CAPn.3 falling edge: a sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC
0
0 This feature is disabled.
11 CAP3I 1 Interrupt on CAPn.3 event: a CR3 load due to a CAPn.3 event will generate an interrupt. 0 0 This feature is disabled.
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
14.5.11 External Match Register (EMR, TIMER0: T0EMR - 0xE000 403C; and
TIMER1: T1EMR - 0xE000 803C)
The External Match Register provides both control and status of the external match pins MAT(0-3).
Table 179: External Match Register (EMR, TIMER0: T0EMR - address 0xE000 403C and TIMER1: T1EMR - address0xE000 803C) bit description
Bit Symbol Description Reset
value
0 EM0 External Match 0. This bit reflects the state of output MAT0.0/MAT1.0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this output of the timer can either toggle, go low, go high, or do nothing. Bits EMR[5:4] control the functionality of this output.
0
1 EM1 External Match 1. This bit reflects the state of output MAT0.1/MAT1.1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this output of the timer can either toggle, go low, go high, or do nothing. Bits EMR[7:6] control the functionality of this output.
0
2 EM2 External Match 2. This bit reflects the state of output MAT0.2/MAT1.2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this output of the timer can either toggle, go low, go high, or do nothing. Bits EMR[9:8] control the functionality of this output.
0
3 EM3 External Match 3. This bit reflects the state of output MAT0.3/MAT1.3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this output of the timer can either toggle, go low, go high, or do nothing. Bits EMR[11:10] control the functionality of this output.
0
5:4 EMC0 External Match Control 0. Determines the functionality of External Match 0. Table 180
shows the encoding of these bits.
00
7:6 EMC1 External Match Control 1. Determines the functionality of External Match 1. Table 180
shows the encoding of these bits.
00
9:8 EMC2 External Match Control 2. Determines the functionality of External Match 2. Table 180
shows the encoding of these bits.
00
11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3. Table 180
shows the encoding of these bits.
00
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
NA
Table 180. External match control
EMR[11:10], EMR[9:8], EMR[7:6], or EMR[5:4]
Function
00 Do Nothing.
01 Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 10 Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 11 Toggle the corresponding External Match bit/output.
14.6 Example timer operation
Figure 50 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset. This gives a full length cycle to the match value. The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value.
Figure 51 shows a timer configured to stop and generate an interrupt on match. The prescaler is again set to 2 and the match register set to 6. In the next clock after the timer reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
14.7 Architecture
The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in Figure 52.
Fig 50. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK prescale counter interrupt timer counter timer counter reset 2 2 2 2 0 1 0 1 0 1 0 1 4 5 6 0 1
Fig 51. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
PCLK prescale counter interrupt timer counter TCR[0] (counter enable) 2 2 0 1 0 4 5 6 1 0