Total Ionising Dose

The physical mechanism behind TID is also the creation of electron-hole pairs, which in Silicon Oxide requires 18 eV [Holmes-Siedle and Adams, 2002], where it is the gradual build up of trapped charge in the device’s oxides that cause the effects observed. In the insulating dielectric layers such as gate or field oxides the creation of charge can form semi-permanent charge sheets affecting the conductivity of the semiconductors around it. Trapped charge near the Si -SiO2 interface in the

oxide can be separated into different populations, the trapped charge closest to the interface are volatile and react to changing electric fields while those above are slow reacting and undergo a “ran- dom walk”, both of these populations are susceptible to annihilation through electron tunnelling. Further away from the Si-SiO2 interface, 5 to 20 nm, is the region which contains the majority of

the trapped charge, at this depth electron tunnelling has less of an effect, the net result of this is shown in Figure 2.20. This trapped charge is long lived as they lie 2.5 eV above the SiO2 band

gap, at 9 eV, and thermal processes are unlikely to free the charge, this charge population is also replenished by holes created by ionising radiation which then drifts into this region [Holmes-Siedle and Adams, 2002].

An electric field needs to be present in the gate oxide for electron-hole pairs to separate with the hole drifting towards the Si-SiO2 interface where it may be trapped, in general for worst case

scenario the bias needs to be kept constant, when the bias on a MOS transistor is switched a higher dose is needed before failure. For a nMOS transistor, as the charge builds up the performance of the transistor decreases, starting with performance degradation, an increase in quiescent current and a decrease in switching speed, followed by device failure at higher levels of dose where the transistor is unable to turn off. For pMOS devices, higher voltages are required at the gate to turn the transistor on, eventually, when enough charge has been trapped, the transistor will not be able to turn on. Ionising radiation can also release protons which can then interact with the bonds at the Si-SiO2 interface where the proton bonds with a bound H+ forming H2 and leaving a

positively charged dangling bond, the interface defect [Rashkeev et al., 2001]. This can be seen as a second TID mechanism as it deforms the transistor’s I-V characteristic. Oxide traps and interface defects have different temporal properties where the oxide traps are formed within seconds, while the interface defects require hours to days to form. They also have different annealing properties, where the oxide traps take hours or days to anneal, the interface defects tend to require elevated temperatures to anneal, this process at room temperature has been measured to be in the order of years. Another property for interface defects is that unlike oxide traps they are formed regardless of the device’s bias [Holmes-Siedle and Adams, 2002]. The rate at which the oxide traps anneal is attributed to three mechanisms, where some of the trapped charge relaxes through pathways such as thermal excitation, electron tunnelling or are driven out by the trapped charge’s field. It is these differences in process time-scales that can cause nMOS devices to “rebound”, reversing the voltage shift caused by trapped charge in the oxide, as shown in Figure 2.21. Some nMOS devices have been known to fully recover or even to overshoot (due to interface defects), others are only

Figure 2.21: nMOS and pMOS Vth Shift with Dose [Holmes-Siedle and Adams, 2002]

able to partially recover; as for pMOS devices their performance is further degraded. The rate of annealing does not have a universal trend due to the many variables which affect this process, however in general the process is sped up at higher temperatures.

As devices continue to scale the mode of TID failure has changed, in modern devices failure is no longer the result of a build up of trapped oxide in the gate oxide. In modern devices the gate oxides are <20 nm, at this thickness the majority of the charge trapped is annihilated by tunnel electrons which have a range of ∼6 nm [Holmes-Siedle and Adams, 2002]. In addition the interface traps in thin gate oxides have less of an effect, where an oxide with a thickness of 10 nm only sees an increase of +0.06 V at 100 krad [ASTM, 2012]. In modern CMOS devices, the dominant radiation response is from oxide traps in the field oxide, used to separate transistors, where the oxide traps cause leakage currents in the parasitic Field Oxide Field Effect Transistor (FOXFET) [Holmes-Siedle and Adams, 2002]. Due to their thickness, field oxides are very susceptible to charge build-up, with sufficient charge being built up in this region inversion can be achieved, causing leakage current, at which point the nMOS transistor will conduct with the gate bias below the threshold voltage. This can be seen in Figure 2.22 as well as the FOXFET between neighbouring transistors, in this case a n-well bulk CMOS structure. Some devices have guard bands which are designed to stop leakage current caused by the parasitic FOXFET transistor.

Enhanced Low Dose Rate Sensitivity (ELDRS) is a term applied to both MOS and bipolar devices which exhibit an enhanced degradation when exposed to low dose rates, this was discovered when devices, based on normal ground testing, were deemed to be radiation tolerant but were then found to exhibit degradation in lower dose rate environments such as that seen in orbit. It was found that at high dose rates a population of oxide traps is quickly created, this population then inhibits the creation of interface traps, after irradiation the oxide traps are quickly annealed, this process leaves fewer interface traps and hence the device displays less degradation. Under low dose rates, this population of partially stable trapped charges is is not as large allowing the more stable trapped

(a) Bird’s beak FOXFET [Torres and Flament, 2002] (b) FOXFET between neighbouring transistors

Figure 2.22: FOXFETs in CMOS Structures

(a) Oxide trap populations at high and low dose rates

(b) Interface trap formation

Figure 2.23: Oxide and Interface Trap Variation with Dose Rate [Schrimpf et al., 2008]

charges to form resulting in a stronger radiation response. The paper [Schrimpf et al., 2008] has a detailed look at the mechanisms behind ELDRS, Figure 2.23 details the oxide trap shielding mechanism at high dose and how interface traps are created.