Transceiver hardware setup

The developed design consists of three FPGA boards, XTS daughter boards, SMA cables and host PC.

Figure 3.7 Transceiver hardware setup

XTS daughter boards are attached to HSMC connectors of each SoC Kit. This card converts transceiver channels through a HSMC inteface to SMA connectors. Four transceiver channels are supported by XTS daughter board. More information can be found in the XTS [37]. Present design applies SMA connectors on the XTS board to establish transceiver interconnection between FPGA boards via SMA cables, which are 40 cm length. Figure 3.7 shows how assembled design looks in life . Figure 3.8 introduces interface of the XTS.

In this topology, one of the boards is master board and two are slave boards. The master board generates data and two others by pass it further. In the master boards the sent and received values of control data are compared. The principle of topology is shown in Figure 3.9.

3.2.2 Structure of the system

The presented design perform following actions : at rst of the initializing transceiver design is activated, then data generator send n-bit count value or synchronization word for receiver alignment. User logic in the receiver side processes incoming data

3.2. Transceiver communication 36

Figure 3.8 XTS daughter board.

Figure 3.9 Simplied transceiver design and measures the bandwidth and latency parameters.

The implemented design requires single ended clock input, which is a master refer- ence clock. The Cyclone V SX has on-chip 50 MHz crystal oscillator. This clock drives PLL IP block which generates clocks in 50 MHz to 600 MHz range. The gener-

Figure 3.10 Transceiver PHY Native architecture.

ated clock are driven to the inputs of the clocks of Transceiver PHY IP, Transceiver Reconguration Controller and Reset Controller IP blocks. This Mega cores from Altera are used for implementation transceiver functionality.

Cyclone V Transceiver PHY IPs cores

Transceiver PHY IP, Transceiver Reconguration Controller and Reset Controller Megafunctions provided by Altera are required for implementation transceiver func- tionality. Figure 3.10 shows three blocks with appropriative connections.

• Cyclone V Transceiver Native PHY IP core parameters

Cyclone V Transceiver Native PHY IP is one of the available transceiver con- gurations. All signals are connected directly to the ports, without memory- mapped interfaces, as it implemented in other transceiver IP cores.

Standard data path is available for the Cyclone V device : PMA and PCS. The general congurations for one of the test of executed designs are listed below.

Number of data channels : 1. PMA congurations. Data rate: 1700 MBps. Number of TX PLL : 1.

3.2. Transceiver communication 38

Figure 3.11 Transceiver Native PHY IP conguration. Reference clock frequency : 85 MHz.

Standard PCS congurations :

Standard PCS protocol mode : basic. Standard PCS/PMA interface width : 10.

FPGA fabric/ Standard TX PCS interface width : 8. TX/RX FIFO mode : low latency.

The word aligner operates in one of the following modes. Manual alignment - when user control word alignment. Bit-slip- the word boundaries shifted by inserting latencies.

Automatic synchronization state machine - programmable state machine control word.

• RX word aligner mode : manual. • RX word aligner pattern length : 10.

• RX word aligner pattern (hex) : 17C, K28.5 negative comma is used.

• The Figure 3.11 shows the example of conguration of Transceiver Native

Figure 3.12 Transceiver Master board design.

• Transceiver Reconguration Controller IP core allows to collaborate and re-

conguration the signals PHY IP core. In the congurations of this IP block the total number of recongurable interfaces needed to provide.

• Transceiver PHY Reset Controller IP core makes power up and initializing of

reset sequences for correct transceiver design.

3.2.3 Send/receive data logic

• Master board. The design programmed to the Master device supports all

function to process a data: generating, controlling, sending and receiving. Figure 3.12 provides implemented design for Master board.

Send data block generates a data and is driven by clock output from the Native PHY. The divide factor is assigned to one, thus clock frequency is the same as reference clock.

First of all, data generator sends control characters to the data channel to establish a synchronization of data to receiver. This pattern is known by

3.2. Transceiver communication 40 receiver part and compares with the received characters with predened value in the Transceiver Native PHY IP Core. If incoming data is corrupted and is not equal to the specied one, then signal is delayed until sampling clock edge is placed exactly in the middle of two transitions. This process guarantees the correct byte alignment of the received data. For each of the channels calibration is required [7].

Pattern and error detect, disparity control and type of data signals from Mega- Function ports deliver information about current status of the data from the receiver. When pattern-detect and control signals are asserted then align- ment pattern BC is correctly received by the receiver side. Data generator block observes continuously status information and ensures that alignment is completed to continue generate and send packets of the data.

The transmitted data is driven to the input of the Native PHY.

Data stream ows through the boards and is received back to the input of the receiver part of the Master device. Receive data block gets data from Transceiver Native PHY IP and processes to measure the performance of the system.

• Slave board. In the design programmed to the slave device the data is driven

from the Native PHY IP receiver to Receive data block. Figure 3.13 shows main components of this design Also received values are transmitted to the Data from RX block, which passes data back to Transceiver Native PHY IP transmitter.