Chapter 5: D iam ond depletion-mode transistors 73
5.0
Introduction
The majority of the diamond transistors fabricated to date, have been on single crystal diamond: natural, synthetic and homoépitaxial material. The use of single crystalline material has inevitably produced extremely encouraging results that show great potential in replacing conventional semiconductors such as silicon in high temperature and high power applications [5.1, 5.2, 5.3]. However, the drawbacks in using these substrates include: the immense cost, the limited workable surface area, and the variability in the properties of one sample to another.
The ability to synthesise diamond using chemical vapour deposition (CVD) techniques has caused a renewed proliferation in diamond research. The cost of growing CVD diamond is much lower (facilities used for HPHT growth are very big and expensive) and can be grown on a variety of substrates over many inches in diameter. The diamond produced by CVD is polycrystalline, and varies from a ’cauliflower’ morphology (with grain sizes ranging from nanometres to microns) to a rough, randomly oriented material (displaying grain sizes of 1-
100|im). The use of polycrystalline diamond for fabricating electronic devices was initially faced with many problems, e.g high leakages and low mobility [5.4, 5.5]. Recently, the technique known as bias-enhanced nucléation (BEN) has produced CVD diamond with morphology that is not rough and randomly oriented, but is textured, with grains showing a particular crystal orientation, such as (100) that are almost aligned to each other [5.6]. Current understanding of polycrystalline diamond is much greater and more extensive, and has resulted in successful fabrication of devices on this material.
5.1
Objective
To design and fabricate a polycrystalline diamond transistor for high temperature applications. Electrical studies on single crystal diamond suggest it to be a superior semiconductor for high temperature, high power and high radiation applications [5.7].
5.2
Design
When designing and fabricating transistors from diamond, a few fundamental issues that have to be addressed include, the doping of diamond and the creation of contacts. Intrinsic
Chapter 5: Diamond depletion-mode transistors 74
Arbitrary Units
1100 1200 1300 1400 1500
Delta wavenumber (cm ')
Fig. 5.1 Scanning electron micrographs (SEMs) showing the surface morphology of: (a) HI 1, (b) H12, (c) H13-4 (d) H13-5
Chapter 5: Diam ond depletion-mode transistors 75
diamond is an insulator, its wide band gap prevents excessive leakage currents from being created, but it also makes it difficult to realise ohmic contacts on it. Doping diamond into a useful semiconductor is difficult because the dopants introduced into the diamond lattice create deep acceptor/donor levels within the band gap.
The diamond substrate used here for the fabrication of the transistors is polycrystalline, this material contains many grain boundaries which have lots of dangling bonds and traps. To investigate the effect of grain boundaries on the electrical properties of the material and hence, the transistor performance, four significantly different polycrystalline substrates were used. The morphology ranged from ‘cauliflower’ to rough and randomly oriented, as shown in Fig. 5.1.
5.2.1
Transistor type
There are two main types of transistors, bipolar junction transistors (BJTs) and field-effect transistors (FETs). The operation of bipolar transistors as its name implies relies on both electrons and holes, while field-effect transistors are unipolar devices and depend on only one type of carrier, either electrons or holes. A semiconductor with an excess of electrons is known as n-type, while an excess of holes gives p-type material.
Dopants can be incorporated into the diamond lattice by in-situ doping during diamond growth or by ion implantation, where the dopant is converted into an ion and accelerated into the diamond substrate. P-type diamond can be readily achieved, but n-type doping has yet to be convincingly demonstrated. Therefore, the only viable approach is to fabricate a unipolar transistor, i.e. a field-effect transistor. Field-effect transistors come in the form of bulk or planar structures. Consider the planar structure, basically, there are two types of planar FETs, which can be distinguished from each other by their different gate structures: MESFETs (MEtal Semiconductor FETs) and Metal Insulator Semiconductor FETs.
The gate of a MESFET is formed by a metal-semiconductor contact, which must be kept under reverse bias, otherwise leakage current will flow through the gate. The function of the reverse biased gate is to present a Schottky barrier that is sufficiently high to prevent excessive gate leakage currents from occurring. Therefore, the leakage current depends on
Chapter 5: Diam ond depletion-mode transistors 76
the quality of the metal-semiconductor interface. If the contact is in the presence of a high concentration of surface states, tunnelling will occur via these states from the conduction/valence band. The dependence of the Schottky contact on the surface property increases the difficulty in fabricating MESFETs reproducibly. At higher temperatures, the Schottky barrier may be inadequate in preventing leakage currents, as the temperature is increased, carriers are excited to higher energies where they will ‘see’ a thinner and lower barrier. Consequently, carriers will be able to tunnel through the metal gate, this is known as thermionic field emission.
This problem can be circumvented by inserting an insulating layer between the metal and the semiconductor, this will significantly reduce the leakage current as it is now a function of the insulator's properties. This structure is what defines a MISFET. Consequently, MESFETs are inherently leakier than MIS FETs for high temperature applications. Based on the above arguments, a p-type MISFET design was chosen.
5.2.2
Structure of the MISFET
5.2.2.1
Choosing the gate insulator
The most commonly used insulator is silicon dioxide (Si0 2). Silicon (Si) and silicon dioxide
technology is a mature field, both its material and electrical properties have been well characterised. A typical Si MISFET would have a SiOi gate because it can be easily grown on Si by oxidising the Si surface or by means of chemical vapour deposition (CVD).
For this project, intrinsic diamond (nominally undoped) was chosen as opposed to Si0 2-
Growing intrinsic diamond on top of diamond instead of Si0 2 on diamond should give a
higher quality interface with fewer interface traps (as seen in Fig. 5.2) because there is no lattice mismatch [5.8]. Indeed, previous studies which have utilised a Si0 2 gate have suffered
from high gate leakage currents due to the poor quality of the Si0 2-diamond interface formed
Chapter 5: Diamond depletion-mode transistors 77 M e t a l Undoped Diamond Boron Doped Diamond M e t a l M e t a l Boron D oped Diamond Met al
Fig. 5.2 Schematic diagram of (a) MIS and (b) MOS structures [5.8]
5 .2 .2 .2 T h ic k n e s s o f d ia m o n d la y e r s a n d th e ir d o p in g l e v e ls
D ia m o n d is the densest material to be found (interatomic spacing of 0 . 154nm) m aking it physically difficult to incorporate dopants into its lattice. Techniques such as in-situ doping during growth and ion implantation have been used successfully, but each has its own problem . H eavy in-situ doping during growth creates defects and stress in the form ation of the d iam ond lattice, which will affect the lattice spacing and crystallinity of the next growth layer.
H ow ever, has been shown from Ram an spectra that the addition of boron during d iam ond grow th to light or m oderate concentrations can improve the quality o f the d iam ond film [5.11]. W hen doping is carried out using ion implantation, the dam age in the lattice follows that o f the io n ’s trajectory path. The damage can be annealed out, and hence the lattice can
revert to its original diam ond structure. However, this is not a trivial task because the
effectiveness of the anneal depends on both the implantation and anneal temperature. N evertheless, ion implantation allows the doping to be well defined, whether it is in thin (m icrons) layers or small areas.
A cross-section o f a p-type diam ond M IS FE T is shown in Fig. 5.3e. It consists o f three layers o f diam ond grown on a Si wafer by m icrow ave plasm a enhanced C V D (M P E C V D ): a p -type (boron-doped) layer is sandwiched between two intrinsic ones.
Chapter 5: Diamond depletion-mode transistors 78
(a) Intrin sic d ia m o n d (i-D) layer g ro w n on Si acts as a b u ffer layer.
B oron is im planted to fo r m the p -type channel (p -D), 0 .7 - 3 .5 p m deep;
peak level, 4x1018 - 5 x 1 0 2 0 I IB atoms/cin3. Intrinsic d ia m o n d gate g ro w n on top, 0 .3 - 4 p m . A lig n m e n t m arks are d efined at the e d g e s (not s h ow n).
( b ) P h o to r e sis t spun o n to surface.
A re a s u n d e r the so urce and drain o p e n e d for a d o u b le im plant o f ■ >B, 160 keV an d 90 keV , d ose o f K)i-Vcm2.
i-D
kC) H eav y d o p in g facilitates the form ation o f o h m ic conta c ts.
i-D p-D i-D
( d ) T i/ A g / A u (titan ium, silver, gold) is ev a p o ra te d on top o f the im planted regions.
_ P -D i-D
(G) A u is ev a p o ra te d to form the source, drain and gate conta c t pads.
A n n e a li n g in air @ 430»C for 1 h r p ro d u c e s o hm i c c o n ta c ts via T iC fo n n a tio n . G a te ' S o u rc e i-D i-D
Chapter 5: D iam ond depletion-mode transistors 79
The intrinsic diamond adjacent to the Si acts as a buffer layer to prevent leakage currents from traversing the diamond-Si interface. In order to achieve this, the buffer layer must be quite thick, of the order of a few microns. The active channel (the p-type layer) needs to be thin and lightly doped (therefore, ion implantation was chosen to dope the channel) to facilitate pinch-off (leading to saturation) and cut-off of the channel current; a channel of
0.5|Lim doped with B (boron) to ~5 x 10^^/cm^ is suggested.
The function of the insulating gate material is to act as a medium for transmitting the electric field, which controls the conduction between the source and the drain without passing any current. Ideally, the gate insulator should have zero conductance and a very small capacitance to minimise dissipation and storage effects in the gate circuit. From equation 5.1 it can be seen that a small capacitance can be achieved by having a thick insulating layer with a small area and a low dielectric constant.
c = ^ ( 5 . 1 )
a
C = capacitance, e = dielectric constant, A = area, d = thickness of the material
It is also preferable to have a small control voltage, but the demands of this requirement conflicts with the previous one, i.e. a thin insulating layer with a large dielectric constant and area is preferred here. Therefore, a compromised thickness of 0.5|xm was chosen.
S.2.2.3
Contacts
The channel is entirely covered by the insulating diamond gate, therefore, it is necessary to find some means to contact the channel. This can be accomplished by a heavy double implant of^^B ions through the source and drain regions. The double implant also serves to create low resistance areas for the formation of ohmic contacts [5.12].
As-grown diamond has shown to have a conductive surface layer, which is dependent on the conditions in the final stages of deposition. This in turn will determine whether the conductivity seen is a result of non-diamond carbon, such as graphite and other forms of sp^ C, or whether it displays p-type conductivity due to hydrogen incorporation near the surface
Chapter 5: Diamond depletion-mode transistors 80
[5.13]. Conduction layers of this kind would be detrimental to the operation of the devices fabricated here. Therefore, it is critical that the diamond surface is cleaned, prior to device fabrication to remove this source of leakage current. This can be achieved by cleaning the substrate in a highly oxidising acidic solution at high temperatures.
Specific contact resistances have been shown to decrease when a carbide-forming metal is used [5.14]. In order to form the carbide it is necessary to anneal the contact. One such metal is titanium (Ti). Titanium is easily oxidised in air, especially when operating at high temperatures, therefore, it is important that another metal is evaporated on top to prevent oxidation from occurring. Gold (Au) is an inert and low resistance metal which is commonly used as a capping layer on top of the titanium. However, the Ti will diffuse into the gold and increase the resistivity of the contact. This problem can be prevented by using a diffusion barrier between the two materials, suitable candidates include silver (Ag) and platinum (Pt). Unfortunately, not only does the Ti diffuse vertically into the gold, it has been shown [5.15] that it also diffuses laterally along the substrate, out of its pre-defined boundary.
S.2.2.4
Resulting structure
The source and drain are metallised with Ti-Ag-Au and have a separation of 50|im.
Gold is thermally evaporated to form the gate, which has a gate length of BOjim and a gate width of 100p.m giving an effective gate area of BOOOjitm^. Fig. 5.4 shows an optical micrograph and schematic diagram of a MISFET and its dimensions.
Field-effect transistors can be designed to have either an enhancement-mode or depletion mode configuration, which are also commonly known as normally-off and normally-on transistors respectively. The MISFETs here are depletion-mode transistors. This means that a channel is incorporated into the substrate at the time of fabrication, therefore, with no gate bias, Vgg, the application of Vds across the source and the drain will cause a current, I^^ to flow. As is made increasingly positive (for p-type FETs), holes are repelled away from
the channel, forming a depletion region and resulting in a decrease in I^g. The opposite
happens when is made increasingly negative, holes are attracted towards the channel,
increasing the hole density and I^g. The opposite is true for an enhancement-mode transistor,
Chapter 5: Diamond depletion-mode transistors (a) G ate 30^111 Source 15nm ^ D rain
Ion implanted regions lOxlOOjim
50gm 100|im
(b)
Fig. 5.4 (a) Optical micrograph (b) Schematic of a diamond MISFET
consequently, the PET is normally-off. Therefore, a negative is required to turn-on a p-
Chapter 5: D iam ond depletion-mode transistors 82
5.3
Experimental methods
Four sets of transistors were fabricated: Set I: sample HI 1
Set n: sample H I2 Set rU: sample H I3-4 Set IV: sample H I3-5.
The same fabrication procedure was carried out on all four sets.