True IDE Mode Addressing

When this product is set to True IDE mode, I/O is decoded as follows:

True IDE Mode I/O Decoding

CE2# CE1# A2 A1 A0 IORD# = 0 IOWR# = 0 Note

1 0 0 0 0 Even RD Date Even WR Data 1 0 0 0 1 Error Register Features 1 0 0 1 0 Sector Count Sector Count 1 0 0 1 1 Sector No. Sector No. 1 0 1 0 0 Cylinder Low Cylinder Low 1 0 1 0 1 Cylinder High Cylinder High

1 0 1 1 0 Select Card/Head Select Card/Head

1 0 1 1 1 Status Command

1 1 1 1 0 Alt Status Device Control 1 1 1 1 1 Not used Reserved

3.5. ATA Register

3.5.1. Data Register (Address 1F0{170}; offset 0,8,9)

Data Register is a Register of 16 bit and used for transfer data block between Data Buffer and Host.

This register is overlap to Error register.

Data Register CE2# CE1# A0 Offset Data Bus Word Data Register 0 0 x 0,8,9 D15-D0 Even Data Register 1 0 0 0,8 D7-D0

Odd Data Register 1 0 1 9 D7-D0 Odd Data Register 0 1 x 8,9 D15-D8 Error/Feature Register 1 0 1 1,Dh D7-D0 Error/Feature Register 0 1 x 1 D15-D8 Error/Feature Register 0 0 x Dh D15-D8

3.5.2. Error Register (Address 1F1{171}; Offset 1,0Dh read only)

When the bit 0 of Status Register indicates an error, an additional information concerning the cause of error is recorded in this Register. The bit is defined as follows:

When CE1# is “High”, CE2# is “Low” and reading operation is executing to offset 0, it is possible to access to this register through data bit D15 – D8.

D7 D6 D5 D4 D3 D2 D1 D0 BBK UNC 0 IDNF 0 ABRT 0 AMNF Bit 7 (BBK) This bit will set when bad block is detected.

Bit 6 (UNC) This bit will set when uncorrectable error has occurred. Bit 5 This bit is set to 0

Bit 4 (IDNF) Requested ID is not correct, or sector ID is not found. Bit 3 This bit is set to 0

Bit 2 (ABRT) This bit will set when command is cancelled, or invalid command is issued because of Adapter status, i.e. “Not Ready”, “Write Fault”, etc. Bit 1 This bit is set to 0

Bit 0 (AMNF) This bit will set when general error has occurred.

3.5.3. Feature Register (Address 1F1{171}; offset 1, 0Dh write only)

sector will reserved. If command is completed correctly, register value will be 0 when all process completed. If command is not completed correctly, number of sectors to be transferred to complete command will be recorded.

3.5.5. Sector Number Register (Address 1F3{173}; offset 3)

In this Register, the starting Sector number of this product which will be accessed by the subsequent command or bit 7-0 of Logic Block Address (LBA) is stored.

3.5.6. Cylinder Low Register (Address 1F4{174}; offset 4)

In this Register, Low 8 bit of starting Cylinder address or bit 15-8 of Logic Block Address is stored.

3.5.7. Cylinder High Register (Address 153{175}; offset 5)

In this Register, High 8 bit of starting Cylinder or bit 23-16 of Logic Block Address is stored.

3.5.8. Drive Head Register (Address 1F6{176}; offset 6)

This Register is used for the selection of Drive or Head. Also it is used for selecting LBA addressing in place of cylinder/Head/Selector addressing. The bit is defined as follows:

D7 D6 D5 D4 D3 D2 D1 D0

1 LBA 1 DRV HS3 HS2 HS1 HS0

Bit 7 This bit is set to 1.

Bit 6 Flag to select Cylinder/Head/Sector(CIS) or Logical Block Address Mode(LBA). If LBA=0, Cylinder/head/Sector will be selected. If LBA=1, Logical Block Address will be selected. In Logical Block Mode, Logical Block Mode will explained as follows.

LBA07 – LBA00: Sector Number Register D7 – D0 LBA15 – LBA08: Low Cylinder Register D7 – D0 LBA23 – LBA16: High Cylinder Register D7 – D0 LBA27 – LBA24: Drive/Head Register Bit HS3 – HS0 Bit 5 This bit is set to 1.

Bit 4(DRV) Indicate Drive No. In case DRV=0, Drive 0 is selected, if DRV=1, Drive 1 is selected. This Adapter is set to Card 0 or Card 1 by using copy field of PC card socket copy set register.

Bit 3(HS3) Under operation of Cylinder/Head/Sector mode, indicate bit 3 as head number. Under operation of Logical Block Address mode, indicate LBA bit 27.

number.

Under operation of Logical Block Sector mode, indicate LBA bit 26. Bit 1(HS1) Under operating at Cylinder/Head/Sector mode, indicate bit 1 as head

number.

Under operation of Logical Block Sector mode, indicate LBA bit 25. Bit 0(HS0) Under operating at Cylinder/Head/Sector mode, indicate bit 0 as head

number.

Under operation of Logical Block Sector mode, indicate LBA bit 24.

3.5.9. Status Register (Address 1F7{177}; offset 7)

This Register records the status of this product. When the content in this Register is read, the reserved interruption is cleared.

D7 D6 D5 D4 D3 D2 D1 D0

BUSY RDY DWF DSC DRQ CORR 0 ERR

Bit 7(BUSY) If adapter is accessing to command buffer or register and disable to access from Host, this bit is set. In case this bit is 1, other bit in this register are invalid.

Bit 6(RDY) This bit indicate that Host can execute operation or not. This bit will be cleared when power on, and keep this condition until the Adapter will be ready to receive command.

Bit 5(DWF) This bit indicate that writing error has occurred. Bit 4(DSC) This bit means Adapter is ready to operate.

Bit 3(DRQ) This bit request data when it is necessary to exchange information between Host through data register.

Bit 2(CORR) When data error have occurred, and this data was corrected, this bit will set.

In this case, multi-sector reading operation will not be cancelled. Bit 1(IDX) This bit is set to 0 always.

Bit 0(ERR) This bit will set if some error have occurred on command execution. Additional information is contained in bit of error register.

D7 D6 D5 D4 D3 D2 D1 D0

x X x x 1 SW Rst IEn# 0

Bit 7 This bit will neglect. Bit 6 This bit will neglect. Bit 5 This bit will neglect. Bit 4 This bit will neglect. Bit 3 This bit will set 1.

Bit 2(SW Rst) This bit will set 1 if execute AT Disk Controller Soft Reset Operation with this Adapter. PC card structure register (2.5.2 – 2.5.5) will not be changed. The Adapter will continue Reset condition until this bit is changed to 0.

Bit 1(-IEn) In case this bit is 0, it is possible to interrupt. Incase this bit is 1, interrupt from Adapter is invalid. This bit is set 1 when power on or reset.

Bit 0 This bit is neglect always.

3.5.12. Command Register