There are a number of covergroups required to check the UART interrupt functional coverage.
Interrupt enable coverage
This covergroup is sampled every time an interrupt occurs. It checks the state of the IER register, decoding the bit patterns in order to determine which interrupt combinations have not been enabled.
covergroup int_enable_cg() with function sample(bit[3:0] en);
option.name = "interrupt_enable";
option.per_instance = 1;
INT_SOURCE: coverpoint en { bins rx_data_only = {4'b0001};
bins tx_data_only = {4'b0010};
bins rx_status_only = {4'b0100};
bins modem_status_only = {4'b1000};
bins rx_tx_data = {4'b0011};
bins rx_status_rx_data = {4'b0101};
bins rx_status_tx_data = {4'b0110};
bins rx_status_rx_tx_data = {4'b0111};
bins modem_status_rx_data = {4'b1001};
bins modem_status_tx_data = {4'b1010};
bins modem_status_rx_tx_data = {4'b1011};
bins modem_status_rx_status = {4'b1100};
bins modem_status_rx_status_rx_data = {4'b1101};
bins modem_status_rx_status_tx_data = {4'b1110};
bins modem_status_rx_status_rx_tx_data = {4'b1111};
illegal_bins no_enables = {0}; // If we get an interrupt with no enables it's an error }
endgroup: int_enable_cg
Interrupt source coverage
This covergroup checks that all possible interrupt status conditions have been sampled. It crosses the content of the IER with the IIR, and also filters conditions which cannot occur. The ignore_bins in the cross ensure that if an interrupt is disabled then interrupt ids of that type are ignored in the cross.. It is sampled when there is an interrupt followed by a read from the IIR register.
covergroup int_enable_src_cg() with function sample(bit[3:0] en, bit[3:0] src);
option.name = "interrupt_enable_and_source";
option.per_instance = 1;
IIR: coverpoint src {
UART example covergroups 66
illegal_bins invalid_src = default;
}
IEN: coverpoint en {
bins rx_data_only = {4'b0001};
bins tx_data_only = {4'b0010};
bins rx_status_only = {4'b0100};
bins modem_status_only = {4'b1000};
bins rx_tx_data = {4'b0011};
bins rx_status_rx_data = {4'b0101};
bins rx_status_tx_data = {4'b0110};
bins rx_status_rx_tx_data = {4'b0111};
bins modem_status_rx_data = {4'b1001};
bins modem_status_tx_data = {4'b1010};
bins modem_status_rx_tx_data = {4'b1011};
bins modem_status_rx_status = {4'b1100};
bins modem_status_rx_status_rx_data = {4'b1101};
bins modem_status_rx_status_tx_data = {4'b1110};
bins modem_status_rx_status_rx_tx_data = {4'b1111};
illegal_bins no_enables = {0}; // If we get an interrupt with no enables its an error }
ID_IEN: cross IIR, IEN {
ignore_bins rx_not_enabled = binsof(IEN) intersect{4'b0010, 4'b0100, 4'b0110, 4'b1000, 4'b1010, 4'b1100, 4'b1110} && binsof(IIR) intersect{4};
ignore_bins tx_not_enabled = binsof(IEN) intersect{4'b0001, 4'b0100, 4'b0101, 4'b1000, 4'b1001, 4'b1100, 4'b1101} && binsof(IIR) intersect{2};
ignore_bins rx_line_status_not_enabled = binsof(IEN) intersect{4'b0001, 4'b0010, 4'b0011, 4'b1000, 4'b1001, 4'b1010, 4'b1011} && binsof(IIR) intersect{4'hc, 6};
ignore_bins modem_status_not_enabled = binsof(IEN) intersect{4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111} && binsof(IIR) intersect{0};
}
endgroup: int_enable_src_cg
UART example covergroups 67
Receive FIFO threshold interrupt coverage
The receive FIFO threshold level is determined by bits [7:6] of the FCR register. When a receive threshold interrupt occurs, word format is crossed with the FCR bits to ensure that all possible combinations occur. It is sampled when an interrupt occurs followed by a read from the IIR register that indicates a FIFO threshold interrupt.
covergroup rx_word_format_int_cg() with function sample(bit[5:0] lcr, bit[1:0] fcr);
option.name = "rx_word_format_interrupt";
option.per_instance = 1;
WORD_LENGTH: coverpoint lcr[1:0] { bins bits_5 = {0};
bins bits_6 = {1};
bins bits_7 = {2};
bins bits_8 = {3};
}
STOP_BITS: coverpoint lcr[2] { bins stop_1 = {0};
bins stop_2 = {1};
}
PARITY: coverpoint lcr[5:3] {
bins no_parity = {3'b000, 3'b010, 3'b100, 3'b110};
bins even_parity = {3'b011};
WORD_FORMAT: cross WORD_LENGTH, STOP_BITS, PARITY, FCR;
endgroup: rx_word_format_int_cg
UART example covergroups 68
Receive Line Status interrupt coverage
This covergroup is sampled when a line status interrupt occurs followed by a read from the LSR register.
covergroup lsr_int_src_cg() with function sample(bit[7:0] lsr);
option.name = "lsr_int_src_cg";
option.per_instance = 1;
LINE_STATUS_SRC: coverpoint lsr[4:1] { bins oe_only = {4'b0001};
bins pe_only = {4'b0010};
bins fe_only = {4'b0100};
bins bi_only = {4'b1000, 4'b1100, 4'b1010, 4'b1100}; // BI active discounts pe & fe bins bi_oe = {4'b1001, 4'b1101, 4'b1011, 4'b1101}; // BI active discounts pe & fe bins oe_pe = {4'b0011};
There are a few things to note about the bins in this covergroup:
• If a Break occurs, then it is also likely to create framing and parity errors
• The receive line status interrupt enable also enables the RX timeout, this will not be detected by this covergroup which is why there is a no_ints bin
Modem Status interrupt coverage
The modem status interrupt can be caused by one of four status bits becoming true, this covergroup checks for all four bits being active and also the error condition where none are active but a modem status interrupt has occurred. The MSR conditions are crossed with the MCR loopback bit since they can be generated in normal and loopback mode. This covergroup is sampled when a modem status interrupt occurs followed by a read from the MSR.
covergroup modem_int_src_cg() with function sample(bit[4:0] src);
option.name = "modem_int_src_cg";
option.per_instance = 1;
MODEM_INT_SRC: coverpoint src[3:0] { wildcard bins dcts = {4'b???1};
wildcard bins ddsr = {4'b??1?};
wildcard bins teri = {4'b?1??};
wildcard bins ddcd = {4'b1???};
illegal_bins error = {0};
UART example covergroups 69
LOOPBACK: coverpoint src[4] { bins no_loopback = {0};
bins loopback = {1};
}
MODEM_INT_CAUSE: cross MODEM_INT_SRC, LOOPBACK;
endgroup: modem_int_src_cg
Note that the fidelity of this covergroup is reduced since wildcard bins are used to check that each of the MSR interrupt source bits is seen to be active true, rather than all combinations. The reasoning behind this is that each bit is orthogonal to the other, and that therefore there is no functional relationship between them.