Understanding the ADC

The simplicity of the physical circuit has its cost in code complexity. Using this peripheral requires initialization and configuration. On the ATmega644p, there are 5 registers involved in the use of the ADC. Here is a brief description of each register. Further, more detailed information can be found in section 20.9 Register Description of the data sheet [11].

ˆ ADMUX - ADC Multiplexer Selection Register

Within the ADC are several multiplexers which are controlled by the bit fields in this register. These include the selection of the reference voltage (REFS1:0) as well as the various channel and gain selections (MUX4:0). This register also contains the justification of the result within the ADCW register (ADLAR).

ˆ ADCSRA - ADC Control and Status Register A

This is the first of two registers responsible for controlling the ADC and making available to the programmer various bits of status information. This includes, but is not limited to, enabling the ADC, triggering conver- sions and controlling interrupts. Additionally, this register controls the selection of a clock prescaler for the ADC. This prescaler causes the ADC clock to run several times slower than the system clock, and is necessary because in order to obtain the full 10-bit precision the ADC must run at a clock frequency between 50kHz and 200kHz.

ˆ ADCW - The ADC Data Register

This register is a 16-bit register made by the combination of ADCL and ADCH. While the datasheet only lists the component registers, ADCW is defined in the header files for the ATmega644p, and is very useful in that it precludes the necessity of manually joining the registers to obtain the full value. Additionally, it is required that when using ADCL and ADCH that ADCL be read first. Reading ADCW takes care of this requirement as well.

ˆ ADCSRB - ADC Control and Status Register B

register. This bit field controls the source for auto triggered comparisons. Auto triggering allows for performing analog conversions at times specified by certain events rather than at specific points in the code. These events could be based on time or an external event. It is also possible to have the ADC begin conversions as soon as the previous one finishes.

ˆ DIDR0 - Digital Input Disable Register 0

The use of this register is completely optional and is used to reduce power consumption. Each bit of this register corresponds to one of the eight ADC input pins. When a given bit is set, the corresponding pin’s digital input capabilities are disabled and the PINA register will always read a 0 for that bit.

Each of these registers corresponds to a physical device inside the ADC. Four of them (DIDR0 is left out as it appears in the DIO logic) appear across the top of figure 4.3, which is a schematic of the internal workings of the ADC. The values of each bit in the registers are transmitted in parallel to the other devices in the ADC. These are the lines exiting and entering the bottom of the register boxes in the schematic. These signals control the other devices, causing the ADC to behave as desired. ADCSRB only controls auto triggering, so its logic is included in figure 20-2 of the data sheet, rather than this one.

There are two sections of this schematic that deserve additional attention. These are the reference selection and the signal selection.

Reference selection

When configuring a progressive-approximation ADC such as the one in the ATmega644p, the ADC must have some reference value to compare to. This voltage is supplied by the portion of the ADC found in figure 4.4. There are four options for the voltage source for the comparator which are selected between using the REFS1:0 bits of the ADMUX register. These options are AVCC, which is an external pin that should be connected to the voltage that the microcontroller is running at, AREF, which is an externally supplied voltage, and the two internally supplied voltages of 1.1V and 2.56V. The first three of these options are selected through a multiplexer. The final choice on whether it is the output of the multiplexer or the voltage supplied at AREF is used is determined by the switch. If the switch is engaged the multiplexer output is connected to the AREF pin and supplied the digital-analog converted (DAC), otherwise only AREF is connected to the DAC. If one of the three sources chosen by the multiplexer is used, it is best to connect AREF to ground using a capacitor to reduce electrical noise, which may result in inconsistencies.

The selected voltage is used to power a DAC. This DAC can then produce voltages in the range of 0V to the selected reference in 210 increments. The output of the DAC is used in the comparator to determine the analog voltage that the ADC is working on.

Figure 4.3: Schematic of the ATmega644p ADC. Found in section 20.2 of the datasheet.[11]

Signal selection

The other section of the ADC that deserves attention is the signal selection. This portion determines what signal is actually converted into a digital value. This value can either stem from one of the eight external ADC pins, which are the pins of port A, ground, or an internally created 1.1V reference. The ground and 1.1V reference voltages are generally used to calibrate the ADC and ensure that it gives the expected value. All these options are fed into the positive input multiplexer, and one of them is selected depending on the status of the MUX4:0 bits in the ADMUX register. This voltage is used both as the positive input to the gain amplifier, and as one of the inputs to another multiplexer discussed below. The first three external ADC pins (ADC2:0) are also connected to another multiplexer. This is the negative input multiplexer which allows for differential conversions. In this case the signal selected by the negative input multiplexer is subtracted from the signal selected by the positive input multiplexer by the gain amplifier. This amplifier can optionally multiply this difference by 10 or by 200. The result of this subtraction and optional multiplication is then used as the second input to the afore mentioned final multiplexer.

Figure 4.4: Reference voltage selection schematic. Excerpt from figure 4.3.

Figure 4.5: Signal selection schematic. Excerpt from figure 4.3.

The unlabeled multiplexer on the right side of figure 4.5 determines whether the signal directly from the positive input multiplexer is used (called a single- ended input) or if the result of the subtraction and multiplication is used (called a differential input). The result of this selection is what is passed on to the progressive-approximation circuitry. For additional information regarding the values stored in ADMUX for each of these options, as well as the limits and ca- pabilities of the peripheral refer to the ADC portion of the microcontroller’s datasheet.