transmitter (USART) . . . 942
27.1 Introduction . . . 942
27.2 USART main features . . . 942
27.3 USART extended features . . . 943
27.4 USART implementation . . . 944
27.5 USART functional description . . . 944
27.5.1 USART character description . . . 947 27.5.2 Transmitter . . . 948 Character transmission. . . .949 Single byte communication. . . .950 Break characters . . . .951 Idle characters . . . .951Contents RM0364
Start bit detection . . . .951 Character reception . . . .953 Break character . . . .953 Idle character . . . .953 Overrun error . . . .954 Selecting the clock source and the proper oversampling method . . . .954 Framing error . . . .957 Configurable stop bits during reception . . . .957 27.5.4 Baud rate generation . . . 958 How to derive USARTDIV from USARTx_BRR register values . . . .958 27.5.5 Tolerance of the USART receiver to clock deviation . . . 960 27.5.6 Auto baud rate detection . . . 961 27.5.7 Multiprocessor communication . . . 962 Idle line detection (WAKE=0) . . . .962 4-bit/7-bit address mark detection (WAKE=1) . . . .963 27.5.8 Modbus communication . . . 964 Modbus/RTU . . . .964 Modbus/ASCII . . . .964 27.5.9 Parity control . . . 964 Even parity . . . .965 Odd parity . . . .965 Parity checking in reception . . . .965 Parity generation in transmission . . . .965 27.5.10 LIN (local interconnection network) mode . . . 965 LIN transmission. . . .966 LIN reception . . . .966 27.5.11 USART synchronous mode . . . 968 27.5.12 Single-wire half-duplex communication . . . 971 27.5.13 Smartcard mode . . . 971 Block mode (T=1) . . . .973 Direct and inverse convention . . . .974 27.5.14 IrDA SIR ENDEC block . . . 976 IrDA low-power mode . . . .977 27.5.15 Continuous communication using DMA . . . 978 Transmission using DMA . . . .978 Reception using DMA. . . .979 Error flagging and interrupt generation in multibuffer communication . . . .980 27.5.16 RS232 Hardware flow control and RS485 Driver Enable . . . 980 RS232 RTS flow control . . . .981 RS232 CTS flow control . . . .981
RM0364 Contents
RS485 Driver Enable . . . .982 27.5.17 Wakeup from Stop mode . . . 982 Using Mute mode with Stop mode . . . .983
27.6 USART interrupts . . . 983 27.7 USART registers . . . 984
27.7.1 Control register 1 (USARTx_CR1) . . . 984 27.7.2 Control register 2 (USARTx_CR2) . . . 988 27.7.3 Control register 3 (USARTx_CR3) . . . 991 27.7.4 Baud rate register (USARTx_BRR) . . . 995 27.7.5 Guard time and prescaler register (USARTx_GTPR) . . . 995 27.7.6 Receiver timeout register (USARTx_RTOR) . . . 996 27.7.7 Request register (USARTx_RQR) . . . 997 27.7.8 Interrupt & status register (USARTx_ISR) . . . 998 27.7.9 Interrupt flag clear register (USARTx_ICR) . . . 1003 27.7.10 Receive data register (USARTx_RDR) . . . 1004 27.7.11 Transmit data register (USARTx_TDR) . . . 1004 27.7.12 USART register map . . . 100528 Serial peripheral interface (SPI) . . . 1007
28.1 Introduction . . . 1007
28.2 SPI main features . . . 1007
28.3 SPI implementation . . . 1008
28.4 SPI functional description . . . 1008
28.4.1 General description . . . 1008 28.4.2 Communications between one master and one slave . . . 1009 Full-duplex communication. . . .1009 Half-duplex communication . . . .1010 Simplex communications . . . .1010 28.4.3 Standard multi-slave communication . . . 1011 28.4.4 Slave select (NSS) pin management . . . 1012 28.4.5 Communication formats . . . 1014 Clock phase and polarity controls. . . .1014 Data frame format. . . .1015 28.4.6 Configuration of SPI . . . 1016 28.4.7 Procedure for enabling SPI . . . 1017 28.4.8 Data transmission and reception procedures . . . 1017Contents RM0364
Sequence handling. . . .1018 Procedure for disabling the SPI . . . .1018 Data packing. . . .1019 Communication using DMA (direct memory addressing) . . . .1020 Packing with DMA . . . .1021 Communication diagrams . . . .1022 28.4.9 SPI status flags . . . 1027 Tx buffer empty flag (TXE) . . . .1027 Rx buffer not empty (RXNE). . . .1027 Busy flag (BSY) . . . .1027 28.4.10 SPI error flags . . . 1028 Overrun flag (OVR). . . .1028 Mode fault (MODF). . . .1028 CRC error (CRCERR) . . . .1028 TI mode frame format error (FRE) . . . .1028 28.4.11 NSS pulse mode . . . 1029 28.4.12 TI mode . . . 1029 TI protocol in master mode. . . .1029 28.4.13 CRC calculation . . . 1030 CRC principle . . . .1030 CRC transfer managed by CPU . . . .1031 CRC transfer managed by DMA . . . .1031 Resetting the SPIx_TXCRC and SPIx_RXCRC values . . . .1031
28.5 SPI interrupts . . . 1032 28.6 SPI registers . . . 1033
28.6.1 SPI control register 1 (SPIx_CR1) . . . 1033 28.6.2 SPI control register 2 (SPIx_CR2) . . . 1035 28.6.3 SPI status register (SPIx_SR) . . . 1038 28.6.4 SPI data register (SPIx_DR) . . . 1040 28.6.5 SPI CRC polynomial register (SPIx_CRCPR) . . . 1040 28.6.6 SPI Rx CRC register (SPIx_RXCRCR) . . . 1041 28.6.7 SPI Tx CRC register (SPIx_TXCRCR) . . . 1041 28.6.8 SPI register map . . . 104229 Controller area network (bxCAN) . . . 1043
29.1 Introduction . . . 1043
29.2 bxCAN main features . . . 1043
29.3 bxCAN general description . . . 1044
RM0364 Contents
29.3.2 Control, status and configuration registers . . . 1044 29.3.3 Tx mailboxes . . . 1044 29.3.4 Acceptance filters . . . 1045 Receive FIFO . . . .1045
29.4 bxCAN operating modes . . . 1045
29.4.1 Initialization mode . . . 1045 29.4.2 Normal mode . . . 1046 29.4.3 Sleep mode (low-power) . . . 104629.5 Test mode . . . 1047
29.5.1 Silent mode . . . 1047 29.5.2 Loop back mode . . . 1048 29.5.3 Loop back combined with silent mode . . . 104829.6 Behavior in Debug mode . . . 1049
29.7 bxCAN functional description . . . 1049
29.7.1 Transmission handling . . . 1049 Transmit priority . . . .1049 Abort . . . .1050 Nonautomatic retransmission mode . . . .1050 29.7.2 Time triggered communication mode . . . 1051 29.7.3 Reception handling . . . 1051 Valid message . . . .1051 FIFO management . . . .1052 Overrun. . . .1052 Reception related interrupts . . . .1052 29.7.4 Identifier filtering . . . 1052 Scalable width . . . .1053 Mask mode . . . .1053 Identifier list mode . . . .1053 Filter bank scale and mode configuration. . . .1053 Filter match index . . . .1054 Filter priority rules . . . .1055 29.7.5 Message storage . . . 1056 Transmit mailbox . . . .1056 Receive mailbox . . . .1057 29.7.6 Error management . . . 1058 Bus-Off recovery. . . .1058 29.7.7 Bit timing . . . 1058Contents RM0364
29.9 CAN registers . . . 1062
29.9.1 Register access protection . . . 1062 29.9.2 CAN control and status registers . . . 1062 CAN master control register (CAN_MCR) . . . .1062 CAN master status register (CAN_MSR) . . . .1064 CAN transmit status register (CAN_TSR). . . .1065 CAN receive FIFO 0 register (CAN_RF0R) . . . .1068 CAN receive FIFO 1 register (CAN_RF1R) . . . .1068 CAN interrupt enable register (CAN_IER) . . . .1069 CAN error status register (CAN_ESR) . . . .1071 CAN bit timing register (CAN_BTR) . . . .1072 29.9.3 CAN mailbox registers . . . 1073 CAN TX mailbox identifier register (CAN_TIxR) (x = 0..2) . . . .1074 CAN mailbox data length control and time stamp register(CAN_TDTxR) (x = 0..2) . . . .1075 CAN mailbox data low register (CAN_TDLxR) (x = 0..2) . . . .1076 CAN mailbox data high register (CAN_TDHxR) (x = 0..2) . . . .1076 CAN receive FIFO mailbox identifier register (CAN_RIxR) (x = 0..1) . . . .1077 CAN receive FIFO mailbox data length control and time stamp register
(CAN_RDTxR) (x = 0..1). . . .1078 CAN receive FIFO mailbox data low register (CAN_RDLxR) (x = 0..1) . . . .1079 CAN receive FIFO mailbox data high register (CAN_RDHxR) (x = 0..1) . . . . .1079 29.9.4 CAN filter registers . . . 1080 CAN filter master register (CAN_FMR). . . .1080 CAN filter mode register (CAN_FM1R). . . .1081 CAN filter scale register (CAN_FS1R) . . . .1081 CAN filter FIFO assignment register (CAN_FFA1R) . . . .1082 CAN filter activation register (CAN_FA1R) . . . .1082 Filter bank i register x (CAN_FiRx) (i = 0..13, x = 1, 2). . . .1083 29.9.5 bxCAN register map . . . 1084
30 Debug support (DBG) . . . 1088
30.1 Overview . . . 1088
30.2 Reference ARM® documentation . . . 1089
30.3 SWJ debug port (serial wire and JTAG) . . . 1089
30.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . 109030.4 Pinout and debug port pins . . . 1090
30.4.1 SWJ debug port pins . . . 1091 30.4.2 Flexible SWJ-DP pin assignment . . . 1091RM0364 Contents
30.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . 1093
30.5 STM32F334xx JTAG TAP connection . . . 1093 30.6 ID codes and locking mechanism . . . 1094
30.6.1 MCU device ID code . . . 1095 DBGMCU_IDCODE . . . .1095 30.6.2 Boundary scan TAP . . . 1095 JTAG ID code . . . .1095 30.6.3 Cortex-M4® with FPU TAP . . . 1095 30.6.4 Cortex-M4® with FPU JEDEC-106 ID code . . . 109630.7 JTAG debug port . . . 1096 30.8 SW debug port . . . 1098
30.8.1 SW protocol introduction . . . 1098 30.8.2 SW protocol sequence . . . 1098 30.8.3 SW-DP state machine (reset, idle states, ID code) . . . 1099 30.8.4 DP and AP read/write accesses . . . 1099 30.8.5 SW-DP registers . . . 1100 30.8.6 SW-AP registers . . . 110130.9 AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . .1101
Features: . . . .1101
30.10 Core debug . . . .1102 30.11 Capability of the debugger host to connect under system reset . . . .1102 30.12 FPB (Flash patch breakpoint) . . . .1103 30.13 DWT (data watchpoint trigger) . . . .1104 30.14 ITM (instrumentation trace macrocell) . . . .1104
30.14.1 General description . . . 1104 30.14.2 Time stamp packets, synchronization and overflow packets . . . 1104 Example of configuration . . . .110630.15 MCU debug component (DBGMCU) . . . .1106
30.15.1 Debug support for low-power modes . . . 1106 30.15.2 Debug support for timers, watchdog, bxCAN and I2C . . . 1106 30.15.3 Debug MCU configuration register . . . 1107 DBGMCU_CR . . . .1107 30.15.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . 1109 30.15.5 Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . 1111Contents RM0364
31 Device electronic signature . . . 1113 31.1 Unique device ID register (96 bits) . . . 1113 31.2 Memory size data register . . . 1114
31.2.1 Flash size data register . . . 111432 Revision history . . . 1115
RM0364 List of tables Table 43. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC, x=1..2) . . . 308 Table 44. ADC register map and reset values (master and slave ADC
common registers) offset =0x300, x=1) . . . 310