Part of the compilation process performed by the Quartus®II software is to determine the simplest form of the circuit before it synthesizes its logic. This eliminates unnec- essary inputs and minimizes the number of gates used in the FPGA. If we redo Example 5–9 using Quartus®II, the software will warn us of unused inputs and will also give us the final simplified equation. The VHDL program, ex5_9.vhd, is given in
Figure 5–30(a). The original Boolean equation is entered in
VHDL as x ((a OR NOT b) AND (b OR c)) AND b;. The Waveform Editor was used to create the vector waveform file (ex5_9.vwf) shown in Figure 5–30(b). If you study the results carefully you will see that x only goes HIGH when a and b are both HIGH, regardless of c.
When the ex5_9.vhd program was compiled, the Compilation Report produced the warning message shown in Figure 5–31. As you can see, it tells us that after sim- plifying the equation, there is no output that is dependent on pin c. This is the same re- sult that we got in the reduction performed in Example 5–9.
Note: To view the Compilation Report of Figure 5–31: Choose Processing Compilation Report.
Then to view the Analysis & Synthesis Messages:
In the left column of the report, expand the Analysis & Synthesis folder by clicking on its “+” sign, then choose Messages.
+ 6 =
X = [(A + B)(B + C)]B
write the logic equation for that truth table, and then press the third button to write the simplified equation. Notice that the simplified equation shown in the lower box is AB just like we got for Example 5–9. (Note: For help on using the Logic Converter, highlight the sym- bol by left-clicking once on it and pressing the F1 key to display its Help Screen.)
(b) Build the logic circuit from Example 5–7 to see if MultiSIM comes
up with the same simplified equation as the textbook did. The circuit is drawn by first selecting File New, then right-clicking in the
empty workspace and selecting Place Component. Type the name of the gate (AND2, OR2, etc.) and left-click where you want to place it. Next, hook up the Logic Converter as shown to supply the inputs A,
B, and C and monitor the resulting output at X. Double-click on the
Logic Converter and sequentially press the three Conversions but- tons [as we did in part (a)] and see if the simplified equation is
(c) Repeat for Example 5–8.
(d) An alternate method of simplifying Boolean equations is to enter the
equation to be simplified in the lower box of the Logic Converter in- stead of drawing the logic circuit. Next you will press the fourth Conversions button to form a truth table from the equation and then press the third Conversions button to convert that truth table to the sim- plified equation.
Test this method by simplifying the equation presented in Example 5–6 should reduce to X = AB + C].
[X = B(A + C) + C
BC + A.
+
SECTION 5–4 | USING QUARTUS®II TO DETERMINE SIMPLIFIED EQUATIONS
173
Figure 5–30 Quartus®II solution to Example 5–9: (a) VHDL listing; (b) simulation file.
The Quartus®II software also provides us with the simplified equation that it will use to synthesize the circuit. To view the equation:
Choose: Tools Chip Planner Edit Find Find What:
Find Next Cancel.
In the Fan-In column click [* GoTo].
+ + + + + x + ex5_9.vhd X=[(A+B)(B+C)]B _ (a) (b) ex5_9.vwf
X is HIGH for a AND b, regardless of c.
The simplified equation appears in the equations box shown in Figure 5–32. (If there is no Equations box, be sure that the Equations selection under the View menu has a check mark.) The equation is listed as: A1L5(x~0) (b&a). This states that the x-output is mapped into FPGA location A1L5 and its value is b&a. This can be interpreted as which matches the reduction we performed using algebra in Example 5–9. The arithmetic operators used by Quartus® II for Boolean equations are as follows:
& AND operator ! NOT operator # OR operator
$ Exclusive-OR operator (covered in Chapter 6) x = ab,
=
Figure 5–31 The warning message produced by the Compilation Report describes the
c-input as not necessary.
}
x = abFigure 5–32 The Equations window in the Chip Planner shows the reduced equation x = ab.
A more visual method to see the reduced equation is to use the Netlist Viewer: Choose Tools Netlist Viewers Technology Map Viewer Post Mapping. Double-click on the block diagram and the reduced circuit will appear with the inputs and outputs as shown in Figure 5–33. The logic diagram shows with c being a “don’t care”
x = ab +
SECTION 5–4 | USING QUARTUS®II TO DETERMINE SIMPLIFIED EQUATIONS
175
c = "don't care"
x = ab
Figure 5–33 The Netlist Viewer showing the reduced logic circuit for x = ab.
E X A M P L E 5 – 1 0
Use the Quartus® II software to determine the simplified equation for
Solution: In this example we’ll use the Block Editor method of design in-
stead of VHDL. The logic circuit is drawn to produce the ex5_10.bdf file shown in Figure 5–34. When the project is compiled, the compiler creates the warning message shown in Figure 5–35. The message states that the output of the logic circuit does not depend on input-a (this makes a an un- used input). The Chip Planner is then used to see the final simplified equa- tion determined by the Fitter, as shown in Figure 5–36. The simplified
equation is which is the same as Prove to yourself
that this is correct by reducing the original equation using Boolean algebra. The Netlist Viewer in Figure 5–37 shows the reduced circuit for with a “don’t care.”
x = bc x = bc.
x = (!c&b), X = (ABC + B)BC.
ex5_10.bdf
Figure 5–36 The equations window in the Chip Planner shows the simplified equation x = bc. Figure 5–35 The compilation warning stating that input-a is unused.
x = bc
SECTION 5–5 | DE MORGAN’S THEOREM
177
A X = A ·B B A X = A+ B B B 0 1 0 1 1 1 1 0 X = AB A 0 0 1 1 B 0 1 0 1 1 1 1 0 X = A + B A 0 0 1 1 Equivalent resultFigure 5–38 De Morgan’s theorem applied to NAND gate produces two identical truth tables.
5–5
De Morgan’s Theorem
You may have noticed that we did not use NANDs or NORs in any of the logic circuits in Section 5–3. To simplify circuits containing NANDs and NORs, we need to use a theorem developed by the mathematician Augustus De Morgan. This theorem allows us to convert an expression having an inversion bar over two or more variables into an expression having inversion bars over single variables only. This allows us to use the rules presented in the preceding section for the simplification of the equation.
In the form of an equation, De Morgan’s theorem is stated as follows:
Also, for three or more variables,
Basically, to use the theorem, you break the bar over the variables and either change the AND to an OR or change the OR to an AND.
To prove to ourselves that this works, let’s apply the theorem to a NAND gate and then compare the truth table of the equivalent circuit to that of the original NAND gate. As you can see in Figure 5–38, to use De Morgan’s theorem on a NAND gate, first break the bar over the A · B, then change the AND symbol to an OR. The new equation becomes Notice that inversion bubbles are used on the OR gate instead of inverters. By observing the truth tables of the two equations, we can see that the result in the X column is the same for both, which proves that they provide an equivalent output result.
X = A + B.
A + B + C = A
BC ABC = A + B + CA + B = A
B AB = A + BAlso, by looking at the two circuits, we can say that an AND gate with its output inverted is equivalent to an OR gate with its inputs inverted. Therefore, the OR gate with inverted inputs is sometimes used as an alternative symbol for a NAND gate.
By applying De Morgan’s theorem to a NOR gate, we will also produce two identical truth tables, as shown in Figure 5–39(a). Therefore, we can also think of an OR gate with its output inverted as being equivalent to an AND gate with its inputs in- verted. The inverted input AND gate symbol is also sometimes used as an alternative to the NOR gate symbol.
When you write the equation for an AND gate with its inputs inverted, be care- ful to keep the inversion bar over each individual variable (not both) because is not equal to (Prove that to yourself by building a truth table for both.) Also,
is not equal to
The question always arises: Why would a designer ever use an inverted-input OR gate symbol instead of a NAND? Or why use an inverted-input AND gate symbol in- stead of a NOR? In complex logic diagrams, you will see both the inverted-input and the inverted-output symbols being used. The designer will use whichever symbol makes more sense for the particular application.
For example, referring to Figure 5–38, let’s say you need a HIGH output level whenever either A or B is LOW. It makes sense to think of that function as an OR gate with inverted A and B inputs, but you could save two inverters by just using a NAND gate. A + B. A + B A
B. AB A X = A + B B A X = A·B B B 0 1 0 1 1 0 0 0 X = A + B A 0 0 1 1 B 0 1 0 1 1 0 0 0 X = A·B A 0 0 1 1 Equivalent result (a)Figure 5–39 (a) De Morgan’s theorem applied to NOR gate produces two identical truth tables; (b) using the alternative NOR symbol eases circuit simplification; (c) summary of alternative gate symbols.
A B C D X X A B C D X = ABCD A B C D ≡
Final equivalent circuit ≡ Original circuit NOR equivalent Inversion bubbles cancel (b) Inverter ≡ NAND NOR ≡ ≡ (c)
SECTION 5–5 | DE MORGAN’S THEOREM
179
ex5_11.bdf
Figure 5–40 The bdf file of circuits used to prove De Morgan’s theorem. E X A M P L E 5 – 1 1
Use Quartus®II to prove the validity of the De Morgan’s theorem circuits of Figures 5–38 and 5–39. Draw the circuits using the Block Editor and prove equivalence by performing a simulation with all possible input conditions.
Solution: The NAND and NOR circuits of Figures 5–38 and 5–39 are
duplicated in the bdf file shown in Figure 5–40. W is the output of a NAND while X is the output of an inverted-input OR gate that is supposed to be equivalent. Y is the output of a NOR while Z is the output of an inverted- input AND gate that is supposed to be equivalent.
Also, referring to Figure 5–39(a), let’s say you need a HIGH output whenever both A and B are LOW. You would probably use the inverted-input AND gate for your logic diagram because it makes sense logically, but you would use a NOR gate to ac- tually implement the circuit because you could eliminate the inverters.
The alternative methods of drawing NANDs and NORs are also useful for the simplification of logic circuits. Take, for example, the circuit of Figure 5–39(b). By changing the NOR gate to an inverted-input AND gate, the inversion bubbles cancel, and the equation becomes simply Figure 5–39(c) summarizes the alterna- tive representations for the inverter, NAND, and NOR gates.
The following examples illustrate the application of De Morgan’s theorem for the simplification of logic circuits.
X = ABCD.
The vector waveform file in Figure 5–41 shows every combination of input for A, B and C, D. By studying the resultant waveforms you can see that the output at W is identical to X and the output at Y is identical to Z, proving De Morgan’s theorem.