9 Register and Memory Package
9.3 Using the uvm_rgm Package
This section provides a step-by-step introduction to using the uvm_rgm register package for register and memory verification.
9.3.1 Defining the Register and Memory Models
First, you need to define the uvm_rgm model (register fields, registers, register files, address map, and register database). This is done using an
First, you need to define the uvm_rgm model (register fields, registers, register files, address map, and register database). This is done using an XML IP-XACT file. The input format, which is a SPIRIT consortium standard, is translated into corresponding SystemVerilog classes and used in the testbench.
9.3.2 Creating an IP-XACT File
IP-XACT files are a standard format for capturing and integrating design IP. They are structural in nature and allow for describing a desired register database name, address spaces, register files, registers, and fields. Like any XML file, you can read and edit these files with an ASCII editor. In addition, you can read these files using free or commercial editors that provide a table view and extra editing and validation capabilities.
Cadence has extended the IP-XACT to enable more automation than is usually specified for register and memory verification. For example, you can specify coverage directives, constraints (for register randomization), an hdl_path variable (for directly accessing the register signals), and more.
Note If you already have a standard register specification format, you might want to create a script that parses the specifications and creates the corresponding IP-XACT file. Some companies start with an IP-XACT format and generate their specifications, C header files, register description, and even HW implementation.
9.3.2.1 XML Structure
XML is a text markup language like HTML, but was created to store data rather than just display text. The XML format is hierarchical and includes start tags followed by end tags, both contained between angle brackets. End tags are named exactly like the corresponding start tags but are preceded by a forward slash. For example:
<note>
<to>Ben</to>
<from>Gal</from>
<heading>Reminder for Shai</heading>
<body>Use UVM and prosper!</body>
</note>
IP-XACT introduces standard tags to capture design and register model attributes.
9.3.2.2 IP-XACT Structure
The structure of the IP-XACT file consists of the following:
A header with some document detail such as the vendor name, the SPIRIT IP-XACT version, a project name, and so on.
An array of memory maps that specify the memory and register descriptions. Each memory map is an address space that can hold memory blocks (register files), registers, or fields.
The XML code below illustrates the IP-XACT descriptions for a memory map, a register file, registers, fields, and their attributes.
<spirit:memoryMap>
<spirit:name>memory_map_name</spirit:name>
<spirit:addressBlock>
<spirit:name>regfile_name</spirit:name>
<spirit:baseAddress>0</spirit:baseAddress>
<spirit:range>16</spirit:range>
<spirit:range>16</spirit:range>
<spirit:width>8</spirit:width>
<spirit:register>
<spirit:name>register_name</spirit:name>
<spirit:addressOffset>0x0</spirit:addressOffset>
<spirit:size>8</spirit:size>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value>0x00</spirit:value>
<spirit:mask>0xff</spirit:mask>
</spirit:reset>
<spirit:field>
<spirit:name>field_name</spirit:name>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth>2</spirit:bitWidth>
<spirit:access>read-write</spirit:access>
<spirit:values> <!-- required only for enumerations -->
<spirit:value>0</spirit:value>
<spirit:name>LEFT</spirit:name>
</spirit:values>
Notes
The easiest way to create an IP-XACT format is to start from an existing IP-XACT file.
Use an XML editor for easy visualization of IP-XACT files (see the following section for details).
Some companies use XML as the format for describing design blocks and leverage this for their register descriptions and some write scripts to convert their own register specification format to XML.
9.3.2.3 IP-XACT Vendor Extensions
The IP-XACT specification is not complete for register automation needs. Some of the missing capabilities include: constraints, coverage directives, and backdoor paths. That said, the standard does support extensions that enable us to add the missing functionality. For example:
<spirit:vendorExtensions>
<vendorExtensions type>ua_lcr_c</vendorExtensions:type>
<vendorExtensions hdl_path>lcr</vendorExtensions:hdl_path>
<vendorExtensions:constraint>c_char_lngth {value.char_lngth != 2'b00;}
</vendorExtensions:constraint>
</spirit:vendorExtensions>
Note The uvm_rgm package introduces useful vendor extensions. We strongly recommend that you leverage the vendor extensions to enable additional automation, but this is not mandatory.
9.3.2.4 Leveraging XML and IP-XACT Editors
One of the benefits of using a standard is the number of free, commercial third-party applications which support that standard.
Some of the benefits of using applications that support the XML standard are that they:
Ensure a clean XML syntax before running the parser script.
Provide an intuitive view that allows collapsing and enhancing sub-trees.
Support edit-time and on-demand standard validation.
Enable automatic correlation between the Spirit and generated SystemVerilog classes.
Note You can download the Eclipse application from www.eclipse.org.
9.3.2.5 Building the Register-Model Procedurally
In some cases, you will need to build the register model using the full procedural language capabilities. For example, you may need to create arrays with complex iterator logic that is not supported by IP-XACT. The uvm_rgm package provides you with the means to capture such models. Please review the Register and Memory Model User Guide for additional information.
9.3.3 Creating uvm_rgm SystemVerilog Classes
The following example shows the XML description for the line control register for the UART Controller device.
Example 9–1 UART Controller Line Control Register XML Description
1 <spirit:register>
2 <spirit:name>ua_lcr</spirit:name>
3 <spirit:addressOffset>0x3</spirit:addressOffset>
4 <spirit:size>8</spirit:size>
5 <spirit:access>read-write</spirit:access>
6 <spirit:reset>
7 <spirit:value>0x03</spirit:value>
8 <spirit:mask>0xff</spirit:mask>
9 </spirit:reset>
10 // FIELD DESCRIPTIONS 11 <spirit:field>
12 <spirit:name>char_lngth</spirit:name>
13 <spirit:bitOffset>0</spirit:bitOffset>
14 <spirit:bitWidth>2</spirit:bitWidth>
15 </spirit:field>
16 <spirit:field>
17 <spirit:name>num_stop_bits</spirit:name>
18 <spirit:bitOffset>2</spirit:bitOffset>
19 <spirit:bitWidth>1</spirit:bitWidth>
20 </spirit:field>
21 <spirit:field>
22 <spirit:name>p_en</spirit:name>
23 <spirit:bitOffset>3</spirit:bitOffset>
24 <spirit:bitWidth>1</spirit:bitWidth>
25 </spirit:field>
26 <spirit:field>
27 <spirit:name>div_latch_access</spirit:name>
28 <spirit:bitOffset>7</spirit:bitOffset>
29 <spirit:bitWidth>1</spirit:bitWidth>
30 </spirit:field>
31 <spirit:vendorExtensions>
32 <vendorExtensions:type>ua_lcr_c</vendorExtensions:type>
33 <vendorExtensions:compare_mask>0xff</vendorExtensions:compare_mask>
34 <vendorExtensions:hdl_path>uart_regs.lcr</vendorExtensions:hdl_path>
35 <vendorExtensions:constraint>c_char_lngth {value.char_lngth != 'b00;}
36 </vendorExtensions:constraint>
37 </spirit:vendorExtensions>
38 </spirit:register>
Example 9–2 UART Controller XML Description for the Reg File, Address Map
1 <?xml version="1.0"?> 7 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd
8 $UVM_RGM_HOME/builder/ipxact/schema
9 $UVM_RGM_HOME/builder/ipxact/schema/vendorExtensions.xsd">
10 <spirit:vendor>Cadence_Design_Systems</spirit:vendor>
17 <spirit:name>addr_map</spirit:name>
18 <spirit:addressBlock>
19 <!-- UART Controller Register File -->
20 <spirit:name>uart_ctrl_rf</spirit:name>
21 <spirit:baseAddress>0x00</spirit:baseAddress>
22 <spirit:range>0xFFFF</spirit:range>
23 <spirit:width>8</spirit:width>
24 <!-- Include each register description for the register file-->
25 <spirit:register> <!--LINE CONTROL REG--> </spirit:register>
26 <spirit:register> <!--INTERRUPT ENAB REG--> </spirit:register>
27 <spirit:vendorExtensions>
28 <vendorExtensions:type>uart_ctrl_rf_c</vendorExtensions:type>
29 <vendorExtensions:hdl_path>rf1</vendorExtensions:hdl_path>
30 </spirit:vendorExtensions>
36 <vendorExtensions:hdl_path>addr_map</vendorExtensions:hdl_path>
37 </spirit:vendorExtensions>
38 </spirit:component>
9.3.3.1 Using the IP-XACT Utility
The uvm_rgm package provides a Java utility to automate the creation of SystemVerilog classes using the IP-XACT description. To convert the input IP-XACT to SystemVerilog classes, use the following command:
$JAVA_HOME/bin/java -jar $UVM_RGM_HOME/builder/ipxact/uvmrgm_ipxact2sv_parser.jar -i INPUT_FILE [Options]
The uvmrgm_ipxact2sv_parser.jar script also has an option to create a simple test to do a quick sanity check of your register database files. The option is: -qt testname. It will create an instance of the register database, execute a hard reset and print the register database and its sub-components. We suggest you use this option to test your register descriptions while you are mastering the IPXACT format.
9.3.3.2 The Generated SystemVerilog Code
The IP-XACT utility, uvmrgm_ipxact2sv_parser.jar, converts the IP-XACT register description file into a set of SystemVerilog classes for register verification. Included in the output file are the following:
Enumerated types—A type declaration for each unique enumeration
Field declarations
Registers—A class for every unique register type
Register files—Contain instances of registers for each register file
Address maps—Contain one or more register files
A top-level RGM_DB class (example) that contains the top-level address map
The generated code is UVM-compliant and tuned for performance and the memory footprint of large systems. It leverages much of the UVM automation and adds additional register-related automation by deriving the classes from the uvm_rgm base classes. Most of the code is not intended to be read by humans, but some of the public attributes are accessible for further user-defined coverage and generation. The code below illustrates an example of a generated register class:
Example 9–3 UART Controller Line Control Register SystemVerilog Description