Parsing of the Files Syntax:
vhpcomp [-work <library_name> ]<file_name> .vhd vhpcomp -work <library_name><file_name> .vhd where
• -workis optional and is only needed when trying to specify a different library than the defaultwork.
• <library_name> indicates the library into which the source specified by<file_name> should be compiled.
There can be multiple VHDL file names per line.
Seevhpcomp Overview and Syntaxfor more information about the command.
Generation of the ISim Simulation Executable - Running fuse Syntax:
fuse {[<library_name>. ]<top_name> }-o <output_file_name>
where:
• {[<library_name>.]<top_name>} is one or more libraries and top level design unit names. For example, design unit name of the test bench file. Include a library name is optional. The default name work is assumed when library name is not specified. Examples:work.topunit, work.glbl, mylib.glbl.
• -oswitch is optional. Without-o, the default name for the simulation executable isx.exe.
Seefuse Overview and Syntaxfor more information about the fuse command.
Simulation
After the compilation and ISim simulation executable generation, the final stage is simulation. The ISim simulation executable generated by the fuse command is run to effect simulation.
If you would like Tcl commands contained in a file to be executed after the simulation has begun, use the -tclbatchswitch.
It is also possible to instruct the simulator to use the correct timing delays from the SDF file.
Syntax:
<executable_name>.exe -tclbatch <tcl_file_name> -sdfmin|-sdftyp|-sdfmax
<<anno_point>=sdf_file>.sdf>
Chapter 3: VHDL Simulation
where
• <executable_name>.exe is the simulation executable called x.exe unless otherwise specified with thefuse -oswitch.
• -sdfmin|-sdftyp|-sdfmaxis the type of delay (minimum, typical, or maximum) that ISim should use.
• <anno_point> is the point of hierarchy where you want to annotate the delay. This is usually UUT.
• <sdf_file> is the filename of the SDF file you want to annotate.
SeeISim Simulation Executable Overview and Syntaxfor more information about the command.
Library Mapping File
Note The following information is intended for advanced users.
The ISim HDL compile programs,vhpcomp,vlogcompandfuse, use thexilinxsim.iniconfiguration file to learn the definitions and physical locations of VHDL and Verilog logical libraries.
Search Order
The compilers attempt to readxilinxsim.inifrom these locations in the following order.
1. $XILINX/vhdl/hdp/<platform>.
2. User file specified through the-initfileswitch invlogcomp,vhpcomporfuse. If-initfileis not specified, "xilinxsim.ini" in the current working directory is searched for.
Syntax
Thexilinxsim.inifile has the following format:
<logical_library1> = <physical_dir_path1>
<logical_library2> = <physical_dir_path2>
. .
<logical_libraryn> = <physical_dir_pathn>
Example
The following is an example of axilinxsim.inifile:
VHDL
std=C:/libs/vhdl/hdp/
stdieee=C:/libs/vhdl/hdp/ieee work=C:/work
Verilog
unisims_ver=$XILINX/rtf/verilog/hdp/nt/unisims_ver
xilinxcorelib_ver=C:/libs/verilog/hdp/nt/xilinxcorelib_ver mylib=./mylib
work=C:/work
Chapter 3: VHDL Simulation
Features/Limitations
Thexilinxsim.inifile has the following features and limitations:
• There must be no more than one library/path per line specified inside thexilinxsim.inifile.
• If the directory corresponding to the physical path does not exist,vhpcomporvlogcompcreates it when the compiler first tries to write to it.
• You can describe the physical path in terms of environment variables. The environment variable must start with $ character.
• The default physical directory for a logical library isisim/<logical_library_name>.
• All comments in this file must start with ’--’.
Interactive Simulation in Command Line Mode
When a simulation is run in command line mode, a Tcl prompt opens and you can enter simulation Tcl
commands, which enable you to run simulation, analyze the design, and debug the design. For more information about Simulation Commands, seeSimulation Command Overview. For tips on how to enter commands, see Entering Simulation Tcl Commands.
Chapter 4
Verilog Simulation
Verilog Simulation Overview
Running a simulation from the command line involves three basic steps:
1. Parsing the design files
2. Generating the ISim simulation executable 3. Simulating the design
Go to the appropriate simulation topic for details:
• Running a Functional Simulation at the Command Line
• Running a Timing Simulation at the Command Line
Running a Functional Simulation of a Verilog Design From the Command Line
In a functional (behavioral) simulation of a Verilog design, the steps must be followed if UNISIM primitives are used:
• Compile$XILINX/Verilog/src/glbl.vto librarywork.
• Specifywork.glblas one of the <library_name>.<top_name> infuse.
• Specify-L unisims_verinfuse.
Method 1: Using a Project File - Recommended
Parsing the Design Files
Create a file called<proj_name>.prjand use the following syntax inside the project file:
verilog <library_name> {<file_name_1>.v} {[-d <macro>] [-i <include_path>]}
verilog <library_name> {<file_name_2>.v} {[-d <macro>] [-i <include_path>]}
.
verilog <library_name> {<file_name_n>.v} {[-d <macro>] [-i <include_path>]}
where:
• verilog indicates that the source is a Verilog file.
• <library_name> indicates the library into which the source on the given line should be compiled. More than one Verilog source can be specified on a given line.
• [-d <macro>] defines one or more macro located in the location specified in [-i <include_path>].
Example:
verilog work top.v testbench.v
Generating the ISim Simulation Executable - Running fuse