vdW-heterostructures

The fabrication process of vdW-heterostructures is schematically shown in Fig.2.2and is based on the technique introduced by Wang et al. [137] and

2SPV 224P, Nitto Europe NV

3Obtained from hq graphene.

4Obtained from NGS.

5Obtained from hQ graphene or Nanosurf, see section7.6for a comparison.

44

2.1. Sample fabrication

~20 nm

~18 nm

10 µm SL SL

BL

graphite

FL

~20 nm

~10 nm

(a) graphene (b) hBN (c) WSe₂

10 µm 10 µm

Figure 2.1. Exfoliation of 2D materials: (a) to (c) show different 2D materials exfoliated onto Si wafers with 300 nm of SiO2 being responsible for the interference contrast. Graphene is easily visible down to a single layer (SL). Bilayer (BL) and few layer (FL) are also easily distinguishable. Due to the large band gap of hBN, only thicker flakes (> 5 nm) are visible on this substrate. Different WSe2 thicknesses result in different optical contrast though less pronounced as for graphene and hBN.

Zomer et al. [138]. In general, any vdW-crystals can be stacked together but for the sake of simplicity the procedure will be described for a hBN/Gr/WSe2

heterostructure. It starts with the preparation of a polycarbonate (PC) film on a glass slide. Using an adhesive tape with a window a PC membrane is transferred and fixed on top of a PDMS stamp placed on glass slide as shown in (a). The glass slide with the PC/PDMS stamp is then mounted on a xyz-stage of a home-built transfer microscope.

The top layer (hBN) of the vdW-heterostructures is exfoliated on clean Si/SiO2 wafer and suitable flakes are located optically. After mounting the wafer piece with the desired top flake in the transfer stage, a clean area on the PC film is located and the flake is picked up, see (b). Detailed description of this process will be given for the pickup of the graphene flake (next step).

Similarly, the next layer (graphene) is exfoliated on a clean substrate as well, see (c). Again the flakes are located by optical means an the thickness is estimated from the optical contrast, which works quite reliable for graphene.

The wafer piece with the graphene flake is then mounted on the xy-stage, which includes a roll and pitch degree of freedom as well. These two parameters can be used to control the relative alignment of the bottom stage to the top translation stage. The two flakes are then aligned relative to each other and the PC/PDMS stamp is lowered until it touches the bottom wafer. Then, the PC/PDMS stamp is further lowered until the meniscus, separating the region where the PC is in contact with the wafer and where it is just before

2. Experimental methods

PC on glass slide Scotch tape

(a)

exfol. t-hBN

(b)

PDMS PC

PDMS PC

exfol. graphene

(c)

graphene

exfol. b-WSe₂

(d)

t-hBN

(c₁) (c₂) (c₃)

SiO₂ graphene

t-hBN

graphene hBN PDMS

SiO₂ PC

Figure 2.2. Dry stacking of vdW-heterostructures following the met-hod introduced by Wang et al. [137] and Zomer et al. [138](a) prepa-ration of the PC/PDMS stamp. First, the top hBN is picked up (b), followed by the pick up the graphene (c), which is released on the bottom layer (d) by melting the PC onto the substrate. The circular insets show the detailed stacking order. Figure adapted from Ref. [48]

46

2.1. Sample fabrication

going into contact with the wafer, is just next to the graphene flake to be picked up. This situation is highlighted in (c1). Then the stage is heated, which leads to the expansion of the PC film, which in turn leads to a lateral movement of the meniscus across the graphene flake bringing the top hBN into contact with the graphene (this happens around 30^◦C to 60^◦C, see also (c2).

Once the meniscus passed both flakes, the temperature is increased to 80^◦C, while keeping the meniscus at a fixed position. This is achieved by slowly retracting the PC/PDMS stamp. At 80^◦C, the heating is turned off and while the substrate cools down, the PC/PDMS will shrink and hence retract, see (c3). In doing so, the meniscus slowly moves across the graphene flake, which will be picked up due to the stronger interaction between the graphene and hBN or PC compared to the interaction with the SiO2. This procedure was also used to pick-up the top hBN layer in the first place.

In a last step (d), the half stack on the PC/PDMS is released on top of the bottom WSe2 flake previously located on the target substrate. This is done by aligning the half stack with the WSe2 and bringing them into contact as described in (c1 to c2). This time the substrate is heated to 150^◦C to detach the PC from the PDMS.

The adhesion of the vdW-heterostructure to the target substrate is increased by heating the complete stack, including the PC, on a hotplate at 180^◦C for 3 min. Afterwards, the PC is dissolved in chloroform. An annealing step in forming gas (H2/N2) at 200^◦C for 100 min is performed to remove polymer residues on the top and to allow the bubbles to move and coalesce in order to obtain a more homogeneous sample. In general, an AFM image is acquired to locate bubble-free regions on the vdW-heterostructure to design the device in these regions. After this treatment, the vdW-heterostructure can be further processed, including shaping into the final device geometry, fabrication of side contacts and the deposition of top gates. For all these steps standard e-beam lithography, reactive ion etching and metallization processes were used. Details can be found in the appendixA.