VHDL, the Very High Speed Integrated Circuit Hardware Description Language, became a key tool for design capture and development of personal computers, cellular telephones, and high-speed data communications devices during the 1990s. VHDL is a product of the Very High Speed Integrated Circuits (VHSIC) program funded by the department of defense in the 1970s and 80s. VHDL provides both low-level and high- level language constructs that enable designers to describe small and large circuits and systems. It provides portability of code between simulation and synthesis tools, as well as device-independent design. It also facilitates converting a design from a programmable logic to an Application Specific Integrated Circuit (ASIC) implementation. VHDL is an industry standard for the description, simulation, modeling and synthesis of digital circuits and systems. The main reason behind the growth in the use of VHDL can be attributed to synthesis, the reduction of a design description to a lower-level circuit representation. A design can be created and captured using VHDL without having to choose a device for implementation. Hence it provides a means for a device-independent design. Device-independent design and portability allows benchmarking a design using different device architectures and different synthesis tools.
Electronic Design Automation (EDA) Design Tool Flow: The EDA design tool flow is as follows:
• Design description (capture) in VHDL
• Pre-synthesis simulation for design verification/validation • Synthesis
• Post-synthesis simulation for design verification/validation • Implementation (Map, Place and Route)
• Post-implementation simulation for design verification/validation • Design optimization
• Final implementation to FPGA/CPLD/ or ASIC technology.
The inputs to the synthesis EDA software tool are the VHDL code, synthesis directives and the device technology selection. Synthesis directives include different kinds of external as well as internal directives that influence the device implementation process. The required device selection is done during this process.
Field Programmable Gate Array (FPGA):
The FPGA architecture is an array of logic cells (blocks) that communicate with one another and with I/O via wires within routing channels. Like a semi-custom gate array, which consists of an array of transistors, an FPGA consists of an array of logic cells [8,10]. A FPGA chip consists of an array of logic blocks and routing channels as shown in Figure 5.1. Each circuit or system must be mapped into the smallest square FPGA that can accommodate it.
Figure 5.1: FPGA Architecture
Each logic block contains or consists of a number of RAM based Look Up Tables (LUTs) used for logic function implementation and D-type flip-flops in addition to several multiplexers used for signal routing or logic function implementation. FPGA
routing can be segmented and/or un-segmented. Un-segmented routing is when each wiring segment spans only one logic block before it terminates in a switch box. By turning on some of the programmable switches within a switch box, longer paths can be constructed. The design for this project is implemented (prototyped) to a Spartan XL FPGA chip which is a XILINX product [8]. It is a PROM based FPGA.
The one that is used for this project is an XCS10PC84 from the XL family. The FPGA is implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), routing channels and surrounded by I/O devices. The FPGA is provided with a clock rate of 50 Mhz. There are two more configurable clocks on the chip. The Spartan XCS10PC84XL is an 84- pin device with 466 logic cells and is approximately equivalent to 10,000 gates. Typically, the gate range for the XL chips will be from 3000-12,000. The XCS10 has a 14x14 CLB matrix with 196 total CLBs. There are 616 flip-flops in the chip and the maximum available I/Os on the chip are 112.
Digilab XL Prototype Board:
Digilab XL prototype boards [8] feature a Xilinx Spartan FPGA (either 3.3V or 5V) and all the I/O devices needed to implement a wide variety of circuits. The FPGA on the board can be programmed directly from a PC using an included JTAG cable, or from an on-board PROM. A view of the board is shown in the figure below. The board has one internally generated clock and two configurable clocks.
The Digilab prototype board contains 8 LEDs and a seven-segment display which can be used for monitoring prototype input/output signals of interest when testing the prototype system programmed into the Spartan XL chip on the board.
VHDL Design Capture:
Behavioral VHDL description was used in design capture and coding of the crossbar interconnect network design and logic. The structural equivalents of two behavioral VHDL descriptions is shown in Figures 6.1 and 6.2 of the next chapter. The scenario of a processor trying to access a particular memory block and whether its request is granted (FLAG = ‘1’) or rejected (FLAG = ‘0’) can be generalized to all processors and all memory blocks. Hence, the main VHDL code has a function ‘flg’, an entity ‘main’ and a process ‘P1’ and it is possible to increase the number of processors, memory blocks (and address bus) , memory locations in each memory block (and address bus), width of data bus, and the width of the processor queue depth bus.
Appendix A contains the VHDL code, structured as shown in Figure 6.1, which describes the crossbar interconnect network assuming the number of processors, the number of memory blocks, and the number of addressable locations in each memory block to be ‘4’. The input queue depth of each processor is 4-bits wide. This VHDL code is described considering the crossbar interconnect network and the shared memory as a single functional unit as shown in Figure 6.1. This code is tested for correct design capture and interconnect network functionality via the pre-synthesis, post-synthesis and post-implementation VHDL simulation stages and is downloaded onto the XILINX based Spartan XL FPGA [7,8] for prototype testing and evaluation. Appendix B contains the VHDL code describing only the crossbar interconnection network as a single functional unit as depicted in Figure 6.2. This code has more I/O pins than the previous code. This code was tested via pre-synthesis and post-synthesis VHDL simulation. With the exceptions of the I/O pins and shared memory, the functionality of both VHDL interconnect network descriptions is the same and is identical to the description of the crossbar interconnect network organization and architecture design described in Chapter 4.