Virtual Architecture

With the definition of the allocation functionsa,a_s, anda_dat hand, we introduce a central concept of our work, the virtual architecture (VA). As already mentioned, we need a common reference model in order to assess the reconfiguration cost metrics in the RSG at structural level. This common reference is provided by the VA. We im-plicitly assumed that the allocation functions map the input graphs to image graphs that are related to each other, i.e. the nodes and edges of the image graphs may have common subsets. In order to built a common reference model for the image graphs, we define the VA as a supergraph that contains all image graphs as a subset. The

Table 3.1: Allocation of nodes and edges as used in Example 3.7. The input graphs are depicted in Figure 3.8.

3.4. Configuration Cost at Structural Level 63

VA itself is defined as an LMG denoted as G_A= (N_A,E_A,S_A,n,S_A,p,l_A,n,s_A,d_A,l_A,s,l_A,d).

We require the setN_Aof nodes and the setE_Aof edges to be enumerable sets, i.e.

the elements of these sets can be completely enumerated by an index l as follows:

n_l ∈N_A={n₁, . . . , n_|NA|}, l = 1, . . . , |N_A| and e_l ∈E_A={e₁, . . . , e_|EA|}, l = 1, . . . , |E_A|.

For a set of input graphs G_iwith i∈N_Tand the allocation functionsa,a_s, anda_d, the VA observes the following conditions regarding the image of the input graphs:

[

i∈NT

N_i^′ ⊂ N_A, (3.19)

[

i∈NT

E_i^′ ⊂ E_A. (3.20)

There exists a very straightforward way to construct a VA for a set of image graphs. For a known allocation function, the VA can be constructed from the image graphs by setting up the nodes and edges according to:

N_A := [

i∈NT

N_i^′, (3.21)

E_A := [

i∈NT

E_i^′. (3.22)

Alternatively, the VA may be given along with the input graphs. In this case, the nodes and edges in the VA may be available resources that can be allocated by the nodes and edges of the image graphs. In this situation, the problem consists of finding valid allocation functions such that the conditions in the Equations 3.19 and 3.20 hold.

The VA provides the ideal tool to establish the reconfiguration cost model based on the RSG. As the name virtual architecture suggests, the VA defines an assumed architecture model. The reconfiguration cost can now be established with the VA as a reference.

The VA defines the reconfigurable elements of a device configuration d(i) = (d(i)₁, . . . ,d(i)_m), i ∈ N_T. The device configuration d(i) consists of m = |N_{A| +}

|E_A| elements. We assume all elements of a VA are reconfigurable. For the VA model, the elementsd(i)_kwith k = 1, . . . , m describe the configuration as follows:

the elementsd(i)₁, . . . ,d(i)_|N

A|are associated with the resource configuration of the nodes n₁, . . . , n_|N

A|∈N_Aand the elementsd(i)_k, k =|N_A| + 1, . . . , m are associated with the interconnect use of the edges e₁, . . . , e_|E

A|∈E_A.

In the following we describe the device configurationd(i) for an input graph G_i with i∈N_T, an allocationaand a VA G_A. The device configuration describes how the resources and interconnect of a VA must be configured in order to implement the image graph G^′_ion the VA such that it realizes the functionality described in the input graph G_i.

The configuration of a resource n_k∈N_Afor an input graph G_idepends on the configuration required by the node n_i ∈ N_i that is allocated to the resource n_k. More precisely, the configuration of resource n_k∈N_A, k∈ {1, . . . , |N_A|} is specified byd(i)_k=l^′_n,i(n_k) if a node n_i∈N_iexists witha(n_i) = n_k∈N_i^′, n_k∈N_A, otherwise d(i)_k= ∅. The nodes nkin the VA may have a different configuration for each task i∈N_T.

The edges e_k−|N

A|∈E_A, k∈ {|N_A| + 1, . . . , m} in the VA represent possible con-nections between nodes. The edges given by an input graph are mapped to edges in an image graph. Depending on this mapping, the interconnect in the VA is ei-ther used by the image graph or it is unused. The configuration of interconnect e_k−|N

A| ∈ E_A, k ∈ {|N_A| + 1, . . . , m} is given with d(i)_k = 1, if an edge e_i ∈ E_i is mapped to an edge e_k−|N

A|∈E_Ai.e.a_e(e_i) = e_k−|N

A|∈E_i^′, otherwised(i)_k= 0.

The device configuration that describes the mapping of each input graph to a configuration of the VA model fully defines the reconfiguration cost within the RSG model. The reconfiguration bitmap is computed from the device configuration as given in Equation 3.1. The definitions used so far are summarized in Figure 3.9.

Input Graphs

Virtual Architecture

Image Graphs/ RSG Reconfiguration

Cost

G(N_T,E_T) G_A(N_A,E_A, . . .)

G_i ^a,a_s,a_d G_i^{′ d} _r

t , s

Figure 3.9: The relationship between input graphs, image graphs, the VA, and the RSG cost model. The reconfiguration costt, sare defined in Section 3.2.

Example 3.8 In this example we want to illustrate the reconfiguration cost that arise for the tasks G₁, G₂, G₃given in Table 3.1. The VA graph is given by the nodesN_A:=

{ f₁, f₂, f₃, f₄} and edgesE_A:={( f₁, f₂, o, i₂), ( f₃, f₂, o, i₁), ( f₄, f₁, o, i₁)}. The allocation functions a,a_e given in the table yield the device configurations ^d(i), i = 1, 2, 3 for each task: ^d(1) = (^′1^′,^′2^′,^′3^′, ∅, 1, 1, 0),^d(2) = (^′5^′,^′6^′, ∅,^′4^′, 1, 0, 1), and^d(3) = (^′10^′,^′8^′,^′7^′,^′9^′, 1, 1, 1). Note that these device configurations are not related to a specific mapping to the target architecture as in Section 3.1. The reconfiguration bitmap can be derived from the device configurations^d(i). In the example the bitmaps are: ^r(1, 2) =^r(2, 1) = (1, 1, 1, 1, 0, 1, 1), ^r(2, 3) =^r(3, 2) = (1, 1, 1, 1, 0, 1, 0), and r(1, 3) =^r(3, 1) = (1, 1, 1, 1, 0, 0, 1).

The reconfiguration cost (with unit weight forw_tandw_s) in the example evaluate to t =¹⁶₃ and s =6.

3.4. Configuration Cost at Structural Level 65

The VA serves as an internal reference architecture in order to optimize the allocation and to identify similarities between the input graphs. However, the map-ping of the input graphs to device resources during the implementation process is a different step. The allocation found for the mapping to a VA provides important allocation constraints for the device mapping: nodes that are mapped to the same node in the VA must be mapped to the same resource in the FPGA and edges that are mapped to the same edge in the VA must be realized by the same interconnect in the FPGA, too. If these constraints are observed, the reconfiguration cost can be reduced as expected from the VA/RSG based cost model.