DC Voltage Margin Control

As analyzed in Section 3.1.1 and 3.1.3, if MMC1 station is responsible for active power generation,

when SLG fault occurs in the transformerless case or the primary side of Y/Δ transformer in this station,

dc voltage will drop because of insufficient active power supply. Otherwise, if MMC1 station is

responsible for active power absorption, the SLG faults in its ac side will induce surplus energy and thus

an overvoltage. In reality, either under-voltage or over-voltage is unacceptable since they may trip the

protection and interrupt the continuous power transfer. In addition, with low dc voltage, the converter will

lose its controllability and operate as a diode bridge. On the other hand, the dc over-voltage will pose a

threat to the system since it may exceed the operation range of devices and passive components, and

induce severe damage.

As a solution, the dc voltage margin control is adopted for converters regulating active power. Relying

on local information, there is no communication requirement for this control. Additionally, consisting of

PI controllers, it has inherent zero steady state error for the dc voltage regulation. Moreover, due to the

autonomous control modes transition, it avoids mistakes during manual operation and becomes robust.

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Figure 4-24 shows the control diagram of dc voltage margin control, where Vdc_Hand Vdc_Lrepresent

the preset upper and lower dc voltage limit, respectively. Under normal conditions, the dc terminal

voltage vdc stays within the range between Vdc_Hand Vdc_L, and the d axis current reference is generated by

the active power control (APR). Otherwise, if SLG occurs and MMC1 cannot bring dc voltage back,

MMC2 will automatically start to regulate dc voltage to either Vdc_H(active power generation larger than

absorption) or Vdc_L(active power generation lower than absorption). The dc voltage margin control is

tested in case 1 under different operation conditions. DC voltage level Vdc_Hand Vdc_L are set to 1.07 and

0.93 pu, respectively.

A. MMC1 suffers a SLG fault and MMC2 absorbs active power of 0.8 MW (P2ref = 0.8 MW)

The active power direction in Figure 4-25 is defined to be positive. If no dc voltage margin control is

employed, dc voltage will drop to about 3974 V (0.79 pu) when another active power balance is achieved,

as illustrated in Figure 4-26.

Figure 4-25. System configuration for case 1.

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Simulated results with dc voltage margin control are shown in Figure 4-27(b). Although the current

reference generated by active power control (idref_p) remains, the real d axis current reference is

determined by dc voltage regulation, which is about 41.86 % lower than its rated value. Consequently,

MMC1 provides its maximum phase current, while the active power absorbed by MMC2 reduces from 0.8

MW to 0.536 MW (Figure 4-27 (d)) to regulate its dc terminal voltage to the pre-set level of 0.93 pu

(Figure 4-27 (a)). For better understanding, the operation point variation of MMC1 and MMC2 in this case

is illustrated in Figure 4-28. Under normal conditions, MMC1 operates as a slack bus and takes charge of

voltage regulation. MMC2 works as an inverter and controls active power absorption. During SLG fault,

MMC1 outputs the maximum allowed ac current and goes into constant active power generation mode,

while MMC1 reduces its active power absorption and controls dc voltage to Vdc_L.

(a) DC voltages (b) d axis current reference

0.4 0.5 0.6 0.7 0.8 0.9 1 0 2 4 6 8 x 105 QP t/s

(c) Active and reactive power in MMC2station (d) Active and reactive power in MMC1station Figure 4-27. Simulated results for case 1, with dc voltage margin control.

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(a) Normal condition

(b) SLG fault occurs in MMC1 station in case 1

Figure 4-28. Operation points of MMC1 and MMC2 with dc voltage margin control.

B. MMC1 suffers a SLG fault and MMC2 generates active power of 0.8 MW (P2ref = -0.8 MW)

The same system configuration in Figure 4-25 is used, and MMC2 generates instead of absorbing 0.8

MW active power. Figure 4-29 gives the simulation results with and without dc voltage margin control

when a SLG fault happens. If no margin control is implemented, active power generated in MMC2 is

constant, while the active power absorbed by MMC1 reduces by about 37.5%. Consequently, dc voltage

keeps increasing and becomes hazardous to devices and passive components. On the other hand, with dc

voltage margin control, the active power generated by MMC2 drops and dc voltage is controlled to 1.07

pu (Vdc_H) as expected.

C. MMC2 suffers a SLG fault

Figure 4-30 and Figure 4-31 give the operation performance of a HVDC system with MMC2 station

side SLG fault and dc voltage margin control, when MMC2 absorbs (case 3) or generates (case 4) 0.8 MW

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(a) DC voltages (a) DC voltages

(b) dq axis current (b) d axis current reference

(c) Active and reactive power (c) Active and reactive power Figure 4-29. Simulated results for case 2, with (left column) and without (right column) dc voltage

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Figure 4-30. Simulated results for case 3, with dc voltage margin control.

Figure 4-31. Simulated results for case 4, with dc voltage margin control.

Since MMC1 is still able to maintain the dc voltage in these two cases, dc voltage control in MMC2

station will be bypassed, leaving APR unaffected, no matter if P2ref is set to 0.8 MW or -0.8 MW.

In summary, through dc voltage margin control, no over- and under- voltage will occur in HVDC

systems during a SLG fault. By setting different upper and lower dc voltage limits, the active power

transfer during SLG fault conditions can be adjusted. Moreover, the various voltage levels also enable dc

voltage margin control a good extensibility to multi-terminal HVDC system. Although a larger dc voltage

range (Vdc_H - Vdc_L) contributes to higher active power transfer, it will lead to lower controllability or

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