Write Subsystem

There are three major elements in this subsystem, namely two interfaces, Slave AXI4-Stream Video and Master AXI4-Memory Mapped, and a top module, in which is managed these interfaces. It is responsible

for tracking of the data received, error control, buffering, main state machine (represented by a diagram in Figure 3.11), and more.

In the Slave AXI4-Stream Video, there is a demand to ensure the protocol compliance and to interface with a master in which the slave must be always ready to receive the data to guarantee there is no data loss in the process. The data is saved in circular buffers, controlled by the top module.

The top module is responsible for monitoring and initiating every operation happening in both Slave and Master interfaces as well as for tracking both data received and transferred. Frame size error control is performed here by tracking the data and signals received to compare them with a pre-configured parameters of the register space.

A Master AXI4-Memory Mapped is needed for interfacing with a slave that will be receiving the video content through the AXI4 data bus and put it in memory whenever the resource is available. This interface should be as optimized as possible for the system to lose less time possible on validations and responses.

There is a simple main state machine presented in Figure 3.11 whose main goal is to control the reading of the data previously buffered in circular buffers and transfer the data through the Master AXI4-Memory Mapped to save in external memory RAM.

(e)

Figure 3.11: Write subsystem of Memory Manager Main State Machine.

• RESET- This state, as the name implies, resets the entire hardware of the Memory Manager and takes the system to the initial state as well as the control registers and status. Additionally, both buffers for reading and write are taken to the initial address value.

• IDLE- When the subsystem is in this state it is waiting for a buffer to be full to be ready to initiate the transfer.

• READ BUFFER - In this state, the subsystem is reading from the currently active buffer until it reaches the last buffer address.

• READ BUFFER DONE- When the state machine reaches this state it triggers a pulse that notifies the end of a burst transaction for frame tracking purposes. It evolves immediately toIDLEorERROR.

• ERROR- If this state is reached, the system may halt, depending on the user configurations, and stays in this state until a restart or aRESETof the core is performed.

The buffering mechanism present in the core is actually a double buffering mechanism. This mechanism is designed to avoid race conditions, i.e., the simultaneous read and write of a memory address of a given buffer. If the buffer controller tries to write in a buffer still being read for data transfer by AXI4-Memory Mapped, it may mean the external memory resource is congested, and an error may be released in the status register. If this situation happens, the Memory Manager opts to write the new data coming in the same buffer again, i.e., it will not start writing in the next buffer once it is still being read.

Since the purpose of this core is to be self-sufficient in error recovery, it was designed an algorithm able to deal with the wrong frame size. Then, the system may keep running as if nothing would have happened. Once residual errors may happen during long periods of run time, there is not a demand to stop the system. If the system is able to understand and correct the error, it may keep running. In Figure 3.12 is presented a block diagram for offset control between frames.

Calculate next burst

Figure 3.12: Algorithm behind frame address offset controlling to prevent misaligned/wrong frames being saved in memory.

By analyzing the Figure 3.12, we can see that this block is receiving two input signals, End of Transaction and End of Frame. In the left part of the Figure, the value is calculated after each burst transaction whereas, in the right, the block is calculating the initial frame address of the next frame. Then, when the End of Frame signal is driven high, the current context of both blocks are compared for checking if the values match. If they match the system continues with its default execution as there is no error. If not, one of two things may happen: (i) The system halts and waits for a restart, or (ii) the offset is corrected and the Memory Manager keeps running. These errors arise due to a fault behavior of the video source and they are supposed to be residual. In such situations, the Memory Manager can correct the error and keep the system running, or it can simply stop. This a trade-off that the Memory Manager delegates to the final user of the video card. For this purpose, the user just needs to configure the Raw video control register.

The register to specify the memory size, Raw video Memory Size, will be used to calculate the last address of of the external RAM, which is used to reference the moment when memory should be rotated.

However, if this value is not divisible by the frame size in bytes it would be a problem because it is not recommendable that a frame should be split in memory. Moreover, due to the burst transaction, if this value would not be carefully calculated, the end of memory can coincide in the middle of a burst transaction.

As it is possible to observe in the example of Figure 3.13, there is enough memory space for at least three frames to be saved in memory. Since the configured memory size resulted in an end address not aligned with a complete frame saved in memory, the mechanism will identify that the N+4 frame cannot be fully saved in the remaining memory. Then, it will rotate immediately after the N+3 frame is saved in memory (at the 0×384000, in this case).

0x 258000

Figure 3.13: Example of buffer rotation when the configured address is not aligned to fill an entire frame YUV 4:2:2 640×480.

This mechanism is also used by the Read subsystem to read video frames from memory.