Testing and Programming PCBA s during Design and in Production

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Testing and Programming PCBA’s

during Design and in Production

Hogeschool van Arnhem en Nijmegen

6 June 2013

Rob Staals

JTAG Technologies

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The importance of Testing

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• Don’t ship bad boards to your customers, find problems before your

customers do.

• DOA’s (Death On Arrival) lead to huge costs (rule of ten)

The "rule of ten" specifies that it costs 10 times more

to find and repair a defect at the next stage of assembly.

the part itself

1 €

at sub-assembly

10 €

at final assembly

100 €

at the dealer/distributor

1.000 €

at the customer

10.000 €

•

Important to find defects in an early stage.

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What are you testing

Simplified statement:

If all components are correctly soldered

- the board should work

Assuming:

Design is right

Components are OK (1ppm - .1ppm)

Conclusion:

Testing the interconnections should be sufficient to

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Error analysis based on real PCBA production data

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26%

17%

12%

9%

10%

7%

6%

13%

Shorts incl.

SA1/SA0

Opens

Not placed

Upside

down

Careless

placement

Component

defect

Tombstoning

Others

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Commonly used Testmethods

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Functional vs Structural Test

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Functional Test

• Checks every function of the board

(interconnects are implicitly tested) - Manual creation of the tests

- Very difficult to diagnose, doesn’t pinpoint to the exact location of the problem - Requires highly skilled engineers

- Time consuming - Expensive

+ @Speed test, very good as final test to check specifications

Structural Test (AOI, AXI, FP and ICT)

• Checks the structure of the board

(interconnects, device orientation, device values etc.) - No @Speed test

+ Automatic generation based on the Netlist + Low cost

+ Pinpoints to the exact location of the problem

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FP and ICT interconnection test

The probes of a Flying Prober and In Circuit Tester are connected to a measurement system.

Compare this with the probes of a multimeter.

Moving around with the probes will pinpoint to the exact location of the interconnection problem.

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How to perform a Structural Test on a board

containing Hi-density devices like BGA’s

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The probes of a Flying Prober or In Circuit Tester require a minimum clearance and have no access to the BGA pins

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Boundary-scan

is the solution to the access problem

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What is Boundary-scan and how does it work

Official standard:

IEEE Std. 1149.1-1990

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Boundary-scan architecture

Core

The Boundary-scan architecture is a standard implementation in many devices, such as µControllers, DSPs, FPGAs etc..

I/0 I/0 I/0

I/0 I/0

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Boundary-scan architecture

16 Controller Instruction register Bypass TDI TMS TCK TRST Optional TDO Core Boundary-Scan Register BSR

TDI Test Data In

TDO Test Data Out

TMS Test Mode Select

TCK Test Clock

TRST Test Reset

Additional Testlogic and pins have been added

I/0 I/0 I/0

I/0 I/0

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Via TDI a Testvectors is shifted into the BSR

Instruction register Bypass TDI TDO Core 110011110 Testvector

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Shift-in Testvector via TDI

18 0 Controller Instruction register Bypass TDI TMS TCK TRST Optional TDO Core →11001111 Shift

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0 1 Instruction register Bypass TDI TDO Core

→

1100111 Shift

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20 0 1 1 Controller Instruction register Bypass TDI TMS TCK TRST Optional TDO Core →110011 Shift

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Shift-in Testvector via TDI

1 1 1 0 Instruction register Bypass TDI TDO Core →→11001 Shift

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22 1 1 1 1 0 Controller Instruction register Bypass TDI TMS TCK TRST Optional TDO Core →→1100 Shift

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1 1 0 1 1 0 Instruction register Bypass TDI TDO Core →→→110 Shift

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24 1 0 0 0 1 1 1 Controller Instruction register Bypass TDI TMS TCK TRST Optional TDO Core →→→→11 Shift

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Shift-in Testvector via TDI

0 0 1 1 0 1 1 1 Instruction register Bypass TDI TDO Core

→→→

1 Shift

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26 0 1 1 1 1 0 0 1 1 Controller Instruction register Bypass TDI TMS TCK TRST Optional TDO Core Shift →→→→

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UPDATE drives the BSR data

onto all pins simultaneously

0 1 1 1 1 0 0 1 1 Instruction register Bypass TDI TDO Core Update

0

1

0

1

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UPDATE command

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The UPDATE command can be compared with one probe of the multimeter, but than for all Bscan I/O pins

simultaneously (hundreds – thousands pins).

However for a proper interconnection measurement a second probe is required.

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CAPTURE simultaneously senses

the values on the pins and stores it in the BSR

Instruction register Bypass TDI TDO Core

1

0

1

0

1

0

1

0

The nets are at a certain logic level.

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CAPTURE simultaneously senses

the values on the pins and stores it in the BSR

30 1 1 0 0 1 0 1 0 1 Controller Instruction register Bypass TDI TMS TCK TRST Optional TDO Core Capture

1

0

1

0

1

0

1

0

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CAPTURE command

The Capture command can be compared with the second probe of the multimeter, but than for all Bscan I/O pins simultaneously.

The UPDATE and CAPTURE commands provides direct access to hundreds or thousands I/O pins.

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Shift-out captured data

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After the values on the pins have been captured into the BSR the result is shifted out via TDO. The result can be compared with the expected data. Any difference pin-points to the error location.

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Shift-out Captured data via TDO

1 0 1 1 0 1 1 1 0 Instruction register Bypass TDI TDO Core Shift 0 Result

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Shift-out Captured data via TDO

34 0 1 1 0 1 0 1 1 1 Controller Instruction register Bypass TDI TMS TCK TRST Optional TDO Core Shift 10 Result

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Shift-out Captured data via TDO

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Compare Captured data

with expected result

1 1 1 1 1 1 1 1 1 Instruction register Bypass TDI TDO Core 010001010 Result 011101010 Expected

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Example 1

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Test interconnections between Bscan devices

Core BP IR Controller Core BP IR Controller TDI TDO TMS TCK TDO TDI IC1 IC2

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Calculate the required Testvector

44 Core BP IR Controller Core BP IR Controller TDI TDO TMS TCK TDO TDI IC1 IC2

1. Calculate Testvector for testing the interconnects xx11111xx

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Shift-in testvector via TDI

Core BP IR Controller Core BP IR Controller TDI TDO TMS TCK TDO TDI IC1 IC2 SHIFT 1 1 1 1 1 xx11111xx Testvector

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UPDATE

3. The UPDATE command drives the testvector onto the pins of IC1 and thus on the corresponding nets.

UPDATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 xx11111xx Testvector

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CAPTURE

Core BP IR Controller Core BP IR Controller TDI TDO TMS TCK TDO TDI IC1 IC2 CAPTURE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 xx11111xx Testvector

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Shift-out result and compare with expected

5. The Captured result is shifted-out on TDO and compared with the expected value.

Any mismatch pin-points to the location of the failure. SHIFT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 Mismatch xx11111xx Testvector xx10111xx Result Caused by an open underneath this pin

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Compare Result with Expected

and Diagnose

Errors are shown in inverse video. In this case the result was a 0 however a 1 was expected.

The diagnostics pin-points to the exact error location

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Faultdetection

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With the aid of Intelligent testvectors

Opens

Shorts

SA1 and SA0

problems are easily detected

The Intelligent testvectors are based on an Enhanced Binary Search principle.

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Bscan Bscan

Testing connectivity of

Non-Bscan components

TDI Boundary-scan chain Non-Bscan

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Bscan Bscan

Testing connectivity

NAND Gate

52 TDI TDO Boundary-scan chain

&

Use Truthtable to stimulate the inputs and sense the outputs of the NAND using the Bscan cells.

A model contains information about the Truthtable. A B Y A B Y 0 0 1 0 1 1 1 0 1 1 1 0

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Bscan Bscan

Testing connectivity

MEMORY

TDI Boundary-scan chain

RAM

ADD Ctrl DATA

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Bscan Bscan

FLASH

A model contains all the information on how to get access to the FLASH. ADD

Ctrl

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Bscan Bscan

I/O plus Connector (1)

TDI Boundary-scan chain I/O C on ne ct or Loo p Ba ck C on n ec tor

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Bscan Bscan

Testing connectivity

I/O plus Connector (2)

56 TDI TDO

Boundary-scan chain

Use an external Bscan board with required # of I/O pins to get full access.

I/O C on ne ct or Ex ter n al Bs ca n b oa rd

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Bscan Bscan

Testing connectivity

serial devices like I2C, SPI etc.

TDI Boundary-scan chain

I2C

SDA SLC

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Using the JTAG interface for

Programming

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Programming

CPLD and FPGA

JTAG Logic

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Programming

CPLD and FPGA

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JTAG Interface

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Programming

CPLD and FPGA

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Bscan Bscan

Programming

external FLASH

FLASH

The Image file gets integrated in the Bscan Addr-Data-Ctrl patterns to program the FLASH. ADD

Ctrl

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Programming

Embedded Flash

JTAG Internal FLASH µController Core

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Demonstration

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Full access through the TAP

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Software tools

JTAG Live Buzz

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Supported controllers

www.jtaglive.com