Objectives. Units of Memory Capacity. CMPE328 Microprocessors (Spring ) Memory and I/O address Decoders. By Dr.

CMPE328 Microprocessors

(Spring 2007-08)

Memory and I/O address Decoders

By Dr. Mehmet Bodur

Dr.Mehmet Bodur, EMU-CMPE 2

CMPE328 Spring 2007-08

„ Define the capacity, organization and types of the semiconductor memory devices

„ Calculate the chip capacity and organization of memory chips from their pin layouts.

„ Compare various kinds of memory devices according their volatility, access time, and per bit prices .

„ Diagram various kind of memory address decoding circuits.

„ Diagram the address map of the devices in a memory address space.

„ Describe 16 bit memory access circuits.

Memory Fundamentals

„

Memory Capacity:

…measured in number of bits.

„

Memory Organization

…described in

number.of.words × wordsize

…Word-size is determined by the number.of.data.lines on the chip.

„

Example

…2764 is an EPROM with 8-data and 13-address lines:

„organization: 2¹³x 8-bit = 8k x 8-bit

„capacity: 64 kilo bit.

Section 10.1

Units of Memory Capacity

„ 1 bit stores one of two cases.

…Either 0, or 1. No other value is possible

„ 1 nibble= four bits. It stores one of 16 cases.

…BCD digits, hexadecimal digits, etc.

„ 1 byte= 8-bit. It stores one ASCII character.

„ 1kbit = 2¹⁰ bits = 1024 bits

…Almost one page of alphanumeric text.

„ 1kByte= 2¹⁰ Bytes = 1024 x 8 bits.

…Address lines A₀ to A₉specifies 1024 locations.

„ 1MByte = 2²⁰ Bytes = 1024 kBytes

„ 1Gbyte= 2³⁰ bytes = 1024 Mbytes

Section 10.1

1M A[0..19]

512k A[0..18]

256k A[0..17]

128k A[0..16]

64k A[0..15]

32k A[0..14]

16k A[0..13]

8k A[0..12]

4k A[0..11]

2k A[0..10]

1k A[0..9]

Mem Size Address

Pins

Dr.Mehmet Bodur, EMU-CMPE 5 CMPE328 Spring 2007-08

„

Memory Speed: (Memory Access Time)

…Read Cycle Time

„includes read access time and data transfer time …Write Cycle Time

„includes write access time and data write time.

…Memory Read/Write Cycle time is the maximum of read cycle and write cycle.

„

Other Characteristics

…Memory Power Consumption

…Number of write cycles.

Dr.Mehmet Bodur, EMU-CMPE 6

CMPE328 Spring 2007-08

„ Read Only Memory (ROM).

…Masked ROM (the fastest memory device)

…Programmable ROMÆ PROM also called OneTimeProgrammableROM

„ 512 x 8bit: T_rc<10ns)

„ 8k x 8bit: T_rc≈ 100ns

…Erasable-PROM Æ EPROM

(Erased in 10minutes under UV-A lamp)

„ Programming similar to OTP ROM. 2000 times programmable

„ 8k x 8bit: T_rc≈ 200ns

…Electrically Erasable- PROM Æ EEPROM

„ In-circuit Programming possible. 500 000 times programmable Erase or Write takes 5 .. 20ms, T_rc≈ 200ns

…Flash ROM.

„ Twc= 5...20ms/block (≈256 B .. 8kB ). 1000000 times progr.

„ Very large capacities possible (1 GByte, access time ≈200ns)

Memory Chips used in Microprocessors

„

27xxx:

EPROM

„

28Cxxx EEPROM

„

28Fxxx Flash ROM

Section 10.1

Typical Address Data and Control Lines of a ROM

„ A[0 .. n] Address lines

„ O[0 .. n] Output lines.

„ ~CE (or ~CS) Active-low Chip or Device enable

…Disabled device typically consumes 1mA while enabled device draws around 20mA.

„ ~OE Active low Output Enable

…Disabled output stays floating (output disconnected)

…Enabled output delivers the contents of addressed location only after the settling time is over.

„ ~Vpp, and ~PGM are programming related control signals.

Dr.Mehmet Bodur, EMU-CMPE 9 CMPE328 Spring 2007-08

Static RAM Devices

„ Static Random Access Memory (SRAM devices)

…typical 10ns < T_RWC< 250ns

(faster devices are expensive. Fast devices are used for Local Cache.)

…Various capacities possible.

„ 6116 (2k x 8-bit)

„ 6264 (8k x 8-bit)

„ 62256 (8k x 32-bit)

„ NV-RAMis a low-power SRAM.

… It has a Lithium Battery and power- control circuit. It has infinite write cycle life, and data retention over 10 years. (Config. RAM in PC’s)

…NVis abbreviation of non-volatile.

6116

Dr.Mehmet Bodur, EMU-CMPE 10

CMPE328 Spring 2007-08

Typical Memory Control Lines

„ ~CS ( ~chip select =~CE : ~chip enable)

„ ~WE(Write Enable)

„ ~OE (Output Enable)

DRAM Devices

DRAM devices use Address lines multiplexed.

Example:

64kx4 bit device needs A[0..15], but 16 lines are multiplexed to 8 lines.

At the edge of CAS device holds A[0...7].

At the edge of RAS device holds A[8..15].

Section 10.1

Properties of DRAM

„ DRAM memory cells are

…made of two transistors and a capacitor.

„ They are eight times cheaper than ten-transistor-flip-flops of SRAM circuits.

…The charge stored in the capacitor decays in 1ms.

„ It needs row-refresh circuitry additional to the row-column address multiplexing circuit.

„ The row-refresh and multiplexing requires DRAM controller circuits.

„ Example:

…8-bit row and 8-bit column decoders of 4464 DRAM works faster than a full 14-bit decoder of 62256 SRAM device.

…For 4464, a DRAM controller generates 256 refresh cycles at every millisecond.

Section 10.1

Dr.Mehmet Bodur, EMU-CMPE 13 CMPE328 Spring 2007-08

„ Address Decoding provides systematic generation of memory ~CS signals.

…The goal of address decoding is to enable only a single memory device

…Well known methods of address decoding:

„ AND-OR-COMPLEMENT, or NAND gate logic.

„ Using commercial decoder chips, LS138, LS139.

„ Using PROM, PLA, FPGA devices.

„ Current Technology uses programmable devices.

…We will see only by using gates, and decoder devices to understand the decoding process.

Dr.Mehmet Bodur, EMU-CMPE 14

CMPE328 Spring 2007-08

„

We limit designs only to SRAM and EPROM circuits.

„

We assume complete address decoding.

…All address lines must be included to decoding.

„

A memory system design shall be

accompanied by a memory address map.

…A memory address map is a table of Address Bus Lines, with corresponding status for each memory or decoder device.

8088 Memory/IO Decoding Circuits

„ Address lines A[0..19], Data lines D[0..7]

„ Control lines,

~MEMR, ~MEMW,

~IOR, ~IOW.

„ ROM must occupy the high end of the memory space ( …. to FFFFFh).

Section 10.2

Memory data-size expansion

„

p of 2

^k

× m-bit devices are

combined to form a 2

^k

× n-bits device, where n=p×m.

„

Example,

…k= 12, (2¹² =4k )

…m= 4 ; n=8 ; p=2 . 2×(4k×4-bit ) Æ4k×8-bit

A

WEOE CE

D A

WEOE CE

D

A[0..11]

A[0..11]

D[0..3]

D[4..7]

D[0..7]

A[0..11]

~OE

~WE

~CE

Both devices are active at the same instant. The first device gives first half of data, while second provides the other half

Section 10.2

Dr.Mehmet Bodur, EMU-CMPE 17 CMPE328 Spring 2007-08

Memory Address-Space Expansion

„

2

^p

of 2

^k

× n-bit devices are combined to form a 2

^k+p

× n-bit device.

„

Example,

…p= 2, (2^p=4 chips required)

…n=8

4×(4k×8-bit) Æ16k×8-bit

AOE WECE

D AOE WECE

D A WEOE CE

D AOE WECE

D

A[0..11]

A[0..11]

A[0..11]

A[0..11]

D[0..7]

D[0..7]

D[0..7]

D[0..7]

D[0..7]

WEOE

CE E SY0Y1

Y2Y3 A[0..13]

A[12..13]

At a given instant, only one of the devices is active. Active device depends on decoder output of A[12..13] lines.

Dr.Mehmet Bodur, EMU-CMPE 18

CMPE328 Spring 2007-08

Decoder Circuits – by NAND

„ 8088 Example:

… Design a decoder to select a 2716, and three 6116 devices:

6116–A, –B and –C shall be located starting from address 00000h.

„ Solution: start with address map

from 01000h . to 017FFh 0F

F0 01 01 01 0 1 0 0 0 0 0 0 6116-C 0

from 00800h . to 00FFFh 0F

F0 01 01 01 1 0 0 0 0 0 0 0 6116-B 0

from FF800h . to FFFFFh 01

01 01 01 01 1 1 1 1 1 1 1 1 2716 1

from 00000h . to 007FFh 0F

F0 01 01 01 0 0 0 0 0 0 0 0 6116-A 0

hex address A[0..3]

A[4..7]

A₈ A₉ A₁₀ A₁₁ A₁₂ A₁₃ A₁₄ A₁₅ A₁₆ A₁₇ A₁₈ A₁₉ Processor

„ internal decoded address lines are A[0..10] for 6116, and A[0..10] for 2716.

„ From the map, decide on the inverted/non-inverted inputs of NAND.

Memory Sub System for 8088 Example

„ The blue part is the memory address decoder circuit.

„ The complete circuit is the Memory Sub

System. A

~OE

~CE D

~OEA

~WE~CE D A

~WE~OE

~CE D

~OEA

~WE~CE

D ^D[0..7]

D[0..7]

D[0..7]

D[0..7]

6116-A

6116-B

6116-C

2716 A[0..10]

A[0..10]

A[0..10]

A[0..10]

A13A14 A15A16 A17A18 A19

A12A11

A11A12

A12A11 A13A14

A15A16 A18A17 A19

~MEMR

~MEMR

~MEMR

~MEMR

~MEMW

~MEMW

~MEMW

Section 10.2

Design a decoder to select a 2716, and three 6116 devices:

6116–A, –B and –C shall be located starting from address 00000h.

A11A12

Decoder Circuits – by NAND

„ 8088 Example:

… Design a decoder to select a 2764, and three 6116 devices:

6116–A, –B and –C shall be located starting from address 00000h.

„ Solution: start with address map

from 01000h . to 017FFh 0F

F0 01 01 01 0 1 0 0 0 0 0 0 6116-C 0

from 00800h . to 00FFFh 0F

F0 01 01 01 1 0 0 0 0 0 0 0 6116-B 0

from FE000h . to FFFFFh 01

01 01 01 01 01 01 1 1 1 1 1 1 2764 1

from 00000h . to 007FFh 0F

F0 01 01 01 0 0 0 0 0 0 0 0 6116-A 0

hex address A[0..3]

A[4..7]

A₈ A₉ A₁₀ A₁₁ A₁₂ A₁₃ A₁₄ A₁₅ A₁₆ A₁₇ A₁₈ A₁₉ Processor

„ internal decoded address lines are A[0..10] for 6116, and A[0..12] for 2764.

„ From the map, decide on the inverted/non-inverted inputs of NAND.

Section 10.2

Dr.Mehmet Bodur, EMU-CMPE 21 CMPE328 Spring 2007-08

„ The blue part is the memory address decoder circuit.

„ The complete circuit is the Memory Sub

System. A

~OE

~CE D

~OEA

~WE~CE D

~OEA

~WE~CE D

~OEA

~WE~CE

D ^D[0..7]

D[0..7]

D[0..7]

D[0..7]

6116-A

6116-B

6116-C

2764 A[0..10]

A[0..10]

A[0..10]

A[0..12]

A13A14 A15A16 A17A18 A19

A12A11

A11A12

A12A11 A13A14

A15A16 A18A17 A19

~MEMR

~MEMR

~MEMR

~MEMR

~MEMW

~MEMW

~MEMW

shall be located starting from address 00000h.

Dr.Mehmet Bodur, EMU-CMPE 22

CMPE328 Spring 2007-08

0 1 1 1 1 1 1 1 1 1 1 0 0 1

1 0 1 1 1 1 1 1 0 1 1 0 0 1

1 1 0 1 1 1 1 1 1 0 1 0 0 1

1 1 1 0 1 1 1 1 0 0 1 0 0 1

1 1 1 1 0 1 1 1 1 1 0 0 0 1

1 1 1 1 1 0 1 1 0 1 0 0 0 1

1 1 1 1 1 1 0 1 1 0 0 0 0 1

1 1 1 1 1 1 1 0 0 0 0 0 0 1

1 1 1 1 1 1 1 1 X X X 1 X X

1 1 1 1 1 1 1 1 X X X X 1 X

1 1 1 1 1 1 1 1 X X X X X 0

~Y7

~Y6

~Y5

~Y4

~Y3

~Y2

~Y1

~Y0 A B C

~E3

~E2 E1

Truth Table of 74LS130

A B

0 1 1 1 1 1 0

1 0 1 1 0 1 0

1 1 0 1 1 0 0

1 1 1 0 0 0 0

1 1 1 1 X X 1

~Y3

~Y2

~Y1

~Y0 B A

~E

Truth Table of 74LS139

Design with Decoders

„ We search patterns of address lines that matches to inputs of LS138 or LS139.

Design a decoder to select a 2764, and three 6116 devices:

6116–A, –B and –C shall be located starting from address 00000h.

B LS139A A

B LS139B A

from 01000h . to 017FFh 0F

0F 01 01 01 0 1 0 0 0 0 0 0 6116-C 0

from 00800h . to 00FFFh 0F

0F 01 01 01 1 0 0 0 0 0 0 0 6116-B 0

from FE000h . to FFFFFh 01

01 01 01 01 01 01 1 1 1 1 1 1 2764 1

from 00000h . to 007FFh 0F

0F 01 01 01 0 0 0 0 0 0 0 0 6116-A 0

hex address A[0..3]

A[4..7]

A₈ A₉ A₁₀ A₁₁ A₁₂ A₁₃ A₁₄ A₁₅ A₁₆ A₁₇ A₁₈ A₁₉ Processor

„ We used both halves of LS139 chip.

--- ~E ---

Section 10.2

Design with LS139

~OEA

~CE D

~OEA

~WE~CE D A

~WE~OE

~CE D

~OEA

~WE~CE

D ^D[0..7]

D[0..7]

D[0..7]

D[0..7]

6116-A

6116-B

6116-C

2764 A[0..10]

A[0..10]

A[0..10]

A[0..12]

A13A14 A15A16 A17

A13A14 A15A16 A17 A18A19

~MEMR

~MEMR

~MEMR

~MEMR

~MEMW

~MEMW

~MEMW A12A11

Design a decoder to select a 2764, and three 6116 devices:

6116–A, –B and –C shall be located starting from address 00000h.

WITH LS139 decoder

GND

Section 10.2

Dr.Mehmet Bodur, EMU-CMPE 25 CMPE328 Spring 2007-08

Design with Decoders

„ Using only LS138, the address map will look like this one.

Design a decoder to select a 2764, and three 6116 devices:

6116–A, –B and –C shall be located starting from address 00000h.

A B LS138-1 C

A B C LS138-2 ~E2

from 01000h . to 017FFh 0F

0F 01 01 01 0 1 0 0 0 0 0 0 6116-C 0

from 00800h . to 00FFFh 0F

0F 01 01 01 1 0 0 0 0 0 0 0 6116-B 0

from FE000h . to FFFFFh 01

01 01 01 01 01 01 1 1 1 1 1 1 2764 1

from 00000h . to 007FFh 0F

0F 01 01 01 0 0 0 0 0 0 0 0 6116-A 0

hex address A[0..3]

A[4..7]

A₈ A₉ A₁₀ A₁₁ A₁₂ A₁₃ A₁₄ A₁₅ A₁₆ A₁₇ A₁₈ A₁₉ Processor

„ We used two LS138 chips.

~Y0 ~E3

Dr.Mehmet Bodur, EMU-CMPE 26

CMPE328 Spring 2007-08

Design with LS138

~OEA

~CE D

~OEA

~WE~CE D

~OEA

~WE~CE D

~OEA

~WE~CE

D ^D[0..7]

D[0..7]

D[0..7]

D[0..7]

6116-A

6116-B

6116-C

2764 A[0..10]

A[0..10]

A[0..10]

A[0..12]

A13 A15A16

A17A18 A19

A13A14 A15A16

~MEMR

~MEMR

~MEMR

~MEMR

~MEMW

~MEMW

~MEMW A12A11

select a 2716, and three 6116 devices:

6116–A, –B and –C shall be located starting from address 00000h.

WITH LS138 decoders

Vs A14

GNDVs GND

Example-2

„ Design a memory subsystem to have

„ one 6116 starting from address 62000h, two 6264 RAM from 64000h, and

„ one 62256 from 68000h using LS138 decoders.

A B C LS138-1 ~E2

from 66000h . to 67FFFh 01

01 01 01 1 1 0 0 1 1 6164-B 0

from 64000h . to 65FFFh 01

01 01 01 0 1 0 0 1 1 6164-A 0

from 68000h . to 6FFFFh 01

01 01 01 01 01 1 0 1 1 62256 0

from 62000h . to 627FFh 01

01 0 0 1 0 0 0 1 1 6116 0

hex address a₀

a₁₀ a₁₁ a₁₂ a₁₃ a₁₄ a₁₅ a₁₆ a₁₇ a₁₈ a₁₉ Processor

~E3 E1

Section 10.2

A

~OE~WE

~CE

D ^D[0..7]

6116-A

~OEA

~WE~CE

D ^D[0..7]

6264-A

~OEA

~WE~CE

D^D[0..7]

6264-B

~OEA

~WE~CE

D^D[0..7]

62256 A[0..10]

A[0..12]

2kx8bit

A[0..12]

8kx8bit

32kx8bit 8kx8bit

A[0..14]

A12 A11

~MEMR

~MEMW

~MEMR

~MEMW

~MEMW~MEMR

~MEMW~MEMR

A17A16 A13A14 A15

A19 A18

~[40000h … ~7FFFFh]

~[62000h … 63FFFh]

~[62000h … 627FFh]

in an address decoding circuit you can determine

the address range of a select output by making non-processed address

lines “0” and “1”.

Data Integrity of PC Memory

„ ROM memory system.

…On Power-Up, boot program tests the sum of all bytes in ROM to test any failure of the ROM block.

(It is called CHECKSUM test).

„ DRAM memory system

…Organized in 9-bit words.

…There is a parity generator-tester 74S280

„ When writing data, it puts into 9^thbit a parity bit (that completes the 8 data bits to even parity)

„ When reading data, it tests parity bit. If parity fails, it generates a non-maskable interrupt to give a memory error message.

…It is called parity-test

Section 10.4

Dr.Mehmet Bodur, EMU-CMPE 29 CMPE328 Spring 2007-08

system organized in two banks.

… Bank-0 (even) connected to D[0..7]

It is Activated by A0 is low

… Bank-1 (odd) connected to D[8..15].

It is activated by BHE is low.

„ 16-bit bus doubles data transfer rate.

to other even banks

to other odd banks decoding circuit

chip select

BHE D[8 ..15].

.

74LS245 74LS245 D[0 ..7].

.

Look at how the address lines are shifted

one bit.

Dr.Mehmet Bodur, EMU-CMPE 30

CMPE328 Spring 2007-08

„ The data rate of a bus is mostly called the Bus Bandwidth.

… Bus Bandwidth = bus-width / bus-cycle-time.

(measured in MBytes/sec)

„ Example:

… 8088 bus takes 4 processor cycles to carry out 8-bit memory read or write cycles. Find Bus Bandwidth of a 20MHz 8088 system.

„ Bus-Bandwidth₈₀₈₈= 1byte 20MHz / 4 proc-cyc. = 5 MB/s … 80286 bus takes 2 processor cycles for a 16-bit

memory read or write. Find Bus Bandwidth of a 20 MHz 80286 system.

„ Bus-Bandwidth₈₀₂₈₆= 2bytes 20MHz / 2proc-cyc = 20 MB/s … Buses with wait cycles will have smaller bandwidth.

What is the Next?

„

Next we will start to hardware and software to use IO ports (IO ports).

„

Please solve the problems (p.303) for

Section 10.1, 10.2, 10.3, 10.4, 10.5,