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Peripheral Devices

Input-Output Interface

Asynchronous Data Transfer

Modes of Transfer

Direct Memory Access

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PERIPHERAL DEVICES

Input Devices

Keyboard

Optical input devices - Card Reader

- Paper Tape Reader - Bar code reader - Digitizer

- Optical Mark Reader

Magnetic Input Devices - Magnetic Stripe Reader

Screen Input Devices - Touch Screen

- Light Pen - Mouse

Analog Input Devices

Output Devices

Card Puncher, Paper Tape Puncher

CRT

Printer (Impact, Ink Jet, Laser, Dot Matrix)

Plotter

Analog

Voice

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* Provides a method for transferring information between internal storage (such as memory and CPU registers) and external I/O devices

* Resolves the differences between the computer and peripheral devices

- Peripherals - Electromechanical Devices CPU or Memory - Electronic Device

- Data Transfer Rate

Peripherals - Usually slower

CPU or Memory - Usually faster than peripherals

Some kinds of Synchronization mechanism may be needed

- Unit of Information Peripherals - Byte

CPU or Memory - Word

- Operating Modes

Peripherals - Autonomous, Asynchronous CPU or Memory - Synchronous

INPUT/OUTPUT INTERFACES

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Types of data

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Synchronous vs ASYNCHRONOUS DATA TRANSFER

Synchronous - All devices derive the timing

information from common clock line Asynchronous - No common clock

Asynchronous data transfer between two independent units requires that

control signals be transmitted between the communicating units to indicate the time at which data is being transmitted

Strobe pulse

- A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to occur

Handshaking

- A control signal is accompanied with each data being transmitted to indicate the presence of data - The receiving unit responds with another control signal to acknowledge receipt of the data

Synchronous and Asynchronous Operations

Asynchronous Data Transfer

Two Asynchronous Data Transfer Methods

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Asynchronous Transfer

Asynchronous transmission sends only one character at a time

where a character is either a letter of the alphabet or number or

control character

i.e.

it sends one byte of data at a time.

Bit synchronization between two devices is made possible using

start bit and stop bit.

Start bit indicates the beginning of data

i.e.

alerts the receiver to

the arrival of new group of bits. A start bit usually 0 is added to the

beginning of each byte.

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Asynchronous Transfer

Addition of start and stop increase the number of data bits. Hence

more bandwidth is consumed in asynchronous transmission.

• There is idle time between the transmissions of different data

bytes. This idle time is also known as Gap

 • The gap or idle time can be of varying intervals. This mechanism

is called Asynchronous, because at byte level sender and receiver need not to be synchronized. But within each byte, receiver must be synchronized with the incoming bit stream.

Asynchronous transmission is well suited for keyboard

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Synchronous Transfer

Synchronous transmission does not use start and stop bits.

In this method bit stream is combined into longer frames that may

contain multiple bytes.

There is no gap between the various bytes in the data stream.

In the absence of start & stop bits, bit synchronization is established

between sender & receiver by 'timing' the transmission of each bit.

• Since the various bytes are placed on the link without any gap, it is the

responsibility of receiver to separate the bit stream into bytes so as to

reconstruct the original information.

• In order to receive the data error free, the receiver and sender operates at

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Synchronous Transfer

Synchronous transmission is used for high speed communication

between computers.

This method is faster as compared to asynchronous as there are no

extra bits (start bit & stop bit) and also there is no gap between the individual data bytes.

It is costly as compared to asynchronous method. It requires local

buffer storage at the two ends of line to assemble blocks and it also requires accurately synchronized clocks at both ends. This lead to increase in the cost.

The sender and receiver have to operate at the same clock frequency.

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I/O BUS AND INTERFACE MODULES

Each peripheral has an interface module associated with it

Interface

- Decodes the device address (device code) - Decodes the commands (operation)

- Provides signals for the peripheral controller - Synchronizes the data flow and supervises

the transfer rate between peripheral and CPU or Memory Typical I/O instruction

(Command) Op. code Device address Function code

Input/Output Interfaces Processor Interface Keyboard and display terminal Magnetic tape Printer

Interface Interface Interface

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Major functions of I/O

module/interface

The major functions of modules are categorized as

follows

1. Control and Timing - In some of the I/O operation few

resources shared such as CPU and memory because CPU communicates with more than one device at a time.

2. Processor Communication - I/O module communicates

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CONNECTION OF I/O BUS

Connection of I/O Bus to One Interface Connection of I/O Bus to CPU

Input/Output Interfaces

I/O bus

Op.

code addressDevice Functioncode Accumulatorregister

Computer I/O control

Sense lines Data lines

Function code lines Device address lines

CPU I/O bus Device address Command decoder Function code Data lines Buffer register Peripheral register Status register Sense lines Input/Output peripheral device and controller AD = 1101 Interface

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I/O Bus

Communication between CPU and all interface units is via a

common I/O Bus

- An interface connected to a peripheral device may have a

number of data registers , a control register, and a status register

- A command is passed to the peripheral by sending to the

appropriate interface register

- Function code and sense lines are not needed (Transfer of

data, control,

and status information is always via the common I/O

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I/O BUS AND MEMORY BUS

* MEMORY BUS is for information transfers between CPU and the Memory Module

I/O BUS is for information transfers between CPU and I/O devices through their I/O interface

* Many computers use a common single bus system for both memory

and I/O interface units

- Use one common bus but separate control lines for each function

- Use one common bus with common control lines for both functions

* Some computer systems use two separate buses,

one to communicate with memory and the other with I/O interfaces Functions of Buses

Input/Output Interfaces

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ISOLATED vs MEMORY MAPPED I/O

- Separate I/O read/write control lines in addition to memory read/write control lines

- Separate (isolated) memory and I/O address spaces - Distinct input and output instructions

Isolated I/O

Memory-mapped I/O

- A single set of read/write control lines

(no distinction between memory and I/O transfer) - Memory and I/O addresses share the common address space -> reduces memory address range available

- No specific input or output instruction

-> The same memory reference instructions can be used for I/O transfers

- Considerable flexibility in handling I/O operations

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I/O INTERFACE

- Information in each port can be assigned a meaning depending on the mode of operation of the I/O device -> Port A = Data; Port B = Command; Port C = Status

- CPU initializes(loads) each port by transferring a byte to the Control Register -> Allows CPU can define the mode of operation of each port

-> Programmable Port: By changing the bits in the control register, it is possible to change the interface characteristics

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence 1 0 0 Port A register

1 0 1 Port B register 1 1 0 Control register 1 1 1 Status register

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UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER

UART

-A typical asynchronous communication interface available as an IC

Transmitter Register

- Accepts a data byte(from CPU) through the data bus - Transferred to a shift register for serial transmission Receiver

- Receives serial information into another shift register - Complete data byte is sent to the receiver register Status Register Bits

- Used for I/O flags and for recording errors Control Register Bits

- Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of stop bits

Chip select Register select I/O read I/O write CS RS RD WR Timing and Control Bus buffers Bidirectional data bus Transmitter register Control register Status register Receiver register Shift register Transmitter control and clock Receiver control and clock Shift register Transmit data Transmitter clock Receiver clock Receive data

Asynchronous Data Transfer

CS RS Oper. Register selected 0 x x None

1 0 WR Transmitter register 1 1 WR Control register 1 0 RD Receiver register 1 1 RD Status register

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Basic I/O Techniques

1. Programmed I/O

2. Interrupt I/O

References

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