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FIGURE 1. When converting rms noise to peak-to-peak noise a crest factor can be used as a multiplying constant which predicts the probability of peaks occurring beyond the peak-to-peak noise calculation.
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©1997 Burr-Brown Corporation AB-120 Printed in U.S.A. September, 1997
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The ADS1210 and ADS1211 are precision, wide dynamic range, ∆Σ A/D converters that have 24 bits of no missing code and up to 23 bitsrms of effective resolution. Because of the nature of the ∆Σ design architecture the circuit designer has control over more of the variables and interface options in the A/D’s conversion process than is realizable with other converter architectures. These options are digi- tally implemented and include analog input configuration, oversampling, calibration and digital protocol control. Con- sequently, these A/D converters can service a wide variety of applications, including high precision, high speed, and low power.
There is the subset of conditions that must exist before 23 bits rms of resolution can be achieved with the ADS1210/11. The manipulation of these A/D functions as well as practical layout recommendations are discussed in this application note.
23-BITSrms OF EFFECTIVE RESOLUTION DEFINED Effective number of bits or effective resolution is a term that was developed with the arrival of the 16+ bit converters.
These high resolution converters were capable of outputting more bits than could accurately be digitized with one con- version. With careful layout practices, this degree of uncer- tainty was and still is predominately a consequence of device noise. Multiple conversions, along with mathemati- cal manipulation, reliably produces a higher effective reso- lution at the expense of overall conversion speed. The addition of a DSP or µC type device is required in the application to accomplish this type of performance improve- ment. The topology of ∆Σ converter relieves the board level designer of the intensive DSP software design work by incorporating the over sampling and digital filtering inside the A/D chip.
The high resolution ∆Σ converters, such as the ADS121x family from Burr-Brown, advertise an effective resolution up to 23 bitsrms in a 10Vp-p Full-Scale-Range at a 100Hz data rate. This translates to 0.975µVrms of effective resolu- tion. For the remainder of this discussion, “effective”
defines the rms digital output of the ADS1210/11 when configured in a full-scale input range of 10V and a Program- mable Gain setting of one. This performance exceeds other A/D converter topologies, such as the SAR (Successive Approximation) designs. As an extra bonus, the ∆Σ con- verter applications are less expensive than the precision SAR converter applications.
Although the ∆Σ converter absorbs the computational overhead of the digital filtering function, there is a slight variation for digital output to digital output. The accuracy of the digital output code is affected by the cumulative noise at the time of the conversion. This noise can be generated by the circuit and injected into the A/D converter through the input pins, reference pin or power supply connections.
Alternatively, the noise can also be generated by the device itself. Effective resolution is defined as the statistical stan- dard deviation (Vrms) of multiple conversions. A sample size of 256 was used to characterize the ADS121x family of products. Smaller sample sizes are also appropriate.
Although noise is a random event and any amplitude is theoretically possible, the occurrence of each output over time can be reliably predicted with the Gaussian distribution statis- tical model. When the rms value is multiplied by twice the crest factor, a peak-to-peak equivalent can be computed. The Gaussian distribution, shown in Figure 1, illustrates that the likelihood of large values decrease with increased magnitude.
The probability of exceeding a value above the rms (one standard deviation) can be anticipated with a crest factor (peak/rms). Peak-to-peak values can be predicted with a 2x crest factor. Figure 1 illustrates the probability of a specific output deviation for the average output vs the 2x crest factor multiple. For instance, with an effective resolution of 1µVrms, the probability of a sample exceeding ±2.625µV (2x crest factor = 5.25) from the average output is 0.01. If a 2x crest factor of 6.6 is applied, the probability of the output exceeding
±3.3µV of the average output is 0.001.
HOW TO GET 23 BITS OF EFFECTIVE RESOLUTION FROM YOUR 24-BIT CONVERTER
By Bonnie C. Baker
1.0 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 0.00000001 0.000000001
P-P NOISE CALCULATIONS FROM RMS
Probability of Higher Peaks
2 3 4 5 6 7 8 9 10 11
2x Crest Factor (Vp-p/Vrms)
12
The 2x crest factor constant can be chosen to meet the application need, however, 6.6 is the standard that Burr- Brown has chosen to use to define “Noise Free Bits”. With this 2x crest factor,
Noise Free Bits = Effective bitsrms – 2.723 bits.
Using the ADS1210/11 as an example, Table I illustrates the relationship of bitsrms (FSR = 10V), Vrms, p-pV and Noise Free Bits (FSR = 10V). In this table the data rate is defined as the frequency of the digital output data produced by the converter. The Turbo Mode (in this case, 16) is an ADS1210/11 feature that is used to increase the modulator sampling rate by 2, 4, 8 or 16 times normal. An increase in sampling rate is equated with an increase in effective resolution.
PROGRAM THE CONVERTER’S TURBO MODE AND DECIMATION RATIO
The ADS1210/11 default data rate is (850 x XIN/107)Hz. For example, if the external clock to the A/D converter (XIN) is 10MHz, the default data rate would be 850Hz. The data rate of the A/D converter is easily measured by putting a oscil- loscope probe on the DRDY pin. This default data rate is achieved with a decimation ratio of 23 (decimal) and a turbo mode of one. When the ADS1210/11 is programmed in this manner, the expected effective resolution is approximately 12 bitsrms (given XIN = 10MHz). Before 23 bitsrms of effective resolution can be realized, the turbo mode and decimation ratio must be re-programmed into the A/D converter. Table III lists the suggested turbo mode and decimation ratio vs external clock (XIN) that is required to get 23 bitsrms effective resolution.
It is useful to note that the setting for the Programmable Gain Amplifier (PGA) inside the ∆Σ converter is always configured as equal to one if 23 bits rms of effective resolution is the desired goal.
NOISE LEVEL (µVrms)
DATA TURBO TURBO TURBO TURBO TURBO
RATE MODE MODE MODE MODE MODE
(Hz) RATE = 1 RATE = 2 RATE = 4 RATE = 8 RATE = 16
10 2.9 1.7 1.3
20 4.3 2.1 1.7 1.3
40 6.9 3.0 2.3 1.6 1.0
50 8.1 3.2 2.4 1.8 1.0
60 10.5 3.9 2.6 1.9 1.0
100 26.9 6.9 3.5 2.7 1.4
1000 6909.7 1354.4 238.4 46.6 7.8
TABLE II. This table demonstrates that the performance of the ADS1210 and ADS1211 can be adjusted with changes in Turbo mode and decimation ratio.
With the ADS1210/11, the turbo mode function allows the user to program the over sampling speed of the converter.
The turbo mode function is the key to achieving 23 bitsrms of effective resolution. As the turbo mode is increased, the effective resolution is also increased. Table II shows the relationship between Turbo Mode and various data rates.
EFFECTIVE
EFFECTIVE RESOLUTION EFFECTIVE DATA EFFECTIVE RESOLUTION (p-pµVrms, NOISE RATE (Hz) BITSrms (µVrms) 2x crest factor = 6.6) FREE BITS
40 23.0 1.0 6.6 20.28
50 23.0 1.0 6.6 20.28
60 23.0 1.0 6.6 20.28
100 22.5 1.4 9.24 19.78
1000 20.0 7.8 51.48 17.28
TABLE I. Using the ADS1210/11 as an example, the various ways of calculating the accuracy of the conversion process are shown.
The translation from effective bits to effective resolution or visa versa is:
ER in bits rms=
20 • log 10V ER in Vrms
– 1. 76 6. 02
ER in Vrms= 10V
10
6. 02 • ER in bits rms+1. 76 20
ACCEPTABLE
EXTERNAL CLOCK RECOMMENDED DECIMATION EXPECTED FREQUENCY, XIN TURBO MODE RATIO(s) DATA RATE (Hz)
10MHz 16 5200 to 8000 40Hz to 60Hz
5MHz 8 7812 10Hz
2.5MHz 16 7812 10Hz
TABLE III. The A/D converter’s turbo mode and decimation ratio must be re-programmed from its default setting in order to achieve 23 bitsrms of effective resolution.
FOLLOW GOOD GROUND AND POWER PLANE LAYOUT PRACTICES
The best layout approach is to power the analog section of the A/D converter from one supply and the digital section from a separate +5V supply. In this configuration, the analog supply should come up first insuring that the substrate is not reverse biased causing a latch condition. Good decoupling practices should be used for the A/D converter on both the analog and digital supplies. A 1µF to 10µF capacitor, in parallel with a 0.1µF ceramic capacitor is recommended. All decoupling capacitors should be placed as close to the device as possible, particularly the 0.1µF ceramic capaci- tors. For either supply, high frequency noise will generally be rejected by the digital filter except for integer multiples of the modulator frequency. In particular, the analog supply should be well regulated and with low noise. The Power Supply Rejection vs Frequency graph shown in Figure 2.
The DEM-ADS1210/11 can be used to illustrate the impor- tance of these grounding and power supply practices. Since the segregation of the analog and digital supplies on the power plane and ground plane is the same, the ground plane is shown in Figure 3 and used for this discussion. The device’s analog pins (1, 2, 3, 4, 5, 6, 7, 19, 20, 21, 22, 23, and 24 in the case of the ADS1211) are all on the analog ground and power plane. The device’s digital pins (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 in the case of the ADS1211) are
85.0
80.0
75.0
70.0
65.0
PSRR vs FREQUENCY
PSRR (dB)
0.1 1 10 100
Frequency (Hz)
1k 10k 100k
FIGURE 3. The DEM-ADS1210/11 demonstration fixture analog and digital power planes are separated as shown above.
FIGURE 2. Good grounding practices and layout practices suggest that the analog and digital power planes be separate.
The ADS1210 and ADS1211 power supply rejection versus frequency are shown here, emphasizing that noise reduction techniques should be applied to the power supply busses.
all on the DUT (Device Under Test) digital ground and power plane (see Figure 3). The digital pins of the A/D converter interface to the “DUT Controller” µP, 8xC51 (U4).
This µP and the “Memory Controller” µP (8xC51, U5) along with the digital memory chips have their own ground and power plane that are partially partitioned from the DUT digital ground and power plane. With this layout, the current paths of the digital portion of the board are steered towards the power connector instead of past the digital side of the A/
D converter. Power is supplied to the board via the analog power supply connector, P4, and the digital supply connec- tor, P5.
At first glance, this layout would suggest that the demo board designer has gone to extraordinary efforts to optimize
the board layout for these high resolution ∆Σ converters. If the A/D converter plus a few logic chips were the only parts on the board, the ground and power plane layout restrictions can be relaxed. If there is a minimum amount of glue logic in the layout, the A/D converters can achieve 23 bits of resolution with one ground and power plane. The key to a successful 23-bit system is to keep the digital return currents away from the analog front end of the circuit. Pay particular attention to the clocking network’s current paths and high frequency coupling. Extra caution should be taken with the surface mount versions of the ADS1210 and ADS1211.
Since the substrate of the chip is physically closer to the board than it would be with a plastic DIP, the power plane and ground plane should be removed from underneath the chip.
The DEM-ADS1210/11 board lends itself for easy experi- mentation in exploring different power layout configura- tions. The results are summarized in Table IV.
It is useful to note that the DEM-ADS1210/11 has a fair amount of logic on the board, including two µP and an array of memory chips. The data in Table IV illustrates the affects of digital noise coupling into the analog signal path and consequently increasing the noise floor.
SELECT THE RIGHT EXTERNAL CLOCK SOURCE The type of clock that is used with the ADS121x does have an effect on the noise performance of the device, particularly when calibration is used. The noise seems to increase as the clock gets further away from a perfect sine wave. For instance, a square wave that is rich in harmonics can cause the most problems.
A square wave is rich is harmonics which are easily coupled from trace-to-trace or from the digital-to-analog planes.
Careful layout may reduce the affects of this noise source. In terms of calibration, the self calibration process of the
nodes. In these application, operation should improve if a system calibration is used.
AN EXTERNAL VS INTERNAL 2.5V REFERENCE An external reference is recommended for the circuit design where 23 bitsrms effective resolution is the design goal. The recommended circuit configuration is shown in Figure 4. In this circuit a REF1004-2.5, 2.5V reference from Burr-Brown is used. This same reference chip along with the support circuitry is implemented on the demonstration fixture for the ADS1210 and ADS1211, (DEM-ADS1210/11). The internal reference for the device will usually provide at most 20 bitsrms, regardless of the other measures to achieve optimum performance. Since the ADS1210 and ADS1211 reference is a CMOS reference, it has more noise than an equivalent bipolar reference. The effective resolution graphs included in the product data sheet for the ADS1210/11 products were generated with an external reference (REF1004-2.5).
SPECIAL CARE WITH THE INPUT PINS
In terms of the differential analog inputs, there is one pair inputs with the ADS1210 and four pairs with the ADS1211.
Three techniques can be used to reduce the input noise to the converter at these pins. A primary consideration is to make
FIGURE 4. This is the recommended external reference circuit for the ADS1210 and ADS1211 when an effective resolution of 23 bits rms is required.
AIN4P AIN4N AIN3P AIN3N AIN2P AIN2N AIN1P AIN1N VBIAS AGND AVDD
REFIN
REFOUT 22
23 24 1 2 3 4 5 7 6 19
21
20
XOUT
XIN
MODE
ADS1211 R13
0Ω
C2 10µF
U3 REF1004
C9 1µF
C15 0.1µF +5V
50kR8Ω 1
J4 DRDY
SDOUT SDIO SCLK DSYNC CS
17 16 15 14 9 8
DVDD
DGND 12 13 10
18 11
Analog Power Supply
EFFECTIVE EFFECTIVE RESOLUTION RESOLUTION
TEST CONDITIONS (µVrms) (Bits rms)
Short analog and DUT digital ground and power 18 18.8 at the chip by shorting pin 6 (AGND) to pin 12
(DGND) and pin 19 (AVDD) to pin 13 (DVDD).
Short analog and DUT digital ground at the 18 18.8 chip by shorting pin 6 (AGND) to pin 12 (DGND).
Short analog and DUT digital power at the chip 18 18.8 by shorting pin 19 (AVDD) to pin 13 (DVDD).
Short analog and DUT digital ground and power 5 20.6 at the edge of the board by inserting a shorting
bar in R1 (for ground short) and CRN2 (for power plane short).
Short analog and DUT digital ground at the 5 20.6 edge of the board by inserting a shorting bar
in R1.
Short analog and DUT digital power at the edge 5 20.6 of the board by inserting a shorting bar CRN2.
Connect the power to the board from the bench 1 23 power supply with four one inch wires.
TABLE IV. ADS1211, XIN = 10MHz, data rate = 60Hz, Turbo Mode = 16, PGA = 1, expected number of effective bits rms = 23.
converter disconnects the inputs from the input pins and performs the self calibration. Once the device goes into normal operation, the noise from a non-perfect sine wave oscillator can be coupled into the high impedance input
the leads from the input sources as short as possible. This is done to avoid EMI effects that could be coupled into the inputs pins of the converter. A 0.1µF capacitor should be placed directly across the differential inputs. This is done to attenuate high frequency noise that is present at the input pins of the device. The third noise reduction technique is to insert an anti-aliasing filter on each analog input pin. This is recommended to reduce high frequency out of band noise from entering the converter and aliasing into the digital output signal.
When testing these noise reductions techniques, the user should be aware of a specific type of device noise that is shown in Figure 5. This type of noise is known to exist in converters using the ∆Σ topology. Certain low voltage inputs create a low level rms noise at the output of the A/D converter. These outputs seem to have a low frequency component or tone.
of 1, and decimation ratio of 195 giving a data rate of 100Hz.
The average output of this data (referred to voltage input) is 43µV with a standard deviation of 32µVrms. The expected performance of the ADS1211 in this configuration is 1.4µVrms, per Table II. The data in Figure 7 is taken from the same device with a slight variation in the layout. The length of the converter input leads is changed from six inches to one inch.
FIGURE 7. This data is taken from the same device in the same conditions as in Figure 5 with a slight variation in the layout. The length of the input leads is changed from six inches to one inch.
The tones originate when the modulator output is 10101010...or 110110110... or 001001001001, etc. That is, the modulator output is a very short sequence of 1s and 0s that repeat very often. This produces digital numbers in the digital filter that are close to a “major” bit transition (such as 0111111... 1000000...). Every so often, the modulator output skips a sequence. For example, 10101010 becomes 10010101.
This occasional skip seems to come along at a very low frequency. Thus, the digital filter “believes” that there is actually a low-level signal there.
An example of this idle tone is shown in Figure 6. These tones are very difficult to find and are usually the last issue to deal with when trying to obtain 23 bitsrms of effective resolution. In the example in Figure 6, the A/D converter, ADS1211, is configure in a PGA gain of one, Turbo mode
RMS NOISE vs INPUT VOLTAGE LEVEL (60Hz Data Rate)
Analog Input Differential Voltage (V)
–5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0
RMS Noise (ppm)
2.5
2.0
1.5
1.0
0.5
FIGURE 5. The noise shown in this graph is only apparent after the noise levels of the ADS1210 and ADS1211 conver- sion process has been reduced through techniques discussed in this application. These techniques include proper pro- gramming of the modulator, proper data rates, and proper power plane layout.
FIGURE 6. The peaks shown in Figure 4 have a very low frequency content. The frequency and magnitude of these tones changes with layout and A/D converter programming of turbo mode and data rate. This data was taken with the a XIN of 10MHz, PGA of 1, decimation ratio of 195 and a turbo mode of one.
ADS1210
TURBO 16, PGA 1, DR 3125, 100Hz, VIN = 0V
Samples
1 51 101 151 201 251
One Tenth Volts
1.00E 0.00E –1.00E –2.00E –3.00E –4.00E –5.00E –6.00E –7.00E –8.00E –9.00E
ADS1210
TURBO 16, PGA 1, DR 3125, 100Hz, SMALL INPUT
Samples
1 51 101 151 201 251
One Tenth Volts
–2.22E
–2.24E
–2.26E
–2.28E
–2.30E
–2.32E
–2.34E
–2.36E
Also, note that the characteristics of the tone is depen- dent on the layout of the ADS1210/11. We have taken an ADS1210/11 out of the demonstration board socket (DEM-ADS1210/11), plugged it back in, and seen a change in the oscillation amplitude and frequency. A soldered part, particularly a surface mount part, should have smaller idle tones and better performance.
Another way to reduce the idle tone problem is to introduce a small offset voltage to the signal. As illustrated in Figure 5, a small offset voltage can take the converter away from the sensitive input voltages that cause the problem.
CONCLUSION
The short cut to 23 bitsrms of effective resolution with the ADS1210 and ADS1211 gives attention to optimizing the converter’s programming, circuit layout, a proper clock source, and special care with the analog input pins. The
converter should be configured in a Turbo Mode of 16 and data rates from to 10Hz to 60Hz. The analog and digital power and grounds should be carefully separated for optimal performance. A crystal oscillator is recommended, although, clock oscillators can be used with great care. An external reference is also recommended if 23 bitsrms is the desired effective resolution. The analog input leads to the input of the A/D converter must be a short as possible and properly filtered.
REFERENCES
(1) Ryan, Scranton, “DC Amplifier Noise Revisited”, Analog Devices, Analog Dialogue, 1984, pg 18-1.
(2) “ADS1210, ADS1211, 24-bit Analog-to-Digital Converter”, Product Data Sheet PDS-1248, Burr-Brown Corporation.
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