e, and Suite 301 Copyright Reproduction

(1)

Augus

The G

150 B

Suite 3

Conco

www.g

st 2008

Gantry Gr

aker Ave

301 ord, MA 0

gantrygro

Sy

Wh

Des

Sol

IP R

Com

roup, LLC

enue

01742

oup.com

RO

ynch

itepap

sign C

ution

Reuse

mplex

C

m

I Im

of

roni

Dat

per:

Collab

s Con

e, and

xity

mpac

f EN

icity

ta M

borati

ntrol C

d Man

ct An

OVI

y De

Mana

ion &

Costs

nage I

naly

IA

sign

ager

Mana

s, Enc

ncrea

ysis

nSyn

r

agem

coura

ased

nc

®

ent

age

(2)

List of Tables

Table 1 Business Impact of ENOVIA Synchronicity DesignSync Data Manager– Gantry Group ROI Study ... 4

Table 2 Design Engineering Time Saved – Gantry Group ROI Study ... 11

Table 3 Productivity Improvements – Gantry Group ROI Study ... 12

Table 4 Multi-site Design Increases – Gantry Group ROI Study ... 13

Table 5 IP Re-Use – Gantry Group ROI Study ... 13

Table 6 Improved Product/Manufacturing Schedules – Gantry Group ROI Study ... 14

Table 7 Manufacturing Cost Savings – Gantry Group ROI Study ... 14

Table 8 Quality Improvement – Gantry Group ROI Study ... 15

(3)

Executive Summary

Meeting the challenges in getting semiconductor products to market does not always require upgrading design tools or making expensive technology investments. Many of the leading

semiconductor companies have seen where they have been able to increase productivity through the use of design collaboration and more standardized design management within their flows. Companies surveyed as part of this study have reported results such as a74% increase in multi-site designs, a 46% savings in design engineering time and a32% increase in product quality. The study will show how leading semiconductor companies gain a significant competitive advantage in using collaborative solutions from Dassault Systèmes ENOVIA Corporation.

This paper is targeted at decision makers concerned with increasing design efficiency, collaboration and improving integrated circuit (IC) product margins while reducing costs.

This study was completed by Gantry Group LLC on behalf of ENOVIA in August 2008, and is based on interviews with 18 customers who have deployed ENOVIA Synchronicity DesignSync Data Manager.

(4)

Abstract

While the complexity of chips has risen by a factor of 1,000 in the past two decades, the

productivity of engineers has increased by only a fraction of this amount. Resultant development costs are therefore growing exponentially with product complexity, fragmented design chains, and pressures to meet narrow market windows with reduced or limited resources. Companies without enterprise-wide Design and Release Management best practices in place are experiencing pricey consequences for errors caused by ad hoc revision control configuration management and lax project management. Common experiences include false build frequencies of over 30%, millions spent in annual re-spin costs, and revenue loss from missed market windows. The numbers aren’t pretty: only 45% of semiconductor product launches meet their planned schedule, 63% of semiconductor designs require at least one re-spin, 42% of design projects exceed planned budget, and only 59% of designs make it into production at all.1

Over the past decade, software tools have become available that assist with management and support of electronics design projects, but only a few have kept pace with the degree of complexity and sheer size of the design databases introduced by next generation SoC design. One such

solution, ENOVIA Synchronicity DesignSync Data Manager from Dassault Systemes ENOVIA, is widely used by leading electronics firms for design project collaboration and management.

ENOVIA engaged the Gantry Group to conduct an objective survey of a group of 18 of its long-term customers to identify the key benefits, value drivers, and percent improvements realized after deployment of DesignSync. This study revealed that DesignSync is defining the Design Release Management process standard for many of its customers, and is seen as an invaluable tool for:

• Maintaining competitive advantage

• Enabling increased use of hierarchical design and IP re-use • Controlling costs, reducing risk

• Enabling multi-site/multi-enterprise design (e.g. complexity) • Speeding up development

• Improving customer satisfaction

These attributes translated into real improvements as seen in Table 1.

Business Impact of DesignSync

Average % Improvements

Productivity Improvements 43%

Design Engineering Time Saved 46%

Multi-Site Design 74%

IP Re-use 44%

Product and Manufacturing Schedules 20%

Manufacturing Cost Savings 25%

Design/Product Quality 32%

Table 1 Business Impact of ENOVIA Synchronicity DesignSync Data Manager– Gantry Group ROI Study

1_{EETimes, September 18, 2006}

(5)

Companies that have deployed DesignSync have also demonstrated improved ability to execute on multi-site, global design projects through the following attributes:

• Single, enforceable, enterprise-wide infrastructure for unified best practices data management and collaboration

• Significant reduction in number of design cycles from efficient project management

• Reduction in errors through superior visibility into all project aspects

• Greater customer satisfaction from accurate, documented interactions

• Improved ability to meet pre-scheduled fab runs and market windows

• Ability to re-use legacy Intellectual Property (IP) data through greater database integrity and modular support

Based on customer input, Gantry Group believes that DesignSync can directly assist in controlling costs and serve as a critical enabling technology component for electronics companies seeking to differentiate further from competitors. DesignSync is considered the foundational infrastructure for new design workflow best practices that semiconductor design companies cannot be without and while not specifically quantified, all those surveyed were confident they received a strong positive return on their investment.

The Semiconductor Business Climate

The semiconductor market can be depicted by the following characteristics:

• Highly competitive

• Stagnant sales opportunities (slow economy)

• Economic pressure on pricing and cost reduction

• Increasingly large, complex databases (shrinking geometries, SoC advances)

• Global communication requirements (distributed design, consolidation, outsourcing)

• Increased instances of multi-site design as a result of industry consolidation

• Fragmented design chain (more parties involved, no longer vertically integrated)

• Narrower market window for products (shorter product life-cycles)

The rapidly intensifying business climate shows no signs of letting up. Already competitive, the economic slow-down experienced over the past three years has decreased the pool of potential sales opportunities, heightening the need for sustainable competitive advantage. At the same time end customers press for lower pricing, adding to internal pressures to reduce development costs. Even during tough economic times, the pace of chip technology development has not slowed. Mainstream design is now embracing smaller and smaller geometries and semiconductor

companies are frantically scrambling to get their share of the market. To manage increased design complexity electronics companies are implementing distributed design teams to accommodate simultaneous development of IP – with each team focusing on a different IP block.

Other drivers fragmenting the design chain include:

• Increased global expansion to tap into lower labor costs overseas

• Increased use of outsourcing for non-core skills

(6)

Effective collaboration, a vital and fundamental component for multi-site/multi-enterprise design chains, is essential for developing SoC chip technology. Without the tools to minimize

miscommunication between suppliers, partners and customers, and manage last minute

engineering changes, today’s complex chips simply cannot be designed. Even companies with a single design site are challenged to adopt a co-development environment as their customers and outsource partners become increasingly involved. In short, companies need to be well positioned to collaborate across both multiple locations and multiple companies.

The increased need for collaboration makes the ability to manage distributed design efficiently a requirement for remaining competitive. Semiconductor companies without this capability will simply not be able to respond to RFPs requiring multi-site projects, which will lead to lost market share and potentially failure of the business.

The Business Impact of Market Dynamics

The impact of the aforementioned market dynamics on the semiconductor industry is significant and broad ranging, affecting development infrastructure, competitive position, costs, revenues, and customer satisfaction.

Multi-Site/Multi-Enterprise Design – Increasingly fragmented design chains can raise the risk of problems. Design management difficulties increase as SoCs give way to even more complex mixed-signal technology; mixed signal represents nearly 60% of application-specific

semiconductors.2_{Today over 70% of all SoCs produced are of the mixed-signal type.}3_To accommodate the parallel development of IP the design chains building these products have

become multi-layered networks of geographically distributed suppliers. While a good idea in theory, different time zones and lack of design management tools can make this strategy a nightmare. Delays and errors that result in the absence of enterprise-wide design workflow processes can lead to longer development cycles and slower time-to-market. In this development environment, the design chain performance may be the primary competitive differentiation. Design chains have become as important (if not more so) than technology innovation since it is the design chain efficiency that governs time to market.

Customer Satisfaction – Maintaining and enhancing customer satisfaction has never been more important and the best way to achieve it is to ensure delivery according to customer expectation. In other words: minimizing budget and time-line surprises. In the current market environment, customers will increasingly design to next generation technology while demanding rapid, on-budget development. Semiconductor companies are challenged to meet these expectations while

transitioning to new technology, efficiently collaborating with multiple design teams across the globe, and reducing development cycles (e.g. controlling costs). In such a demanding, fast-paced, distributed work environment, the opportunity for costly, delay-causing errors is a major challenge to be overcome to gain repeat customer business.

Revenue Opportunities – The impact of the current market environment has its most noticeable effect on the top line. Revenues are affected when business opportunities are lost and when delays create lost revenue. As customers design to more complex technology, only those companies with the demonstrated capability to manage multi-site design and very large databases will be included in the RFP process. Semiconductor companies that cannot mitigate delay-causing errors will sustain significant revenue loss, both from revenue delays and from lost billion-dollar market opportunities.

2_{databeans, Incorporated. Real World Signal Management Drives $50 Billion Mixed-Signal Market,} 2006

(7)

A 12-month delay can result in over 55% in lost opportunities for revenue and revenue reduction of 33%.4

Development Costs – Delay-causing errors are a primary determinant of development costs. The more engineers on a project, the more data files involved, and the more time zones to account for, the greater the risk for engineers to be unknowingly working on builds based on bad data.

Sometimes the build-time is less than the time it takes to track down and then resolve the error. As companies deal with more complex databases delays to diagnose and locate errors and re-work the build, will be longer. These delays in development can be about a few days to a few weeks, and can spiral into several months if they result in a lost run-window at the fab. In short, the longer the delay, the greater the resource costs. To mitigate the risk of re-work (e.g. high development costs) companies are seeking to reduce or eliminate the “avoidable” costs such as number of chip spins, shortening coding review cycle, etc.

Competitive Advantage – Already a challenge, competitive advantage is more difficult to sustain in the current business climate. Competitive position is defined largely by a company’s ability to bid and execute on complex projects, conduct efficient design collaboration, manage last minute

design changes, and keep control of development costs. The current market conditions exert pressure on each one of these capabilities. When companies transitioned from 0.18 micron to 0.13 micron processes, the incidences of delay increased by at least one-third.5_{Chip designs in the 0.18} micron process typically can have an 80% success rate at meeting schedule; only 50% of chips in the 0.13 micron process come in within required design schedules. Of those 0.13 micron chips that fall behind, about half can be more than 50% behind schedule.6_{These problems are magnified as} the industry moves to 45 and 32 nanometer technologies. Companies that cannot beat these design rollout numbers (not an easy challenge to overcome) will lose considerable competitive advantage to those who can.

Note: An inventory of semiconductor design process challenges that are the direct result of the current market and technology dynamics is listed in the Appendix of this white paper.

ENOVIA Synchronicity DesignSync

Data Manager:

Design & Release Management Solution

Circuit densities have now increased 10 times over what they were three years ago and the designs themselves have grown into more complex architectures including nanometer-scale systems-on-a-chip.7_{As design components become smaller and chips denser, the risk of errors is higher because}

the consequences of re-work is costlier than ever now. The later a design flaw is discovered, the more expensive the fix. Stratospheric development costs for a new chip can rise to tens of millions. Today, a design flaw undetected until tape-out could mean scrapping a 90-nanometer mask set worth more than $1 million.8_{At 65-nanometers mask set costs could rise to $2 million.}9_As

consolidation and outsourcing have fueled multi-site design locations, the probability of errors and flaws is ever greater.

What is needed is an enterprise and extraprise-wide solution that enforces best practices from the project definition stage, all the way to delivery. By offering a structured way to communicate and transfer data and information, the design chain is “connected,” the productivity of limited resources

4_{International Business Strategies research, 2002} 5_{International Business Strategies research, 2002} 6_{International Business Strategies research, 2002} 7_{EE Times Nanometer Devices Rev Race, 2005}

8_{Kalypso White Paper, Semiconductor PLN, November 2006} 9_{Electronic Business Network, 2004}

(8)

is optimized, and many of the “technical problems” that are caused by lack of formal Release Management processes are eliminated or reduced. With formal management of the work processes involved in all aspects of design collaboration and management, companies can compress their time-to-release, gain competitive advantage, and reduce design development costs. In addition, design environments that offer integration of analog, mixed signal, digital, tools and software extends design, integration and release management benefits to all teams. A modular approach to IP enables development of IP block libraries available for multi-site and multi-enterprise use, ensuring consistency, reducing errors (inherent in designing “from scratch”), and boosting IP Return on Investment (ROI).

Design and Release Management processes are comprised by a set of best practices for the capture, tracking, and management of all events around design data, integrated into a project management tool set that provides instant visibility into the entire project (or hierarchies of projects), abstracting data into hierarchical modules that can be re-used and released across multiple projects. DesignSync solutions for design collaboration and management represent an infrastructure for implementing Design and Release Management best practices. All aspects of the design process and associated data are managed within a single, centralized database, eliminating the use of multiple ad hoc data management tools and numerous private copies of data files. The DesignSync design and release management solution has successfully addressed key

semiconductor design challenges in over 120 customer sites, worldwide.

Customer Perceptions of ENOVIA Synchronicity

DesignSync Data Manager Value

Customers of DesignSync found the rich offering of design collaboration and management capabilities resulted in a set of strong value drivers that can impact both revenue and development costs.

Revenue Enhancement

• While DesignSync itself does not directly assist sales representatives to close sales, it does provide companies with the confidence and execution ability to bid on large, highly complex, multi-site projects. This would not be possible without the management and control afforded by DesignSync as it is one of the only solutions available designed specifically to handle the

challenges of design networks – a requirement for complex project development. Without DesignSync many companies stated that multi-site projects could simply not be done.

“Collaboration across multi-site – is much easier with DesignSync. Another benefit is that it facilitates managing data changes and provides good historical documentation for regulatory compliance (documentation of processes and code). “

- Principal Design Automation Engineer

• DesignSync also helps enhance revenue by helping companies to avoid revenue losses associated with the project delays that result in being late to market. With fewer design cycles and smoother interactions that come from disciplined Release Management work processes, DesignSync can improve time-to-release. While other factors weigh in on whether a product is late to market, DesignSync certainly contributes to improvements.

“There are penalties for being late plus we could miss the time window to meet the market which could cost many millions. Other types of costs might be related to having delayed other products in the pipeline and missing their windows too – chain effect and costs are too high to estimate.”

(9)

• Customer satisfaction, a key criterion in gaining repeat business, is impacted by DesignSync in several ways. By providing predictability and accountability within the design process by making the entire project state (and history) visible, DesignSync enables companies to better support customers and more accurately deliver on expectations. In addition, just as ISO 9000 certification supplies buyers with an indication of a vendor’s quality procedures, the knowledge that a design firm is formally implementing Release Management with DesignSync provides the same type of reassurance. Finally, since DesignSync connects the customer into the design chain, the workflow processes it supports act to tie customers closer, making vendor switching less desirable.

“Managing data and data sharing are both major areas of value for us because of

DesignSync. Being able to concurrently work on the same set of files globally was critical for us since we have about 15 design centers and would not be able to do this without DesignSync. “

- Manager, Engineering Operations & CAD

• Properly and consistently implemented, workflow processes can yield tremendous competitive advantage. DesignSync impacts competitive advantage by helping companies in their efforts to be first to market by reducing the number of design cycles in development and avoiding lengthy delays. Further, as products mature the productivity gains and avoided costs supported by Release Management work processes enable companies to price competitively to sustain market share.

“With multi-site capability we can hire skilled resources where they live and take advantage of this. It allows us to avoid a skill crunch in a specific geography and lets us leverage our resources better and enables us to successfully execute more complex projects.”

- Senior Staff Development Engineer

Cost Reduction

• DesignSync customers unanimously report a reduction or even elimination of configuration errors brought about by the use of multiple versions of data files in the absence of DesignSync. With a reduction of these types of errors time is saved not only by avoided re-work but also by recovering resources spent previously on tracking down and fixing bugs. As a result of

DesignSync, customers have noted a definite reduction in the number of design cycles required on projects which in turn reduces the time-to-release.

“ DesignSync offers us revision control, design consistency, and better control on what team members are doing when running at remote sites - all of which combines to help avoid design errors that result in re-work and longer design cycles.”

(10)

• Reducing the risk of catastrophic errors can result in significant cost avoidance. In some cases configuration error costs can balloon into the millions when the error makes it all the way to the mask set. However, even at costs of $300,000 - $1 million per mask set, the cost of the re-spin is not as expensive as the cost of lost engineering productivity. One wrong file can take up to a month to track down and another 1-2 months to get to market. Simply by reducing the

incidence of configuration errors, DesignSync can help companies avoid millions annually in unproductive labor hours and re-spin costs.

“I think overall the quality increase is the biggest benefit we get from DesignSync, which ultimately drives to the bottom line as cost savings.”

- Senior Staff Engineer

• Another area of economic benefit concerns the cost savings from greater productivity – doing more without adding additional staff. One Synchronicity customer that measures productivity of the design team found that the number of gates produced per engineer increased after

deployment of DesignSync. Even without this metric, the fact that companies can take on a greater number of projects or simply more complex projects without adding engineers, speaks to their enhanced productivity due to the implementation of proper best practices (e.g. less engineer time spent tracking down and resolving problems).

“Hierarchical Configuration Management is where we have the biggest benefit from DesignSync. This solution has enabled us to deploy HCM and this has really increased our efficiency – now we can do more with fewer people.”

- Principal Design Engineer

• Development costs can be reduced further when engineers are able to re-use legacy IP across projects. With the management control and workflow procedures enforced consistently by DesignSync, project teams are confident of the integrity of data libraries, making it possible to re-use IP blocks instead of starting development from scratch. The database integrity benefit of DesignSynccan build on itself over time, shortening design cycles through error reduction and IP re-use.

Measured Improvements of Design Workflow with

ENOVIA Synchronicity DesignSync Data Manager

DesignSync provides the infrastructure that has enabled semiconductor companies to modify workflow processes that generate real results. Interviews with Project Managers and Design Directors at leading semiconductor companies revealed that DesignSync is helping them meet productivity and cost objectives in very specific ways:

(11)

Design Flow Efficiency: Engineering Time Saved

All study participants had embedded DesignSync into design flows via scripting, process or automation. Embedding was widely seen as the most effective means to enforce the use of

DesignSync from initial design and layout. As a result, study companies were able to enforce data management and version control as part of an integrated process that provided a consistent environment to each engineer without requiring the engineers to learn anything new. Participants in the study estimated the following percent improvements design engineering time saved as a result of DesignSync:

Note: Averages represent participants who estimated improvement since deployment of ENOVIA Synchronicity DesignSync Data Manager.

Table 2 Design Engineering Time Saved – Gantry Group ROI Study

Getting Back to Tape-Out Configuration

In the 6-10 week period while designs are at the fab, engineers continue working on the product. DesignSyncallows engineers to issue the commands instantly to get them back to the tape-out configuration of the data files when the silicon comes back from the fab, enabling them to pick-up were they left off in the design. Without the enterprise-wide framework for structured data

management it could take days for engineers to get back to where they left off prior to the fab run. Time wasted in trying to get back to a particular state in the data files is reduced to a few hours. The average reduction to get back to tape-out configuration estimated by study participants as a result of DesignSync deployment was 41%.

Data Set Compares

As the number of iterations increases into the hundreds of thousands for a given project, engineers will be challenged to keep track of “what’s changed” in a data library. In an environment where each engineer keeps their own copies of the data files they work on, it can take considerable time to compare all the files in a library set. DesignSync dramatically compresses the amount of time required to compare data sets, providing a “delta file” that immediately indicates what changes

Design Engineering Time Saved

Average %

Improvement

% Decrease in time looking for correct data --- Finding actual tapeout data, rework data, verified data, etc.

41% % Decrease in time recreating mishandled data --- Redesign or

roll-back time because of lost or damaged data

61% % Decrease in time lost simulating wrong data --- Simulating

incorrect or changed data and libraries

49% % Decrease in time lost laying out wrong data --- Laying out with

incorrect or changed components

59% % Decrease in time lost verifying wrong data --- Verifying incorrect

or changed layouts

53% % Decrease in time spent coordinating with remote sites 43% % Reduction in time to assemble IP at tape-out 11%

(12)

were made, when, why and by whom. The number of steps to complete a data set file compare is cut down to one. The average reduction in time to complete a data set compare estimated by study participants as a result of DesignSync deployment was 55%.

Design Engineer Productivity

There is no question that DesignSync introduces additional steps into the design development process. However even though more time is spent on project management and more people get involved with it, the resulting projects go forward with fewer delays. At all times, all team members know they are working with good data. Participants in the study estimated the following percent improvements design engineer productivity a result of DesignSync:

Productivity Improvements

Average %

Improvement

% Increase in overall engineer productivity 27% % Increase in overall recovered engineering

resources due to D/S implementation 20% % Impact on design team size 38% % Increase in number of gates

produced/engineer 45%

% Increase in number of products designed per

year (team throughput) 43%

% Increase in number of design

configurations/variants worked on at one time 80% % Reduction in manpower required to manage

design integration of various versions of design

blocks and libraries 46%

Note: Averages represent participants who estimated improvement since deployment of DesignSync.

Table 3 Productivity Improvements – Gantry Group ROI Study

Less Disk Space

Simply put, the lack of a single, centralized database consumes huge amounts of disk space. Considering that new technologies have databases in the terabytes, the consequences of supporting multiple copies of data files for each engineer will be large enough to affect infrastructure performance. The added costs to purchase and maintain disk space are not

inconsequential and can be deferred longer with DesignSync. What may be more damaging is that the excessive data explosion that results from multiple copies of design information in various states frequently leads to confusion. In turn, that confusion is a common source of bad data hand-offs between teams and blown releases. The high costs associated with this lack of design data management discipline are avoidable and recoverable.

Collaboration Across Multi-Sites/Locations

When multiple parties in geographically disparate locations are all involved with a design project, it is critically important to be able to formally document all communication, requests and deliveries. DesignSync can be used to “connect up” the entire design chain – including remote design teams,

(13)

suppliers, partners, and customers. By providing a common unified management framework throughout the design chain, DesignSync makes interactions smoother. Customer expectations are documented for all to see and hand-offs between parties are more accurate. Because of the

recognized benefits of multi-site design and because it is also an outcome of consolidation, study participants estimate that the instance of multi-site or multi-enterprise designs over the next 3 years will increase by an average of 95%. All study participants agreed that the biggest benefit of multi-site design is the better use and availability of resources – something these companies rely on DesignSync to support. Participants in the study estimated the following percent improvements in multi-site designs as a result of DesignSync:

Multi-Site Design Increases

Average %

Improvement

% Increase in the number of multi-site

designs (e.g. complexity) 85%

% Increase in the number of multi-site/multi-enterprise designs anticipated

over next few years 63%

Table 4 Multi-site Design Increases – Gantry Group ROI Study

IP Re-Use

Study participants using IP blocks unanimously agreed that an IP block needs only to be re-used one or more times to achieve payback. Increasingly with tools like DesignSync that support modular design, companies are leveraging the re-use of already verified code blocks. With centralized libraries, IP modules offer plug and play capability in a user environment that is

consistent across all users. The cost benefits of IP re-use are evident – lack of organizations taking steps to build and maintain IP libraries is seen as the biggest barrier, since the technology offered by DesignSync to support modular design is available. Participants in the study estimated the following percent improvements in IP re-use as a result of DesignSync:

IP Re-use

Average %

Improvement

% Increase in design IP re-use capabilities (e.g. Increase in size of IP library of

internally developed and commercially

acquired IP) 31%

% Increase in number of designs re-using

design blocks and packaged IP 45% % Increase in library of reusable IP blocks 38% % Increase in projects using hierarchical

design 63%

(14)

Product & Manufacturing Schedules

Participants in the study estimated the following percent improvements in product and manufacturing schedules as a result of DesignSync:

Product and Manufacturing

Schedules

Average %

Improvement

% Reduction in frequency of false builds or configuration errors that reach

manufacturing 17%

% Reduction in time to resolve issues (bug tracking, finding last good state,

etc.) 18%

% Reduction in number of times Fab

window is missed 17%

% Products that meet original

go-to-market schedule 32%

% Reduction in time to release (reduced

development times) 20%

% Reduction in overall product design

schedule, from front to back. 18% % Decrease in cancelled projects (due to

delays or cost overruns) 18%

Note: Averages represent participants who estimated improvement since deployment of DesignSync.

Table 6 Improved Product/Manufacturing Schedules – Gantry Group ROI Study

Manufacturing Cost Savings

Participants in the study estimated the following percent improvements in manufacturing costs as a result of DesignSync:

Manufacturing Cost Savings

Average % Improvement

% Decrease in number of mask

layer respins 24%

% Decrease in product overall cost 14% What % of manufactured products

have required additional mask

layer respins? 29%

By what % has this decreased since D/S implementation due to getting the right data sets for

full-set manufacturing? 35%

(15)

Product Quality

When all elements of design projects are executed more accurately, getting things right the first time happens more frequently. When errors do occur, DesignSync compresses the time required to track down and correct them. The DesignSync framework uses a single database to capture all aspects of a design project in one place, which is integrated tightly into ProjectSync to provide closed-loop issue tracking. Participants in the study estimated the following percent improvement in quality as a result of DesignSync:

Design/Product Quality

Average %

Improvement

% Increase in overall Design Release quality due to early bug

tracking 33%

% Decrease in pre-release design

bugs 31%

% Decrease in post-release issues 34% % Increase in frequency of “right

first time” (whether in design or

final deliverable to customer) 29%

Table 8 QualityImprovement – Gantry Group ROI Study

Conclusions

After aggregation and analysis of value driver interviews with semiconductor companies who have DesignSync deployments, Gantry Group concludes that the value gained with DesignSync not only justifies the initial cost and support fees, it will in fact serve as a critical enabling technology component in the increasingly complex electronic products market. Overcoming enterprise adoption resistance will be required to achieve a seamless collaboration network throughout the enterprise. However once this is accomplished, customer consensus was that savings in avoided costs, improved competitive advantage and enhanced customer satisfaction combine to deliver an extremely attractive net return on investment.

Based on customer experiences, a key take-away is that payback on the DesignSync investment can be achieved with reduction in just a few of the common release mistakes and avoidance of one or two respins. Over time, the ROI continues to grow well beyond payback as other efficiencies build and incremental improvements become accretive over time.

DesignSync provides a comprehensive, enterprise-wide and business-to-business solution to the problems of managing design collaboration among distributed design chain members engaged in the development of complex electronic products. With this highly scalable solution, semiconductor design teams can implement a set of Release Management best practices workflow procedures that enable them to manage the challenges of today’s intense business climate, remaining competitive even with reduced resources.

(16)

The table below summarizes the major benefits realized by ENOVIA Synchronicity DesignSync Data Manager customers:

ENOVIA Synchronicity DesignSync Data Manager Benefits

Value Contribution

Reduced configuration errors Fewer design cycles per project Ability to manage multi-site, complex projects Superior competitive advantage Reduction in re-spin frequency Avoided costs

Ability to hit Fab windows Faster time to market Real-time visibility into design projects Greater product quality Legacy IP Sharing Reduced development times Implementation of Release Management Best

Practices

Greater customer satisfaction Single, unified database Faster assembly of IP at tape-out

Table 9 Benefits of ENOVIA Synchronicity DesignSync Data Manager – Gantry Group ROI Study

About The Gantry Group, LLC

The Gantry Group is a technology impact analysis company that applies primary market research to help companies cost-effectively accelerate the successful market adoption of their products and services. Gantry Group has helped over 175 companies drive sales, introduce new product

concepts, acquire new customers, increase brand equity, and increase customer lifetime value through our market analysis, market validation, and ROI/TCO benchmarking service suites. Gantry Group has equipped many product and service firms with credible TCO and ROI models that

communicate value in the terms of the business metrics that customers and prospects use to assess the performance of their own companies.

Gantry Group’s ROI & Customer Payback Practice provides companies with tools to accurately calculate the economic benefit of their offering to customers. This practice relies on customized market research and quantitative financial modeling to develop a credible payback calculator that is based on metrics that are meaningful to a vendor’s target market. Cause and effect analysis

enables us to determine the tangible value associated with often intangible benefits. Our rigorous methodology results in customized tools for economic payback projections: customer’s return on investment (ROI), total cost of ownership (TCO), Net Present Value (NPV), and internal rate of return (IRR). The result is a quantified value proposition that is crisply differentiated within a receptive market.

Gantry Group works with management teams in technology, financial/professional services, health care and life science sectors to Sell with ROI. The company can be reached at 978-371-7557 or www.gantrygroup.com.

(17)

About ENOVIA

ENOVIA is a recognized leader in delivering collaborative product lifecycle management (PLM) solutions. We enable companies from a broad range of industries to accelerate innovation

dramatically, time-to-market, and revenue generation by collaboratively developing, building, and managing products. Our solutions facilitate the sharing of concepts, content, and context across product lifecycles and throughout value chains of employees, customers, suppliers, and partners — all to achieve a compelling competitive advantage.

Our interoperable solutions unify and streamline processes across the product lifecycle, enabling companies to work on projects cost-effectively and easily within and outside of their enterprises. Our adaptable, scalable technology accommodates the ever-changing marketplace.

About Dassault Systèmes

As world leader in 3D and PLM solutions, the Dassault Systèmes group brings value to more than 90,000 customers in 80 countries. A pioneer in the 3D software market since 1981, Dassault Systèmes develops and markets PLM application software and services that support industrial processes and provide a 3D vision of the entire life cycle of products from conception to

maintenance. Our offering includes integrated PLM solutions for product development (CATIA®, DELMIA®, ENOVIA®, SMARTEAM®), mainstream product 3D design tools (SolidWorks®), 3D components (Spatial/ACIS®) and SIMULIA®, DS’ open scientific platform for realistic simulation. Dassault Systèmes is listed on the Euronext Paris (#13065, DSY.PA) stock exchanges. For more information, visit 3ds.com.

Appendices

Semiconductor Design Process Challenges

Companies interviewed in this study shared past experiences about their processes prior to the deployment of DesignSync. Typically, these companies used some form of freeware, in-house scripts, or an ad hoc combination of the two. Each engineer had his or her own method for tracking and managing data files. While each company believed it was “doing data and project

management,” without common structure and formalized workflow process to ensure the integrity of the data files and monitor the true status of the project, they faced numerous challenges. Well-managed team communication and structured data sharing are critical to project success.

Multi-site Process Splits

Site A finds a problem in a data library cut by Site B and rolls back to a previous version; Site B proceeds to chase down and fix the bug. The resulting process split can take days to unravel without visibility in the project history showing what changes were made, why and when they were made, and by whom.

False Builds and Error Induced Re-spin

Lack of assimilation of data files into single unified database can result in 30% - 40% of builds being “false.” Sometimes builds with bad data make it all the way to the mask set before they are found. When this happens, the cost of respin results in the “million-dollar mistake” depending upon the complexity of the chip.

(18)

The Tower of Babble

Companies involved with multi-site design who do not have collaboration workflow processes in place can end up with the classic supplier/customer breakdown. Without a formal way to document and communicate customer needs in a common language across the design chain, customers can end up with a deliverable that doesn’t match requirements. Unpleasant surprises create volatile customer-supplier interactions, which, coupled with discomfort around quality issues can depress a customer’s desire for repeat business.

Multi-Site Over-Writes and Update Latency

Because of time-zone differences, design sites may not have the same update version of a database. This can be compounded if the design engineer in an earlier time zone over-writes the real updated version of a library with the older one they have been working on. Until a problem shows up in test or simulation, work proceeds resulting in a false build. All design and verification activities performed on stale data must be re-run.

Delay Inflation

After a false build occurs, it takes time to unravel and track down exactly which file(s) contained the bug or get back to the last good state of the data files before the bug was introduced. These error situations can easily result in project delays of a week or two for each incidence. The delay is lengthened if the pre-scheduled fab window is missed. These runs are tightly scheduled and if a run window is missed, it can be weeks before a new run can be scheduled. Often a few days of delay to deal with errors can expand dramatically into setbacks of a few months.

Revenue Loss

As technology innovation accelerates electronic product life cycles are shortening. It is not atypical for a design team to be developing for a product with a 12 month commercial life-time. A three month delay results in 25% of the revenue being permanently lost assuming that the revenue is constant over the life of the product.10_{For some companies the consequences have been far worse.}

About This Study

ENOVIA Corporation engaged the Gantry Group to conduct an objective customer study that would examine the key ROI value drivers and areas of cost savings realized through the adoption and deployment of DesignSync. Specifically, Gantry Group explored the changes that occur within a design chain workflow as a result of deployment of DesignSync. This white paper captures and explores the experiences and quantitative improvement realized by 18 ENOVIA customers, achieved through the implementation and adoption of DesignSync.

Using a guided session interview approach, Gantry Group spoke with project management staff to develop a deep understanding of the DesignSync impact and to gain insight into their objectives and expectations of DesignSync compared with their actual experience with it.

The study was designed to probe the following issues for semiconductor design companies: • The value drivers delivered by DesignSync

• Percent improvements in key process areas due to DesignSync • Key challenges facing chip design companies or IP suppliers

• Major workflow/process changes noted since DesignSync deployment • Justification of DesignSync purchase

• The strategic importance of design collaboration and design management processes • The critical success factors for design management/design collaboration solution

(19)

Gantry Group would like to thank the following DesignSync customers for their participation: Agere Systems, Broadcom, Conexant, Dialog Semiconductor Inc., Freescale, Intel Inc., LSI Logic,

Medtronic, Micron Technology, PMC Sierra, Qualcomm Inc., Saifun, Seagate, STMicroelectronics, Tower Semiconductor, Texas Instruments (US and France),

About ENOVIA Synchronicity DesignSync Data Manager

Designing an Integrated Circuit (IC) today requires integrating many, various datasets that are generated by multiple, and often geographically dispersed, design teams. As IC products become more complex, design teams are required to consider ways that maximize their productivity. Designing with reuse in mind and being able to leverage Intellectual Property (IP) from both internal and external sources is a necessity. The results are IC products that have increased flexibility and extended lifespans.

Another trend in the design of complex IC is that the contributions of multiple functional teams are included in each product. Many of today’s leading-edge design includes both analog and digital content, a significant amount of software and even consideration for the physical effects of the manufacturing process and packaged environment. A key factor in meeting shrinking design schedules is the ability to manage both the release and integration from all of these functional design teams.

The Leader for Collaborative IC Design Data Management

Since 1998, IC design teams have relied on the leading solution for collaborative IC design data management, ENOVIA DesignSync, to help manage the hardwareand software data in their

products. With integrations into the leading EDA design environments, the ability to manage digital and software design projects and the capability to integrate design IP across multiple sites, ENOVIA Synchronicity DesignSync Data Manager is the proven solution that industry leaders rely upon for their key semiconductor products. Along with the IP and PLM solutions from ENOVIA, ENOVIA Synchronicity DesignSync Data Manager has the power and scalability that you need today and tomorrow. Today, over 120 development organizations, including 13 of the top 15 semiconductor companies,have chosen ENOVIA Synchronicity DesignSyncData Managerto boost design

productivity.

For more information, go to: www.3ds.com/products/ENOVIA/industries/high-tech/semiconductor/

Trademark Information

ENOVIA Synchronicity DesignSync Data Manager, and the Synchronicity Logo are registered trademarks and ENOVIA Synchronicity DesignSync Data Manager is a trademark of Dassault Systemes.

e, and Suite 301 Copyright Reproduction

Augus

The G

150 B

Suite 3

Conco

www.g

st 2008

Gantry Gr

aker Ave

301

ord, MA 0

gantrygro

Sy

Wh

Des

Sol

IP R

Com

roup, LLC

enue

01742

oup.com

RO

ynch

itepap

sign C

ution

Reuse

mplex

C

m

I Im

of

roni

Dat

per:

Collab

s Con

e, and

xity

mpac

f EN

icity

ta M

borati

ntrol C

d Man

ct An

OVI

y De

Mana

ion &

Costs

nage I

naly

IA

sign

ager

Mana

s, Enc

ncrea

ysis

nSyn

r

agem

coura

ased

nc

®

ent

age

Contents

List of Tables

Executive Summary

Abstract

Business Impact of DesignSync

Average % Improvements

The Semiconductor Business Climate

The Business Impact of Market Dynamics