Analyzing Methods Study of Outer Loop Current Sharing Control for Paralleled DC/DC Converters

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Analyzing Methods Study of Outer Loop Current Sharing Control

for Paralleled DC/DC Converters

Yang Qiu, Ming Xu, Jinjun Liu, and Fred C. Lee

Center for Power Electronics Systems

The Bradley Department of Electrical Engineering Virginia Polytechnic Institute and State University

Blacksburg, VA 24061 USA

Abstract— Outer loop current sharing control method is most widely used for paralleled DC/DC converters. There are mainly two methods to analyze its stability and transient performance. The first method uses transfer function models, while the other

uses output impedance models. The advantages and

disadvantages of these two methods are investigated and discussed in this paper.*

I. INTRODUCTION

Compared with centralized power system, the distributed power system (DPS) provides several advantages such as redundancy, reliability, design standardization and ease of maintenance. However, due to thermal and device stress requirements, uniform current sharing among paralleled modules is a primary concern. Several methods have been proposed and practiced by the industry. A complementary classification of the existing current sharing methods for DC/DC converters has been documented [1][2]. The passive droop method is simple, but it is hard to achieve high current sharing accuracy and high voltage regulation accuracy at the same time [3]. The active current sharing control, with a current sharing bus as the current reference signal, is widely implemented.

According to the control structure, i.e., the relationship of current sharing control loop with voltage regulation loop, the active method is further classified into outer loop regulation (OLR), inner loop regulation (ILR) and dual loop regulation (DLR). Among them, OLR method is the most popular industry solution.

According to how the current sharing bus is organized among modules, three bus program methods have ever been proposed, i.e., automatic master (AM), with the highest current signal takes the current sharing bus [4]; average program (AP), with the average load current signal as current sharing bus [5]; and dedicated master (DM), only the current information from one prescribed module is directly connected to the current sharing bus.

The fundamental issue of the current sharing control is its relationship with voltage regulation control. However, the control structure for paralleled modules with current sharing is much more complicated than that of a single module. At the same time, more requirements have been proposed, such

*_{This work was supported primarily by the ERC Program of the National} Science Foundation under Award Number EEC-9731677.

as higher accuracy and better transient response. The current sharing schemes need further analysis and understanding to aid the control design. Addressing OLR current sharing, there are mainly two analyzing methods, one utilizes transfer function models [6], and the other utilizes output impedance models [7][8]. In this paper, these two methods are investigated and explored. Advantages and disadvantages are discussed.

II. Outer Loop Current Sharing Control

Fig.1 shows the configuration of outer loop current sharing with AM bus. Texas Instrument/Unitrode provides commercial chips for this control method [4].

Based on regular stand-alone modules, OLR current sharing is easy to realize. The stand-alone modules already has a very fast current feedback loop as an inner loop to improve the system dynamic performance and stability, and a quite fast voltage loop as the outer loop to regulate the output voltage. If these stand-alone modules are parallel connected using OLR current sharing structure, nothing has to be changed inside each module, including the current feedback loop and voltage loop design. The only thing need to do is adding a slow current sharing control loop to each module outside the voltage loop to adjust the voltage reference.

With the AM structure, the converter carrying the largest current is the master module and its current serves as the current sharing bus and then the common current reference for the other modules. The voltage loop reference of the slave module is adjusted through the current sharing compensator

HCS according to the difference between its own output current and the common current reference. As a result, the output current of the slave module will follow that of the master module.

Introduction of the current sharing control makes the whole system complicated. More control loops exist, and interactions of the paralleled modules must be taken into consideration. The function and bandwidth of the control loops are usually designed to be clearly distinguished from each other to make sure there is no conflict. The current sharing control is relatively slow because its bandwidth is limited by the voltage loop. Therefore the output currents of the parallel modules are not quite evenly distributed during the load transient, and in practical applications, some

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unnecessary minor alarms occur as the load rapidly changes or one module fails and shuts down.

To get further improvement of the OLR current sharing control, a fundamental understanding of the relationship of the control loops is needed. More analysis addressing this most popular control scheme is necessary.

Fig.1 Outer loop current sharing control structure

III. TRANSFERFUNCTIONMODEL

One method to analyze the paralleled converters with current sharing is the small signal transfer function model [6]. Fig. 2 shows the transfer function blocks of a two converter paralleled system with OLR+AM current sharing control, with module #1 as master, and module #2 as slave. In this case, inductor currents are used instead of output currents as the variables to be controlled in the current sharing scheme.

The transfer functions of duty cycle to output voltage (Gvdx,

x=1,2) and to inductor current (Gidxx, x=1,2) should be calculated first. Because there exist interactions of one module to another, Gvdxand Gidxxare different from those of an individual module. For example, Gidxx becomes a three-pole two-zero function instead of the two-three-pole one-zero function in an individual module. Transfer functions of one module’s duty cycle to another module’s inductor current (Gidxy, x, y=1,2, x≠y) should be considered in this structure,

too.

There are new loops introduced with the current sharing control. The current sharing loop gain, which physically determines the current sharing transients, is defined as,

22 id m v cs i cs

K

H

F

G

T

=

(1)

To design HCSto achieve a stable and fast loop, bode plot of TCSexcluding HCSis shown in Fig. 3. Based on this figure, a current sharing compensator in the form of Kc/(s/ωp+1) is proposed by [6]. ωp is placed to get sufficient switching

ripple attenuation. Kc should be chosen large enough to get small current sharing error, because Hv’s zero frequency pole cannot guarantee zero current sharing error.

The cross-coupling loop gain, which determines how the master module’s current is influenced by the current sharing scheme, is defined as,

12 id m v cs i cc

K

H

F

G

T

=

(2)

Bode plot of TCSand TCCof a buck converter system design example are shown in Fig. 4. Because there is no negative sign in TCCloop, its phase margin should be compared with – 360o, but not –180o.

The voltage control loop gain is changed by the current sharing control. With opening the master’s voltage control feedback, the slave converter’s voltage loop gain is,

cc cs v slave v

T

−

+

=

1

_ (3)

Where, Tv is the individual module’s voltage loop gain without current sharing control.

vd m v v v

K

H

F

G

T

=

(4)

The master module’s voltage loop gain is also modified.

cc cs cc cs v v master v

T

−

+

−

⋅

+

=

1

)

(

_ (5)

Total system loop gain is the sum of Tv_masterand Tv_slave.

slave v master v total v

T

_{_}

=

_{_}

+

_{_} (6)

It can be told that if the two modules are exactly identical,

v total

v

T

_

=

2

(7)

This is because with identical modules, there will be no current difference. The current sharing control will have no influence on the system.

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Fig. 3 Bode plot of TCSexcluding HCS

Tv_master, Tv_slave and the individual module voltage loop gain Tv_iare shown in Fig. 5. Tv_slaveis changed dramatically from an individual module. The reason is that current sharing control makes the slave module become a current source. In low frequency region, Tv_slaveis much less than Tv_master. This means the master module take the role of output regulation. To avoid the output voltage regulation fighting between the slave module and master module, Tv_slave should be smaller than Tv_master, thus avoiding the unwanted chattering problem, i.e., the master/slave role change during transient [6].

To make the current sharing control stable, the current sharing loop and the cross-coupling current sharing loop should be stable. The voltage regulation loops should be stable at the same time.

Fig. 4 Bode plot of TCSand TCC

Fig. 5 Bode plot of the voltage loop gains

IV. OUTPUTIMPEDANCEMODEL

An alternative method to analyze the small signal stability and transient performance of outer loop current sharing is the systematic approach. The basic idea of this method is shown in Fig. 6 [2]. It utilizes the interface stable concept. To make the whole system stable, each module should be stable, i.e., each module’s output impedance or output admittance should be stable. At the same time, the system interconnection is stable, i.e., the system minor loop gain as (8) should be stable. load o load o m

Z

Y

Z

T

=

/

=

1

/

(8)

Where, Zois the output impedance of the paralleled module system, Yois the output admittance of the system.

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The small signal models to calculate the master and slave module’s output impedance are shown in Fig. 7 and Fig. 8 separately. In these figures, Zol_x(x=1, 2) is the open loop output impedance. Because the interface concept is utilized and what to be considered is the unterminated output impedance, there is no interaction for the power stages. Therefore, the master module’s output impedance is not influenced by the current sharing control.

V ol_ o_master cs o_master

T

Z

+

=

1

1 (9) While the slave’s impedance is changed to:

CS master o slave o CS slave o cs slave o

T

Z

T

Z

⋅

+

=

_ _ _ _

1

)

1

(

(10)

The current sharing loop gain

2 _

1

ol vd v cs i CS

Z

G

H

K

T

=

⋅

(11)

Zo_masterand Zo_slave are the close loop impedances of the individual master and slave modules. It is easier to consider the slave module’s stability with the output admittance.

CS master o CS slave o cs slave o

T

Y

T

Y

+

=

1

_ _ _ (12)

The current sharing loop gain TCSis critical to the stability of slave module. The compensator can be designed in the same way as the analyzing method with transfer functions. For the buck converter, the bode plot of TCSexcluding HCSis shown in Fig. 9. Finite or infinite DC gain HCS can be designed to get sufficiently small current sharing difference.

A design with the HCSin the form of Kc/(s/ωp+1) is shown in Fig. 10 and Fig. 11. In a stable system, the current sharing loop gain TCS should have enough phase margin, and the Nyquist plot of Tmshould not encircle (–1, j0) point if there is no RHP poles in Tm.

Therefore, to get a stable paralleled system with OLR+AM current sharing, first, each individual module should be stable; second, HCS should be designed to make TCS stable; and the system minor loop gain should be examined.

It can be also told from Fig. 10 that inside the current sharing bandwidth, slave module’s output impedance is pulled to match the master module’s. This means the higher the current sharing bandwidth, the closer the impedances of the paralleled modules with current sharing, and the better transient performance [7].

The relationship between the load change and output current difference is:

)

1

(

ˆ

2 1 cs slave cs master o o o o

Z

v

i

=

−

=

⋅

−

∆

o CS slave o master o

v

T

)

Z

(

ˆ

1

_ _

⋅

+

−

=

(13)

From (13), it can be shown clearly that the current sharing loop gain is critical to both the stability and transient performance of the system.

Therefore, it is expected to get a high current sharing control loop bandwidth for better transient performance. The current sharing controller design is a trade-off between faster transient and system stability.

Fig. 7 Master module’s small signal model to calculate output impedance

Fig. 8 Slave module’s small signal model to calculate output impedance

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Fig. 10 Current sharing loop gain and its relationship with output impedances

Fig. 11 Nyquist plot of minor loop gain Tm

V. COMPARISON OFTRANSFERFUNCTIONMODEL AND

OUTPUTIMPEDANCEMODEL

The method using transfer functions is the direct way to analyze the current sharing control. It is almost same as analyzing single modules except the module interactions should be considered. Once every transfer function is calculated, the loop gains can be derived.

However, when analyzing more than two modules, the number of feedback loops grows dramatically and this method becomes impractical. Even with only two modules, the transfer functions may be too complicated in some case. For example, if the output current information is used for load sharing, Gidxyand Gidxxwill become five-pole functions. It is then hard to design the current sharing compensator as proposed. At the same time, it is not clearly stated which loop gain is crucial for the system stability and transient performance assessment.

Compared with the analyzing method of transfer functions, the method with output impedance is easy to implement because the interface concept decouples the power stages of the paralleled modules and makes the transfer functions simpler, especially in multi-module case. Once the unterminated impedances are derived, each converter module can be treated as a black box in the system stability and transient analysis.

It should also be noticed that the current sharing loop gain

TCSdefined in these two methods is different from each other. It is easier to derive with the output impedance model because there is no interaction of power stage should be taken into consideration.

With both methods, the current sharing compensator can be designed according to the bode plot of TCSexcluding HCS. However, if zero current sharing error is wanted, an infinite DC gain compensator is necessary, and the compensator design will be complicated to ensure a stable and fast system.

VI. SUMMARY

Two analyzing methods addressing outer loop current sharing control are investigated and evaluated. The method using transfer function models is the direct way, but may be too complicated to use. The interface concept used by output impedance models simplifies the analysis by decoupling the power stage of the converters. Current sharing compensator design is given in both methods. The advantages and disadvantages of these two methods are discussed.

ACKNOWLEDGMENT

This work was supported primarily by the ERC Program of the National Science Foundation under Award Number EEC-9731677.

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