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Nehru Arts and Science College

Department of Information & Computer Technology

Unit Test – 01 Date:

Reg. No: Name:

Subject:DIGITAL FUNDAMENTAL ARCHITECTURE Class: I IT & CT

Max Marks: 55 Duration:

SECTION A ( 25 X 1 =25)

1 What is the difference between binary coding and binary coded decimal?

(a). Binary coding is pure binary. (b)Binary coding has a decimal format. (c)BCD is pure binary. (d)BCD has no decimal format.

2 Base 10 refers to which number system?

(a)decimal (b)binary coded decimal (c)octal (4)hexadecimal

3 The weight of the LSB as a binary number is:_______________ (a)2 (b)1 (c)3 (d)4

5 Convert the binary number 1001.0010 to decimal. (a)12.5 (b)90.125 (c)125 (d)9.125

7 Convert the decimal number 151.75 to binary.

(a)10000111.11 (b)11010011.01 (c)10010111.11 (4)00111100.00

8 The number of bits used to store a BCD digit is:______________ (a)4 (b)2 (c)1 (d)8

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1 0

What is the result when a decimal 5238 is converted to base 16? (a)327.375 (b)12166 (c)1388 (d)1476

1 1

Convert hexadecimal value 16 to decimal. (a)2210 (b)1610 (c)1010 (d)2010

1 2

Convert the following decimal number to 8-bit binary. 187 (a)101110112 (b)110111012 (c)101111012 (4)101111002

1 3

Convert binary 111111110010 to hexadecimal. (a)EE216 (b)FF216 (c)2FE16 (d)FD216

1 4

Convert the following binary number to decimal. 010112 (a)11 (b)35 (c)15 (d)10

1 5

Convert the binary number 1001.00102 to decimal. (a)90.125 (b)9.125 (c)125 (d)12.5

1 6

Which of the following is the most widely used alphanumeric code for computer input and output?

(a)Gray (b)ASCII (c)Parity (d)EBCDIC

1 7

Convert 59.7210 to BCD.

(a)111011 (b)01011001.01110010 (c)1110.11 (4)0101100101110010

1 8

Convert 8B3F16 to binary.

(a)35647 (b)011010 (c)1011001111100011 (4)1000101100111111

1 9

Which is typically the longest: bit, byte, nibble, word? (a)Bit (b)Byte (c)Nibble (d)Word

2 0

Convert decimal 64 to binary.

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2 1

Convert hexadecimal value C1 to binary.

(a)11000001 (b)1000111 (c)111000100 (d)111000001

2 2

Convert the following octal number to decimal. (a)51 (b)82 (c)57 (d)15

2 3

Convert the following binary number to octal. 0101111002 (a)1728 (b)2728 (c)1748 (d)2748

2 4

The BCD number for decimal 347 is ________.

(a)1100 1011 1000 (b)0011 0100 0111 (c)0011 0100 0001 (d)1100 1011 0110

2 5

The binary number for octal 458 is ________. (a)100010 (b)100101 (c)110101 (d)100100

SECTION B (4 X 5=20) 1. Explain universal gates and their uses.

2. Perform the subtraction with the following binary number using 2’s complement. 11010-1101. 3. Explain the function of Half adder with its diagram.

4. Explain NOR gate and NAND gate.

5. Explain about the Excess-3 code and gray codes with an example.

SECTION C (10 X 1=10)

1. Convert the following decimal number to binary, octal and hexadecimal 4398. 2. Explain the binary adder subtractor circuit.

3. Describe in detail about the full adder with diagram. 4. Convert the following

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(iv) (100101.1001)2 = ?2

5. Convert (1234.56)10 to Hexadecimal, Octal, Binary.

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Subject: DIGITAL FUNDAMENTAL ARCHITECTURE Class: I IT & CT

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(a)1111110 (b)1111101 (c)1111000

2. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? (a)4 (b)2 (c)8

3. Convert BCD 0001 0111 to binary. (a)110011 (b)10001 (c)11000

4. How many 1-of-16 decoders are required for decoding a 7-bit binary number? (a)5 (b)4 (c)8

5. Which of the following statements accurately represents the two BEST methods of logic circuit simplification?

(a)Boolean algebra and Karnaugh mapping (b)Actual circuit trial and error evaluation and waveform analysis (c)Boolean algebra and actual circuit trial and error evaluation 6. Which gate is best used as a basic comparator?

(a)OR (b)AND (c)Exclusive-OR

7. Which of the following is an important feature of the sum-of-products form of expressions?

(a)The delay times are greatly reduced over other forms.(b)All logic circuits are reduced to nothing more than simple AND and OR operations. (c)The maximum number of gates that any signal must pass through is reduced by a factor of two. 8. Looping on a K-map always results in the elimination of:

(a)variables that remain unchanged within the loop. (2)variables within the loop that appear only in their uncomplemented form (c)variables within the loop that appear in both complemented and uncomplemented form.

9. Which of the following expressions is in the sum-of-products form? (a)(AB)(CD) (b)AB(CD) (c)AB + CD

10. Which statement below best describes a Karnaugh map?

(a)Karnaugh maps provide a visual approach to simplifying Boolean

expressions. (b)The Karnaugh map eliminates the need for using NAND and NOR gates. (c)Variable complements can be eliminated by using Karnaugh maps. 11. When adding an even parity bit to the code 110010, the result is ________.

(a)001101 (b)1110010 (c)110010

12. How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have?

(a)7 (b)4 (c)3

13. Most demultiplexers facilitate which of the following?

(a)decimal to hexadecimal (b)single input, multiple outputs (c)ac to dc

14. How many inputs are required for a 1-of-10 BCD decoder? (a)10 (b)4 (c)8

15. One application of a digital multiplexer is to facilitate:

(a)data generation (b)parallel-to-serial data conversion(c)parity checking 16. A multiplexed display:

(a)uses one display to present two or more pieces of information (b)accepts data inputs from multiple lines and passes this data to multiple output lines (c)accepts data inputs from several lines and multiplexes this input data to four BCD lines

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(a)hexadecimal (b)binary-to-hexadecimal (c)dual octal outputs

18. A circuit that responds to a specific set of signals to produce a related digital signal output is called a(n):

(a)decoder (b)encoder (c)display driver

19. Which digital system translates coded characters into a more intelligible form? (a)Counter (b)Decoder (c)Display

20. A basic multiplexer principle can be demonstrated through the use of a:______________

(a)linear stepper (b)rotary switch (c)DPDT switch

21. What is the binary equivalent of the decimal number 368_______________ (a)10101010 (b)11110000 (c)101110000

22. The decimal equivalent of hex number 1A53 is________________ (a)6739 (b)6843 (c)5467

23. The Gray code for decimal number 6 is equivalent to________ (a)0101 (b)1100 (c)1010

24. The four possible ways to AND two input signals that are in complemented and uncomplemented from. These outputs are called________________

(a)fundamental products (b)outputs (c)primary outputs 25. A flip flop is a______________

(a)tri stable device (b)bi stable device (c)memory

SECTION B (4X 5 =20)

1. Simplify the Boolean equation

Y=

2. Explain about parallel in and parallel out register. 3. Explain about the RS flip flops.

4. What is meant by Don’t care conditions? Explain. 5. Explain about the multiplexer and demultiplexer.

SECTION C (10 X 1 = 10)

1. Explain in detail about the flip flops.

2. Explain about the 1X 16 demultiplexer with a neat diagram. 3. Implement the full adder circuit with decoder and two OR gates.

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SECTION A (25 X 1 = 25)

1. Device which recognizes this address responds to the commands issued on the (a)Address lines (b)Control lines (c)data lines

2. The data will be placed on

(a)Data lines (b)Address lines (c)Control lines 3. used to indicate a read request for memory

(a)ReadReq (b)dataRdy (c)Ack 4. has direct control over I/O

(a)MEMORY (b)CPU (c)REGISTER 5. DMA means

(a)Direct Memory Access (b)dial memory access (c)direct memory accept

6. _______________procedure is used to identify the highest priority source by software means. (a)Polling (b)handshaking (c)strobe

7. is not clocked in buses

(a)Synchronous bus (b)asynchronous bus (c)none 8. Which buses cannot be long if they are fast?

(a)Synchronous bus (b)asynchronous bus (c)none 9. PC means

(a)process counter (b)program counter (c)process chip 10. Accumulator is an register

(a)32 bit (b)16bit (c)8 bit 11. SP means

(a)stack pointer (b)string pointer (c)none

12. The stack pointer is also a used as memory pointer (a)64 bit (b)32 bit (c)16 bit

13. points to the memory location in R/W memory (a)stack (b)flags (c)PC

14. The result of operations is stored in (a)accumulator (b)PC (c)stack pointer 15. INTA means

(a)Input ack (b)input access (c)interrupt acknowledgement 16. Is a non-mask able interrupt and has the highest priority

(a)Trap (b)ready (c)RST 17. ALE means

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18. The instructions can be classified into functional categories (a)7 (b)5 (c)6

19. The method of asynchronous data transfer employs a single line to time each transfer (a)Strobe control (b)handshaking (c)status control

20. Data transfer between interface and an I/O device is commonly controlled by a set of (a)strobe control (b)handshaking lines (c)pulses

21. The signal is activated by the destination unit after it accepts the data from the bus (a)Data valid (b)data invalid (c)none

22. The can handle many peripherals through DMA (a)handshaking (b)CPU (c)IOP

23. The branch address is assigned to a fixed location in memory is called (a)Vectored interrupt (b)non vectored interrupt (c)none

24. The ________________ field in instruction code format distinguishes the instruction as an I/O type.

(a) Operation code (b) device address field (c)function code (d)accumulator register. 25. A _________ command causes the interfaces to respond by taking n item of data from the

data lines in the I/O bus.

(a) Control command (b) Test command (c) Data- output command (d) Data-input command.

SECTION B (4 X 5 = 20)

1. Elaborate the DMA contrtoller with its diagram.

2. What do you mean by parallel priority interrupt? Explain it.

3. Write a short note on Handshaking.

4. Discuss about the Strobe control.

5. Discuss the main features of CPU-IOP communication.

SECTION C (10 X 1 = 10)

1. Write a short note on I/O interface.

2. What is the difference between isolated I/O and memory mapped I/O?What are the advantages and disadvantages of each.

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5. Explain the Daisy priority interrupt and parallel priority interrupt.

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1A __________ is a cache used by the central processing unit (CPU) of a computer to reduce the average time to access data from the main memory.

(a)CPU cache (b)virtual memory (c)associate memory 2__________ is the main memory

(a)RAM (b)cache memory (c)virtual memory

3______can only read, the data bus can only be in an output mode. (a)ROM (b)RAM (c)CACHE

4______________ has bidirectional data bus that allows the transfer of data either from memory to CPU during a read operation or from CPU to memory during a write operation.

(a)RAM (b)ROM (c)CACHE MEMORY

5The capacity of the RAM memory is ____________ of eight bits (one byte) per word. (a)256 words (b)128 words (c)32 words

6The________ control inputs are for enabling the chip only when it is selected by the processor. (a)BR (b)chip select (CS) (c)BG

7____________ requires a 7-bit address and an 8-bit bidirectional data bus (a)ROM (b)CACHE (c)RAM

8__________can only read, the data bus can only be in an output mode (a)ROM (b)RAM (c)ERAM

9There are_________ address lines in the ROM chip (a)9 (b)7 (c)5

10A _____________ is a pictorial representation of assigned address space for each chip in the system. (a)memory address map (b)cache map (c)address mapping

11The______ are always assigned to the low order bus lines (a)X (b)Y (c)Z

12The selection between RAM and ROM is achieved through ______ (a)bus line 10 (b)bus line 09 (c)bus line 07

13__________devices that provide backup storage (e.g)magnetic disks and tapes (a)associative memory (b)auxillary memory (c)virtual memory

14_________high speed memory used to increase the speed of processing by making programs and data available to the CPU at a rapid rate

(a)cache memory (b)virtual memory (c)auxillary memory

15______function is start the computer software operating when power is turned on (a)boot strap loader (b)loading (c)cycle stealing

16______________loads a portion of operating system from disc to main memory and control is then transferred to operating system

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17_____________ can also be called as Content addressable memory (CAM) (a)Auxillary memory (b)Associative memory (c)cache memory

18_______holds an external argument for content matching (a)argument register (b)flip flop (c)key register

19___________mask for choosing a particular field or key in the argument word (a)argument register (b)buffer register (c)key register

20__________is more expensive than a RAM because each cell must have storage capability as well as logic circuits

(a)Associative memory (b)cache memory (c)auxillary memory 21__________ stores both address and content of the memory word (a)Associative mapping (b)Direct mapping (c)Set associatie mapping 22An address used by a programmer is

(a)Virtual address (b)Memory address (c)cache address 23An address in main memory is called a ________

(a)location or physical address (b)memory address (c)address space 24Set of virtual addresses are called

(a)address space (b)memory address (c)memory space

25physical memory is broken down into groups of equal size is called as___________ (a)blocks (b)packets (c)pages

SECTION B (4 X 5 =20)

1. Explain about page replacement in virtual memory. 2. Discuss about page table mapping.

3. What are the main memory and explain?

4. What are the various mapping procedures in cache memory? 5. Write about the set associative mapping.

SECTION C (1 X 10 = 10)

1. Explain the need for memory hierarchy.

2. What do you mean by cache memory? Explain its process. 3. Explain in detail about the memory organization in detail. 4. Discuss about the associative memory.

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(a)32 (b)64 (c)8

2 The 80286 addresses ____ Byte of physical memory (a)16 M (b)32M (c)8M

3 the 80286 doesn’t incorporate internal peripherals; instead it contains___________ (a)MMU (b)PDU (c)TXT

4 80286 has___ registers & data bus (a)16-bit (b)32-bit (c)64-bit

5 Backwards Compatibility with ____________ CPUs (a)82x86 (b)80x86 (c)80x84

6 80486 have

(a)Integrated FPU (b)integrated IDU (c)32 NIFT 7 80286 AND 80386 has____pipeline stages

(a)3 (b)4 (c)2

8 MMU means__________

(a)Memory management unit (b)memory miss unit (c)none 9 In 80486 Load 16 bytes of instructions into

(a)prefetch buffer (b)register (c)stack 1

0

____________Translates linear addr. to physical addr. (a)Paging Unit * NEW (b)paging *update (c)none 1

1

Interprets instructions from IDU

(a)In 80486 (b)Control Unit *Half EU (c)both 1

2

___________Performs arithmetic & logic operations,in 386 instruction set

(a)Cache Unit *NEW (b)Floating-point Unit *NEW (c)Integer (datapath) Unit *Half EU 1

3

the 80286 addresses a_______ memory address space (a)1MByte (b)1kb (c)32 bit

1 4

In the protected mode, the 80286 addresses a_______memory space (a)16MByte (b)32MByte (c)8MBypte

1 5

The 80386 has a physical memory size of (a)4GBytes (b)12MBytes (c)32Mbytes 1

6

80386 virtual memory with up to (a)32Mbytes (b)64Tbytes (c)32Gbytes 1

7

The 80386 is operated in the _______________mode (a)private (b)protected (c)pipelined

1 8

BR means

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1 9

ALE means

(a)Address latch enable (b)Address list enable (c)none 2

0

The 80386 is also capable of _____ (a)Protected (b)paging (c)private 2

1

The 80386 is operated in the real mode (i.e. 8086 mode) when it is _________ (a)reset (b)hold (c)set

2 2

The 80486 microprocessor executes a few new instructions that control the internal_______ (a)cache memory (b)Virtual memory (c)main memory

2 3

BIST means

(a)builtin self-test (b)built in server test (c)none 2

4

TR3____

(a)cache data (b)cache control (c)cache status 2

5

If the 80486 passes the test, EAX contains a ____________ (a)zero (b)one (c)neutral

SECTION B (4 X 5 = 20)

1. Discuss about the addressing modes of the processor 80286. 2. Draw and explain the pin diagram of processor 80486. 3. Discuss about the addressing modes of the processor 80386. 4. Distinguish between 80386 and 80486 microprocessor. 5. Write short notes on: Microcontroller 8085.

SECTION C (1 X 10 = 10)

1. Discuss about the architecture and organization of the processor 80386. 2. Discuss about the architecture and organization of the processor 80286. 3. Write a short note on microcontrollers and its features.