Algorithmic Design Methodologies and Design Porting of Wireline Transceiver IC Building Blocks Between Technology Nodes
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(2) Outline • Introduction • Low-noise broadband input comparators • Mm-wave VCOs • High-speed logic gates • Circuits beyond 40 Gb/s • Summary.
(3) Si(Ge Bi)CMOS speed is free ... if you can afford the mask costs!. MOS-HBT (BiCMOS) Cascode. • MAG > 8 dB @ 65 GHz in HBTs and MOSFETs • HBT-based cascodes have highest gain • Benefits of the MOS cascode questionable at 65 GHz.
(4) Fundamental limitations of dynamic range Voltage. Breakdown voltage. Dynamic Range. Dynamic range compressed as data rates increase. Noise floor Bandwidth Emphasizes need for low-noise design methodologies.
(5) Power dissipation a major limitation in circuits beyond 40 Gb/s • Bipolar only implementations suffer from – VCC >= 3.3V – 40 GHz latch consumes more than 50 mW. • CMOS has lower supply voltage and lower power dissipation but – 40 GHz latch has yet to be demonstrated - must design in 90/65 nm with first pass success Emphasizes need for new low-voltage, high-speed logic topologies and robust design methodologies.
(6) Goal of this presentation • Prove that algorithmic design methodologies exist for optimal solutions for all wireline building blocks – Broadband input amplifiers – VCOs – (Bi)MOS-CML logic gates. • Prove that CMOS implementations are portable between technology nodes and foundries.
(7) Key enablers • Invariance of characteristic current densities in MOSFETs • Low-noise broadband matching, biasing, and sizing • Low-voltage (Bi)CMOS topologies • Small footprint (less than 20 mm per side) inductors with SRF> 100 GHz.
(8) MOSFET characteristic current densities invariant across nodes & foundries. Peak fT @ 0.3 mA/mm. Peak fMAX @ 0.2 mA/mm. NFMIN @ 0.15 mA/mm.
(9) Characteristic MOSFET current densities invariant over CS and cascode topologies • The peak fT current density of a MOSFET cascode stage remains 0.3 mA/mm • Cascode stage can be treated as a composite transistor in circuit design (fT, fMAX, NFMIN) • fT of MOSFET cascode is < 60% of MOSFET fT.
(10) Vertically stacked, multi-metal inductors for CML logic • Q is not important • Size is important • Maximize L*SRF to trade-off tail current for bandwidth • Use 3-7 metals T. Dickson et al. IMS-2004.
(11) Low-noise broadband amplifiers VCC. VCC. VCC. Z0. RC. Z0. RC. RC. L0. LC. L0. LC. LC. VOUT VIN. VIN. Q1. Q2. VOUT. Q1 Q2. VIN. LF. RE. VDD = 1.2 V. VDD = 1.2 V. Z0. RC. VOUT. Q1. W = 40 um. RF. VDD = 1.2 V. W = 120 um W = 40 um 3mA. L0. LC. 180 pH. 180 pH. 200 Ohm M1. 200 Ohm. 600 pH. 650 pH W = 40 um. W = 40 um IT. W = 60 um. W = 20 um.
(12) Transistor low-noise design (S. Voinigescu et al., BCTM 1996). 130nm MOSFET. HBT. JOPT. JOPT. Lowest noise achieved when transistor biased at JOPT (0.15mA/mm). Transistor noise parameters scale with emitter length/ gate width. RN = R/LE RN = R/W. GN = G2LE GN = G2W. GCOR = GC2LE GCOR = GC2W. BCOR = BLE BCOR = BW. Optimal biasing and sizing of transistor @ BW3dB is key to low noise design..
(13) Sizing SiGe HBT TIA & INV designs for noise matching. TIA requires much smaller transistor size: Higher bandwidth Broadband input match lEOPT. Lower power consumption.
(14) Broadband CMOS LNA topology scaling VDD = 1.2 V. VDD = 1.2 V. Z0. RC. W = 40 um. VDD = 1.2 V. W = 120 um W = 40 um 3mA. L0. LC. 180 pH. 180 pH. 200 Ohm M1. 200 Ohm. 600 pH. 650 pH W = 40 um. W = 40 um IT. W = 60 um. W = 20 um. Biased at 0.15 mA/mm W, IDS do not change with nodes NF50 and BW3dB improve as technology scales.
(15) Algorithmic design methodology for broadband low-noise TIAs 1. Bias HBT(MOSFET) at optimal noise current density JOPT (0.15 mA/mm) at 3dB frequency 2. Choose the DC voltage drop across RC for linearity requirements. This fixes the loop gain T = gmRC (=gm*ro) 3. Set the feedback resistance RF for 50 input match. 4. Size the emitter length (gate width) of Q1 for lownoise, such that the TIA noise impedance is 50 . 5. Add inductors to extend bandwidth and filter highfrequency noise..
(16) Measured single-ended 50-Ohm noise figure VCC. VCC. VCC. Z0. RC. Z0. RC. RC. L0. LC. L0. LC. LC. VOUT VIN. Q1 RE. VIN. Q2. VOUT. Q1 Q2. VIN. VOUT. Q1 LF. RF. •Differential versions of three circuits implemented •Measured single-ended noise figure in 50 Ohm. TIA has low noise over entire measured bandwidth.
(17) 40-Gb/s eye diagrams 20-mV single-ended input (10-mV per side). EF-INV. TIA. Eye quality better for TIA (7.0) than EF-INV (5.8).
(18) 90-nm SOI TIA. 40mm. 10 Gb/s. • • • •. 8-dB noise figure 1V supply 6 mW p-MOS load. 15 Gb/s.
(19) VCOs.
(20) HBT VCOs • Differential Colpitts topology. gm Neg. Res. = Rb - 2 ω C1C 2 f osc. 1 C1C 2 = , C EQ = C1 + C2 2π LB CEQ.
(21) SiGe HBT oscillator measurements Impact of: 1. base (tank) inductor 2. inductive emitter degeneration (LE). C. Lee et al. CSICS-2004.
(22) CMOS VCOs VDD = 1 V. VDD = 1 V ISS. L. 2L. C. C. L. Von. Vop. Q2. Q1. Vop. Von. Q2. Q1 ISS. osc , CMOS ≤. 2 3. g ' m Q eff CL C ' gs 4 C ' gd C ' db W. osc , n −MOS ≤. g ' m Q eff. CL C ' gs 4 C ' gd C ' db W 1 W n −MOS ,cross ≤ 2 osc L [C ' gs 4 C ' gd C ' db ].
(23) Colpitts CMOS/BiCMOS VCOs VDD = 1 V 100 pH 80 pH. LD. LD. Von. 100 pH Q2. 30x1mmx65nm. C1 40 fF. C2. 100 pH LT. LT. 40 .. 80 fF 200 pH. C1 40 fF. C2. 80 pH. Q1. 200 pH. RSS. Vop. 3x9mm Q4. Q3 3x9mm 200 pH. Q2 33x1mmx130nm. C1 30 fF. C2. LT. 230 fF 415 pH. CSS =0.5 pF. 1 C ' gs C ' sb 2 osc L k C ' gd C ' gs C ' sb. [. Colpitts has higher fOSC and built-in buffering over X-coupled. LT. C1 30 fF. C2. Q1 33x1mmx130nm. VCON. 415 pH LS. LS. ]. 200 pH. 230 fF. RSS. W n −MOS , Colpitts ≤. 100 pH. Von. Vop. LS LSS 200 pH. LS. LD. 30x1mmx65nm. 40 .. 80 fF VCON. VDD = 2.5 V. LD. A E , HBT , Colpitts ≤. CSS =1 pF. [. 1. C var AE 2 osc L k C jcA C var C ' jbA AE C jbA. ].
(24) BiCMOS cascode oscillator measurements. •. Measured phase noise at 35 GHz and simulated NFMIN of SiGe MOS-HBT cascode stage as a function of gate voltage.
(25) VCO design methodology VCOs treated as LNAs matched to the “source” impedance Rp. This is generally not possible in cross-coupled VCOs! • VCO topology (CS/CE or cascode) biased at optimum NFMIN current density (0.15 mA/mm in FETs) • Vosc must be set close to VMAX to minimize phase noise • Lower inductance, higher bias current, better L(fm) – HBT-VCOs have 6..10 dB better phase noise due to larger VMAX L. ∣In∣. 2. C1. L f m =. V1. VOSC RS R<0. C2. 2 V osc. ×. 1 × f m2. 1. C1. 2. C1 1 C2. 2.
(26) High-Speed Logic.
(27) Logic families RL Wp. DV. kWp. RL. DV. RL OUTP. Wn. kWn. DV. DV IT. RL OUTN. INN. IT. INP IT. Fig. 9. Inverters in various CMOS and SiGe BiCMOS logic families.. • Unlike conventional CMOS, gate & subthreshold leakage is not a problem in MOS-CML • In MOS-CML low-VT is desirable • MOS-CML with peaking is > 3x faster than CMOS.
(28) MOS/BiCMOS CML device sizing & biasing VDD = 1.8 V. VDD = 1.8 V 330 . 330 . 250 . 1 nH. 1 nH. 1 nH. 250 . 1 nH. OUT. OUT OUT. Q1. Q3. Q2. DATA DATA. Q1. Q4. Q3. Q2. DATA. CLK. CLK. IT. IT. 2 Veff ≤ V≤2 Veff C R L p= L 3.1. 2 L. scales with L. CL V 2 Lp = 3.1 IT2. Q4. W=. IT 1.5 J peakfMAX. BW 3 dB=. =. IT 0.3 mA /m. 1.6×IT 2 V CL. ; AE =. ITmin= V. IT 1.5 J peakfMAX. . CL 3.1 Lpmax. • For a given speed and technology there is a maximum realizable Lpmax • Speed improvement as CMOS scales is due solely to Veff (DV) scaling..
(29) BiCMOS ECL latches (> 49 GHz). 2.5 V supply, IT=2 .. 4mA. 3.3 V supply, IT=2 .. 4mA. • BiCMOS cascode with EF (SF) • EF vs. SF: – higher gain, lower E-S capacitance – VBE > VGS.
(30) Evolution to 1-V, 40-GHz latch DUMMY. VDD = 1 V 330 . 330 . 1 nH. 1 nH. DUMMY. OUT. LVT QUAD. Q3. S. D1. S. D2. S. S. D1. S. S. D1. S. D2. S. D1. S. D2. S. D2. S. G1. Dummy. G1. G2. G2. G2. G2. G1. HVT Pair. G1. HVT. Dummy. CLK. HVT. D1. S. S. D2. S. G1. Dummy. G1. G2. G2. G2. G2. G1. G1. Dummy. G1. Dummy. G2 D2. G1. G2. G2. G2. LVT. G1. LVT. Q4. G1. DATA. Q2. Dummy. Q1. D1. S.
(31) Wireline circuits beyond 40 Gb/s.
(32) 2.5-V, Broadband 49-GHz MS DFF BiCMOS D-Flip Flop Data In. D. Q. Transimpedance Preamplifier. Data Out. 45 Gbs. 50- Output Driver CLK Buffer CLK. 12 Gb/s. 40 Gb/s.
(33) 2.5-V, 80-GHz driver with pre-emphasis and gain control VDD = 2.5 V 55 125 pH. 27.5 . Q2. 50 pH. 50 pH. 3x4.8mm Q1 3x4.8mm. Q3. 33x2mmx130nm. 2x4.8mm. 10 mA. 10 mA. Von. 2x4.8mm. 4x4.8mm Q4. 23.5 10 mA. Vop. 10 mA. 10 mA. 10 mA 20 mA. • Adjustable gain with peaking • Gain > 0 dB @ 94 GHz • S22<-12 dB up to 94 GHz • 130-nm MOS-HBT cascode.
(34) 31. 80-Gbs SiGe BiCMOS 2 -1 PRBS Generator. T. Dickson et al. ISSCC-2005.
(35) Selector: BiCMOS 80-Gb/s. D1. D2. •EF2 & series-shunt peaking for highest speed •3-D stacked inductor for reduced area and high SRF VCC = 3.3V. DOUT. RL LP1. CLK D2 CLK. VGTAIL. D1. RL LP1. LP2 DOUT LP2.
(36) 40-Gb/s Feed Forward Equalizer. • core of each gain stage is a Gilbert cell • tail current of the differential pair controls the tap weight (GAIN pad) • SP/N pads control the tap sign A. Hazneci et al. CSICS-2004.
(37) 40 Gb/s over 9-ft SMA cable + 3dB attn. input. output.
(38) 10 Gb/s equalization over 24-ft SMA cable +6dB attn..
(39) 100-Gb/s transmission over 5cm of on-chip interconnect possible in 90nm SiGe BiCMOS. • Model extracted from meas. on 3.6-mm long line • 7-tap FFE equalizer.
(40) Summary • Key design ideas: – Optimal solutions exist for LNA, TIA, VCO, (Bi)CMOSCML gate topologies – Biasing at minimum noise figure current density – Matching noise impedance to signal source (tank) impedance • Key MOSFET circuit scaling ideas – FETs should be biased at constant current density – Circuit size and bias current invariant over nodes while performance improves with scaling • Circuits in the 50-80 GHz range • Sub-3W, 100 Gb/s Ethernet transceiver possible in 250GHz, 90-nm SiGe BiCMOS technology.
(41) Acknowledgments • Bernard Sautreuil for his support over many years • STMicroelectronics for fabrication • Micronet, NSERC, Gennum Corporation and STMicroelectronics for financial support • OIT and CFI for equipment grant • CMC for CAD licenses.
(42) Backup.
(43) Impact of scaling in deep-submicron MOSFETs (500nm to 50nm) • As a result of the constant-field scaling rules being applied to every new CMOS technology node: – Voltages scale by factor S – Vertical & lateral electric fields remain constant – Charge per unit gate width and current per unit gate width remain constant – The classical MOSFET I-V square law remains valid only at very low Veff beyond which it becomes linear.
(44) Mobility degradation • Mobility degradation due to the vertical gate field dominates behaviour (based on Intel data, S. Thompson, IEDM'99 Short Course).. eff =. [ ] [ ]. ac sr ac sr. [ ] [ ]. ac. cm 2 MV ≈330 E eff −1/3 Vs cm. sr. cm 2 −2.9 MV ≈1450 E eff Vs cm. • The lateral field (due to VDS bias) is about 50 times smaller than the vertical field.
(45) Measured transfer & subthreshold characteristics in 90-nm n-MOSFETS.
(46) Measured small signal gm, Cgs, Cgd characteristics in 90-nm n-MOSFETS.
(47) Si vs. III-V FETs: fT, fMAX. S. Voinigescu et al. JHSES, March 2003. peak fT: 0.3 mA/mm peak fMAX: 0.2 mA/mm.
(48) Consequences of constant-field scaling in 500 nm to 50 nm MOSFET channels: • C'gs, C'gd, C'db constant over nodes down to 130 nm then decreasing as scaling of tOX stopped at 1.2 nm • g'm, g'ds, fT, fMAX increase • FMIN, Rn decrease • RF & high-speed performance (except output swing) improves with scaling • Constant current density biasing ensures design robustness over bias current, VT, process variation, nodes & foundries. Scaling is good for high-speed digital/wireline.
(49) 60-GHz, single metal inductor for VCOs Planar spiral inductor:. C. Lee et al. CSICS-2004. Diameter = 27 mm Turns = 1 ¾ S = 2 mm, W = 2.5 mm. Slide 49.
(50) Applying negative feedback for noise matching • Negative feedback has similar impact on noise and input impedance • Use Y-matrix to analyze noise params of: – Multifinger MOSFETs – CMOS inverter topology – Parallel (transimpedance) feedback circuits. • Use Z-matrix to analyze noise params of: – Differential stage – Series feedback circuits: • Tuned LNA with L (xfmr) degeneration • EF input • Inverter with resistive degeneration.
(51) Series feedback for noise matching. . r ∣z CORF −Z 11 F∣ g NF 2 z SOP = r SOPA NF 2 r CORA ℜZ 11 F ℜ2 Z 11F j [X SOP −ℑZ 11 F ] g NA g NA F MIN =12 g NA [r CORA r SOP ℜZ 11 F ]. 2.
(52) Parallel feedback for noise matching. . G NF ∣Y CORF −Y 11 F∣ R NF 2 2 Y SOP = G SOPA 2G CORA ℜY 11 F ℜ Y 11 F j [B SOP −ℑY 11 F ] R NA R NA. F MIN =12R NA [G CORA G SOP ℜY 11 F ]. 2.
(53) Inverter noise matching. ∣. 1. ∣ 2. 2 F Zo =1 Z R Y G N 0 N COR 2 Z 0 L 0 1 Z0. . l E W OPT =. 1 2 Z0. . 1 G G C2 B 2 R. TIA noise matching. ∣. ∣. 2. Z0 1 1 1 1− j 0 F Zo =1R NA Z 0 Y CORA Z 0 G NA Z 0 R F 102 R F 102. 1 l E W OPT = . . . 1 1 1 1 0 Z 0 R F 102 R F 102 2. 2. 1 G G C2 B 2 R. ZIN=. RF 1RC IT. RF > Z0 for 50 match, resulting in lower noise & smaller transistor size than low-noise INV design.
(54) CMOS topology • In 90-nm CMOS, the p-MOSFET is low-noise and fast enough for most applications up to 40 Gb/s – Use CMOS inverter to improve gm/I, Rn to save current over NMOS-only implementations.
(55) Si CMOS, SiGe BiCMOS, InP low-noise broadband preamps IN+. OUT+. IN-. OUT-. OUT+ IN OUT+.
(56) Low-noise broadband preamps: InP vs. SiGe BiCMOS (H. Tran et al. GaAs IC Symp. 2003 for InP TIA) SiGe: 40 Gbs. NF at 10 Ghz CMOS 16.5 dB SiGe-HBT 10 dB InP-HBT 11.5 dB. InP: 40 Gbs. Data Rate 20 Gb/s 40 Gb/s 40 Gb/s. Sensitivity 20 mVpp 20 mVpp 8 mVpp.
(57) Push-Push VCO measurements (con’t) Tuning characteristics: Tuning: 10 GHz (10.2%). Tuning: 15 GHz. (21%). C. Lee et al. CSICS-2004. Slide 57.
(58) CMOS VCO design scaling and porting • As technology scales to next node, g'm increases but VMAX decreases, • Ideally W and IDS are fixed to maintain VOSC • In reality W and IDS must be reduced in sync with VMAX • maximum fOSC increases hence larger Cvar can be used – Scaling allows for smaller IDS&W but not necessarily better L(fm).
(59) High-Speed Logic FoM: CML Gate Delay I DpeakfT SL FET = C gd Cdb. I CpeakfT SL HBT = C bc C cs. . C 1− AV C bc C bc C cs Rb HBT ≈V k V IT RL IT. . C gd C db Rg C gs 1− AV C gd FET ≈V k V IT RL IT BiCMOS ≈V. C C cs IT. Rg C gsC gd k V RL IT.
(60) Scaling of MOS/BiCMOS CML logic Table 1: fanout-of-1 latches ideal i.e. no parasitics, *) measured Latch Family Rate:Gbs VDD (V) DV (V) IT (mA) PD(mW) Ind (nH) 130nm MOSCML 40 1.8 0.5 1.5(2.4) 2.7 2 130nm BiCMOS 40 1.8 0.2 0.83 (1.6) 1.5 (2.9) 1 CML 130nm BiCMOS 12 2.5 0.2 1 2.5 0 CML *) 130nm BiCMOS 50 2.5 0.25 7.5(12.5) 18(30) 0.25 ECL *) 90nm MOSCML 40 1.2 0.38 1.8 2.2 0.5 90nm BiCMOS 40 1.5 0.2 1 1.5 0.5 CML 90nm BiCMOS 30 1.5 0.2 1 1.5 0.5 CML extracted 65-nm MOSCML 60 1 0.35 2.5 2.5 0.5. • Assumes maximum inductor SRF of 80 GHz*nH and SRF=2*Bitrate • Numbers in brackets include emitter(source) followers.
(61) 49 Gb/s over 6-ft cable 49 Gbs. 43 Gbs.
(62)
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