Dr. Vasantraodada Patil Shetkari Shikshan Mandal’s Dr. Vasantraodada Patil Shetkari Shikshan Mandal’s
PADMABHOOSHAN VASANTRAODADA PATIL INSTITUTE OF
PADMABHOOSHAN VASANTRAODADA PATIL INSTITUTE OF
TECHNOLOGY, BUDHGAON-416304
TECHNOLOGY, BUDHGAON-416304
LAB Manual
LAB Manual
Xilinx ISE 7.1
Xilinx ISE 7.1
(Digital System Design)
(Digital System Design)
DEPARTMENT OF ELECTRONICS ENGINEERING
DEPARTMENT OF ELECTRONICS ENGINEERING
(2010-11)
(2010-11)
Xilinx ISE Overview
Xilinx ISE Overview
The Integrated Software Environment (ISE™) is the Xilinx® design software suite that allows you to The Integrated Software Environment (ISE™) is the Xilinx® design software suite that allows you to take your design from design entry through Xilinx device programming. The ISE Project Navigator take your design from design entry through Xilinx device programming. The ISE Project Navigator manages and processes your design through the following steps in the ISE design flow.
manages and processes your design through the following steps in the ISE design flow. Design Entry
Design Entry
Design entry is the first step in the ISE design flow. During design entry, you create your source Design entry is the first step in the ISE design flow. During design entry, you create your source files based on your design objectives. You can create your top-level design file using a Hardware files based on your design objectives. You can create your top-level design file using a Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or using a schematic. You can use Description Language (HDL), such as VHDL, Verilog, or ABEL, or using a schematic. You can use multiple formats for the lower-level source files in your
multiple formats for the lower-level source files in your design.design. Note:
Note: If you are working with a synthesized EDIF or NGC/NGO file, you can skip design entry andIf you are working with a synthesized EDIF or NGC/NGO file, you can skip design entry and synthesis and start with the implementation process.
synthesis and start with the implementation process. Synthesis
Synthesis
After design entry and optional simulation, you run synthesis. During this step, VHDL, Verilog, or After design entry and optional simulation, you run synthesis. During this step, VHDL, Verilog, or mixed language designs become netlist files that are accepted as input to the implementation step. mixed language designs become netlist files that are accepted as input to the implementation step. Implementation
Implementation
After synthesis, you run design implementation, which converts the logical design into a physical file After synthesis, you run design implementation, which converts the logical design into a physical file format that can be downloaded to the selected target device. From Project Navigator, you can run format that can be downloaded to the selected target device. From Project Navigator, you can run the implementation process in one step, or you can run each of the implementation processes the implementation process in one step, or you can run each of the implementation processes separately. Implementation processes vary depending on whether you are targeting a Field separately. Implementation processes vary depending on whether you are targeting a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).
Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD). Verification
Verification
You can verify the functionality of your design at several points in the design flow. You can use You can verify the functionality of your design at several points in the design flow. You can use simulator software to verify the functionality and timing of your design or a portion of your design. simulator software to verify the functionality and timing of your design or a portion of your design. The simulator interprets VHDL or Verilog code into
The simulator interprets VHDL or Verilog code into circuit functionality and displays logical results ofcircuit functionality and displays logical results of the described HDL to determine correct circuit operation. Simulation allows you to create and verify the described HDL to determine correct circuit operation. Simulation allows you to create and verify complex functions in a relatively small amount of time. You can also run in-circuit verification after complex functions in a relatively small amount of time. You can also run in-circuit verification after programming your device.
programming your device. Device Configuration Device Configuration
After generating a programming file, you configure your device. During configuration, you generate After generating a programming file, you configure your device. During configuration, you generate configuration files and download the programming files from a host computer to a Xilinx device. configuration files and download the programming files from a host computer to a Xilinx device.
What's New in Xilinx ISE 7.1i
What's New in Xilinx ISE 7.1i
This file describes the new features in the Xilinx® Integrated Software Environment (ISE) 7.1i This file describes the new features in the Xilinx® Integrated Software Environment (ISE) 7.1i software release. It contains the following sections:
software release. It contains the following sections: New Device Support
New Device Support
New Software Features
New Software Features
New Partner Product Features
New Partner Product Features
Technical Support
Technical Support
New Device Support New Device Support
This release includes support for the following device families. This release includes support for the following device families.
Spartan-Spartan-3E™ FPGA Family3E™ FPGA Family
Spartan-Spartan-3L™ FPGA Family3L™ FPGA Family
Spartan-Spartan-3™ FPGA XA (Xilinx Automotive) Family3™ FPGA XA (Xilinx Automotive) Family
Spartan-Spartan-IIE™ FPGA XA FamilyIIE™ FPGA XA Family
CoolRunnner-CoolRunnner-II™ CPLD XA FamilyII™ CPLD XA Family X
XA9500XL™ CPLD XA FamilyA9500XL™ CPLD XA Family New Software Features New Software Features
Following are the new features in this release. Following are the new features in this release. Design Management
Design Management
Following are the design management and design entry enhancements: Following are the design management and design entry enhancements: Improved ability to run multiple versions of ISE Software.
Improved ability to run multiple versions of ISE Software.
o
o Version-specific Windows® desktop icon and program group created.Version-specific Windows® desktop icon and program group created. o
o ISE executable sets environment for its version; no need to manually manage environment whenISE executable sets environment for its version; no need to manually manage environment when
switching versions. switching versions.
o
o Simply double-click desktoSimply double-click desktop icon (or p icon (or select from program group) for desired version.select from program group) for desired version.
Project Navigator features Project Navigator features
o
o New Technology ViewerNew Technology Viewer
Provides schematic view of post-synthesis/optimization netlists.Provides schematic view of post-synthesis/optimization netlists.
o
o RTL and Technology Viewers improvementsRTL and Technology Viewers improvements
Cross probing from logic in the RTL Viewer to corresponding source code lines in the ISE TextCross probing from logic in the RTL Viewer to corresponding source code lines in the ISE Text
Editor. Editor.
Enhanced schematic rendering capability, providing improved readability.Enhanced schematic rendering capability, providing improved readability.
o
o Easier to add multiple VHDL or Verilog sources viaEasier to add multiple VHDL or Verilog sources via Apply to All Apply to All checkbox on Source Type dialog.checkbox on Source Type dialog. o
o Easier to enable/disable Advanced properties using option in Process Properties dialog boxes.Easier to enable/disable Advanced properties using option in Process Properties dialog boxes. o
o Improved CORE Generator™ software integration.Improved CORE Generator™ software integration. o
o New process to add editable test bench from TBW to project in single step.New process to add editable test bench from TBW to project in single step. o
o Design Summary viewDesign Summary view
The most useful design flow information is shown in a single view, and is updated immediately asThe most useful design flow information is shown in a single view, and is updated immediately as
new information becomes available. new information becomes available.
o
You can customize your output and reports to hide certain warning or info messages not applicable
to your design.
o Tools integration
Mentor Graphics® Precision® RTL Synthesis flow is now integrated into Project Navigator on all
platforms.
Cross probing between Timing Analyzer (ITA) and FPGA Editor.
Integration of Schematic and Symbol Editors, RTL and Technology Viewers, and ISE Simulator
within Project Navigator.
Improved integration with Xilinx Platform Studio.
o Pushing into a flat (non-hierarchical) user-defined symbol now presents the option to create a
VHDL, Verilog, or schematic definition.
o New Paste Special command in Schematic Editor gives more control over how nets and inputs are
named in the pasted content.
o Design Rule Checks now detect illegal wired-OR connections.
o New preferences give control over the width of nets and buses when printing a schematic.
o Schematic Editor has added support for a Partial Bus I/O by providing the ability to take one or
multiple bits of a bus out to an individual I/O port. ISE Text Editor features
o When the RTL Viewer cross probes to a source file, cross probing back to the schematic is
enabled.
o Comment and Uncomment functionality is available. VHDL/UCF only have the
Comment/Uncomment LINE functionality. Verilog has both Comment/Uncomment LINE and Comment/Uncomment SELECTION.
o Increase and Decrease Indent functionality is available from menu items and toolbar buttons.
o You can view/edit the preferences for the ISE Text Editor, in the typical manner. Preferences
include the font used by the editor, how to treat tab characters, and whether to allow the cursor to be moved beyond the end of the line.
o Functionality for adding and removing breakpoints is available for debugging code while running in
the ISE Simulator.
Synthesis
Following are the Xilinx Synthesis Technology (XST) enhancements. For more information, see the XST User Guide available from the Software Manuals collection.
VHDL Language Support
o Support for configurations and nested configurations.
o Support for shared variables (dual-write block RAM inference only). o Support for NULL arrays.
o Improved support for File Read.
Support for hexadecimal values in read operations.
Support for std_ulogic type (limited to values “1” and “0”). Support for character and string type read functions.
Verilog Language Support
o Support of defparams for passing attributes to Xilinx® library primitives. o Support for variable part select.
o Improved support for while loops.
Macro Inference
o Support for parity bits use for block RAM implementation (limited to Virtex-4™ devices). o Support for Block RAM initialization via signal declaration mechanism.
Initialization of dual-port block RAMs in VHDL.
Initialization of single and dual-port block RAMs in Verilog.
o Support for Block RAM/Block ROM initialization from an external text file. o Finite State Machine (FSM) Processing.
Support for Safe FSM implementation.
Improved automatic FSM encoding selection.
Introduced new speed oriented encoding method, called Speed1. Report of original and final FSM encoding.
o Support for Macro inference for Virtex-4 devices and its control via USE_DSP48
constraint/command line switch.
o More Macro Inference capabilities are listed in Chapter 1 of the XST User Guide . See the XST User
Guide available from the Software Manuals collection Design Constraints
o New constraints controlling design processing have been added. Seven constraints have been
updated with new values or capabilities. Please refer to Chapter 1 of the XST User Guide for a complete list of all the new and modified constraints.
o New syntax for switches supporting multiple directories. This change is related to the support of file
and directory names with spaces. FPGA Flow
o Support for automatic inference of BUFGs on most critical internal clocks controlled by
BUFFER_TYPE constraint.
o Improved support for Incremental Synthesis. INCREMENTAL_SYNTHESIS constraint can now be
applied to blocks instantiated more than once.
o Improved detection and reporting of multi-source problems.
o The number of analyzed or failed paths and ports is now reported in Detailed Timing Report. o Improved quality of results under high optimization effort for speed-oriented optimization.
Verification
Following are verification enhancements: New ISE Simulator
o New built-in HDL simulator, available in limited (free) and unlimited versions.
o Integrated VHDL/Verilog simulator with integrated wave editor for test bench creation. o Behavioral/RTL simulation prior to synthesis.
o Timing simulation after place and route or fitting. o Design Hierarchy, waveform, and console views. o Source-level debugging capabilities.
o Command-line console features TCL interface.
o Generate Expected Results process generates expected design output behavior based on input
stimulus.
o Simulator can generate Value Change Dump (VCD) file for use in XPower. o Available in Base and Foundation™ configurations only.
Simulation Performance Improvements
o UNISIM and SIMPRIM library optimizations to reduce simulation runtimes. o CompXLib Verilog library compilation time reduction.
Memory Model Improvements including 2-dimensional array representation of memory contents and added control of memory collision checks.
New JTAG simulation model added for Virtex-4 devices. Ability to generate XST post-synthesis simulation netlists. ModelSim® Xilinx Edition III support.
o ModelSim Xilinx Edition III is upgraded to version 6.0a.
o Increased capability in free MXE III Starter to support larger designs with better performance. o 20% additional performance improvement in full MXE III.
ChipScope Pro™ improvements
o Operating System Support
The ChipScope Analyzer joins the Core Generator and Inserter on Linux and Solaris platforms. Enterprise Linux 3.0 is fully supported, and Solaris 8 and 9 are supported in client-server mode.
o Storage Qualification is available for ILA and IBA cores.
This feature, introduced in 6.3.01i, allows users to filter data to be stored after trigger conditions
have been met.
o Performance Increase to over 300MHz.
ILA and IBA cores have been re-engineered for Virtex- II™, Virtex-II Pro™, Virtex-4, and
Spartan-3™ devices, leading to performance improvements up to a 50% increase in clock frequency.
o Multi-Gigabit Transceivers can be debugged by ChipScope Pro software.
o The ChipScope Core Inserter now supports full netlist insertion. Designs utilizing Hierarchical
Design flows and non-secure IP blocks can now be fully instrumented.
o New communication support: Platform Cable USB o Updates to ATC2 cores support
The ATC2 cores now support Virtex-4 devices.
Multiple ATC2 cores can be inserted in a single FPGA.
The new Plug & Debug process will automatically associate individual signals in the FPGA to the
logic analyzer probe inputs without user intervention.
ATC2 cores are supported on the 1680, 1690, and 16900 Logic Analyzers as well as the Infiniium
Mixed-Signal Oscilloscopes.
Implementation
Following are implementation enhancements: FPGA Editor Features
o Ability to see larger shapes that utilize multiple components (such as a carry chain and wide
function) and move and place these shapes together.
o Ability to change background from black to white.
Constraints Flexibility
o Bus delimiters in the UCF file do not have to match the delimiters in the source netlist. Any of the
delimiter types – < >, [ ], { }, or ( ) – can be used to denote a signal within a bus. Improvements to Timing-Driven Packing and Placement
o The Place and Route Extra Effort option is available when the Map Effort Level is set to High.
Values available are Normal and Continue on Impossible.
o The Place and Route Starting Cost Table option is available. Values can range from 1 to 100.
o A new Register Duplication feature can also be enabled, allowing Map to replicate flip flops to
improve timing.
Improved detection of designs containing paths that cannot be routed.
o Rather than spend a long time attempting to route a design with unroutable paths, the router quickly
detects such cases. Upon detection of an unroutable path, the router exits, giving detailed information about the reason the design is unroutable.
PlanAhead
o Ability to edit/create constraints and analyze the effect of the changes using TimeAhead.
o Support for PBlock geometry to comprise multiple rectangles enabling rectilinear shaped PBlocks. o Improvement in correlation between the estimated TimeAhead report and the TRACE post-routed
timing results.
o Design Rule Check warning users if RTL code is written to not use synchronous output registers
(inside the DSP48 and RAMB16).
o The order and comments in the input UCF file are now preserved in the PlanAhead output UCF file. o Ability to apply a floorplan from an existing netlist to a newly resynthesized netlist to preserve QOR. o Reduction in memory use when loading large designs.
Device Configuration
Following are the cable software enhancements:
The new CableServer executable allows for programming of devices across a network. Following are the iMPACT enhancements:
The new iMPACT Project File (.ipf) provides an easy way to save and restore any configuration work.
Ability to execute SVF files.
Configuration Debug enhancements
o New Debug menu
o Capability to determine if a JTAG chain is broken and where the break occurs.
o Capability for users to read and decode the FPGA configuration status register at any time.
Improvements to wizards and dialogs for both PROM-file creation and PROM programming functions.
Support drag-and-drop addition of files to projects.
Advanced Users will have the ability to switch off the iMPACT wizard for many functions.
ISE Software Documentation Improvements
Following are improvements to the ISE Help:
ISE Help provides access to all help packages available and includes a common search and indexing capability.
ISE Help now includes design strategies for each of the steps in the ISE software flow.
New Partner Product Features
Following are the new features in partner releases related to the Xilinx ISE 7.1i software release. The Cadence® software includes the following enhancements:
The Xilinx specific runtime improvement in the Cadence® NC-Sim tool is now extended to the Virtex-4 family.
Cadence® Conformal-LEC formal verification tool verifies the functionality of the Synplify Pro V8.0 (or later) synthesized netlist against RTL in a more automated fashion and minimum user intervention for the latest FPGA devices including Virtex-4. The Conformal-LEC can also be used to validate the functionality of post PAR netlist against post synthesis netlist.
Cadence® Allegro PCB SI (SPECCTRAQue st) is now compatible with Xilinx latest RocketIO™ design kit.
The Mentor Graphics® software includes the following enhancements: Precision® RTL Synthesis: New device support
QOR Improvements
o Fmax (~10% faster) o Area (~4% smaller)
Precision® Physical
o New device support o Additional functionality
Incremental placement
Bottom up physical design flow support
LeonardoSpectrum™ Synthesis: New device support
FPGA BoardLink now supports the latest Xilinx devices including Virtex-4.
In addition to automating schematic symbols creation and updates, I/O Designer supports the latest device families and performs design rule checks to assist in creating FPGA pinout.
ModelSim v6.0 has new enhanced user interface.
The Synopsys® software includes the following features and enhancements: DC FPGA®
o The latest FPGA synthesis solution from Synopsys provides the flexibility of a Design Compiler for
FPGA designs.
o The ASIC Prototyping Synthesis process can be customized using DC commands, supports
Synopsys DesignWare®, provides inferencing of Xilinx architectural resources including RAMs (BRAM and Distributed RAM).
o New device support.
PrimeTime®
o The ISE software (Netgen) generates netlist and SDF files with max and relative min delays, which
enables min-max analysis within the PrimeTime software.
o New device support.
HSPICE®
o The HSPICE Signal Integrity Simulation (SIS) software supports S-parameter simulation models for
the RocketPHY™ family of physical layer transceivers (PHYs) and the extended Virtex -II Pro family of 10 Gbps transceivers.
o Also includes CosmosScope™, a power ful, new waveform viewer.
Formality®
o The ISE software (Netgen) generates an Equivalency Checking (EC) netlist and Formality setup
(SVF) files to verify RTL to post synthesis and post synthesis to post Place and Route netlists.
o The Formality software supports RAM inferencing, multiplier matching, and verification for operands
greater than 18 bits and new device support. LEDA®
o The LEDA checker supports about 150 FPGA-specific rules, which cover Virtex-II, Virtex-II Pro, and
Spartan-3 devices.
o There are 10 new rules provided in LEDA 4.1 compared to what was available in the previous
version with the ISE 6.1i software.
The Synplicity® 8.0 software includes the following enhancements: Synplify Pro® software
o First feature support for System Verilog
o QOR improvements (Better Performance, smaller area) o New device support
o Graphical Warning Viewer o TCL and GUI Find function o HTML log file
Amplify® Software
o Physical Synthesis o Physical Analyst
o Island Timing Report (Spreadsheet view of timing information)
The Product Acceleration Inc.® software includes the following enhancements:
Automated FPGA pinout assignment for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-4. Updated IO banking design rule checks - single ended and differential pairs for all families.
Support Weighted Average Simultaneous Switching Outputs (WASSO) guidelines for all families. Added Support for local clocking and regional clocking rules for all families.
Added Verilog and VHDL top level entity/module import capabilities. Added support for Import and Export of Xilinx user constraint file (UCF).
Architecture Support
The ISE™ software supports the following device architecture families: FPGAs Spartan-II™ Spartan-IIE Spartan-3™ Spartan-3E Spartan-3L™ Virtex™ Virtex-E Virtex-II™ Virtex-II Pro™ Virtex-II Pro X Virtex-4™ CPLDs CoolRunner™ XPLA3 CoolRunner-II™ XC9500™ XC9500XL XC9500XV
Project Navigator Overview
Project Navigator organizes your design files and runs processes to move the design from design entry through implementation to programming the targeted Xilinx® device. Project Navigator is the high-level manager for your Xilinx FPGA and CPLD designs, which allows you to do the following: Add and create design source files, which appear in the Sources in Project window
Modify your source files in the Workspace
Run processes on your source files in the Processes for Source window View output from the processes in the Transcript window
Note: Optionally, you can run the Project Navigator processes from a script you create or from a command line prompt. However, it is recommended that you first become familiar with the basic use of the Xilinx Integrated Software Environment (ISE™) software and with project management, as described in the following sections.
Project Navigator Main Window
The following figure shows the Project Navigator windows, which allow you to manage your design starting with design entry through device configuration.
1. Toolbar
2. Sources in Project window 3. Processes for Source window 4. Workspace
5. Transcript window
Note For details on these areas, see Project Navigator Main Window. Using the Sources in Project Window
The first step in implementing your design into a Xilinx® FPGA or CPLD is to assemble the design source files into a project. The Module View of the Sources in Project window shows the source files you create and add to your project, as shown in the following figure. For information on creating projects and source files, see Creating a Project and Creating a Source File.
The Module View shows the hierarchy of your design. You can collapse and expand the levels by clicking the plus (+) or minus (-) icons. Each source file appears next to an icon that shows its file type. The file you select determines the processes available in the Processes for Source window. You can double-click a source file to open it for editing in the Workspace. For information on the different file types, see Source File Types.
From the Module View, you can also change the project properties, such as the device family to target, the top-level module type, the synthesis tool, the simulator, and the generated simulation language. For information, see Changing the Target Device and Design Flow .
Note: The Sources in Project window also includes the Snapshot View and the Library View. For information on working with libraries, see Working with VHDL Libraries. For information on working with snapshots, see Working with Snapshots.
Using the Processes for Source Window
The Process View of the Processes for Source window allows you to run actions or "processes" on the source file you select in the Module View of the Sources in Project window. The processes change according to the source file type you select, as shown in the following figures.
The Process View shows the available processes in a hierarchical view. You can collapse and expand the levels by clicking the plus (+) or minus (-) icons. Processes are arranged in the order of a typical design flow: project creation, design entry, constraints management, synthesis, implementation, and programming file creation.
Processes Types
The following types of processes are available as you work on your design: Tasks
When you run a task process, the ISE software runs in "batch mode," that is, the software processes your source file but does not open any additional software tools in the Workspace. Output from the processes appears in the Project Navigator Transcript window.
Reports
Most tasks include report sub-processes, which generate a summary or status report, for example, the Synthesis Report or Map Report. When you run a report process, the report appears in the Project Navigator Workspace.
When you run a tools process, the related tool launches in standalone mode or appears in the Project Navigator Workspace where you can view or modify your design source files.
Note: The icons for tools processes vary depending on the tool. For example, the Timing Analyzer icon is shown above.
Process Status
As you work on your design, you may make changes that require some or all of the processes to be rerun. For example, if you edit a source file, it may require that the Synthesis process and all subsequent process be rerun. Project Navigator keeps track of the changes you make and shows the status of each process with the following status icons:
Up-to-date
This icon shows that the process ran successfully with no errors or warnings and does not need to be rerun. If the icon is next to a report process, the report is up-to-date; however, associated tasks may have warnings or errors. If this occurs, you can read the report to determine the cause of the warnings or errors.
Warnings reported
This icon shows that the process ran successfully but that warnings were encountered. Errors reported
This icon shows that the process ran but encountered an error. Out-of-Date
This icon shows that you made design changes, which require that the process be rerun. If this icon is next to a report process, you can rerun the associated task process to create an up-to-date version of the report.
No icon
If there is no icon, this shows that the process was never run.
Running Processes
To run a process, you can do any of the following: Double-click the process
Right-click while positioned over the process, and select Run from the popup menu, as shown in the following figure.
Select the process, and then click the Run toolbar button:
When you run a process, Project Navigator automatically processes your design as follows: Automatically runs lower-level processes
When you run a high-level process, Project Navigator runs associated lower-level processes or sub-processes. For example, if you run Implement Design for your FPGA design, all of the following sub-processes run: Translate, Map, and Place & Route.
Automatically runs preceding processes
When you run a process, Project Navigator runs any preceding processes that are required, thereby "pulling" your design through the design flow. For example, to pull your design through the entire flow, double-click Generate Programming File.
Automatically runs related processes for out-of-date processes
If you run an out-of-date process, Project Navigator runs that process and any related processes required to bring that process up to date. It does not necessarily run all preceding processes. For example if you change your UCF file, the Synthesize process remains up to date, but the Translate process becomes out of date. If you run the Map process, Project Navigator runs Translate but does not run Synthesize.
Note: For more information on running processes, including additional Process menu commands, see Running Processes.
Setting Process Properties
Most processes have a set of properties associated with them. Properties control specific options, which correspond to command line options. When properties are available for a process, you can right-click while positioned over the process and select Properties from the popup menu, as shown in the following figure.
When you select Properties, a Process Properties dialog box appears, with standard properties that you can set. The Process Properties dialog box differs depending on the process you select. For example, the following figure shows the Process Properties dialog box for the Synthesize - XST process.
After you become familiar with the standard properties, you can set additional, advanced properties in the Process Properties dialog box; however, setting these options is not recommended if you are just getting started with using the ISE software. When you enable the advanced properties, both
standard and advanced properties appear in the Process Properties dialog box.
Note: For more information on process properties, see Setting Process Properties. To set command line options using process properties, see Setting Command Line Options using Process Properties.
Using the Workspace
When you open a project source file, open the Language Templates, or run certain processes, such as viewing reports or logs, the corresponding file appears in the Workspace. You can open multiple files at one time. Tabs at the bottom of the Workspace show the names of the open files. Click a tab to select the file to view.
You can undock a file in the Workspace to open it in a standalone window outside of the Project Navigator main window. You can dock or undock the file as needed using the following buttons:
Dock Undock
Using the Transcript Window
The Console tab of the Transcript window shows output messages from the processes you run. When the following icons appear next to a message, you can right-click the message and select Goto Answer Record to open the Xilinx website and show any related Answer Records. If a line number appears as part of the message, you can right-click the message and select Goto Source to open the source file with the appropriate line number highlighted.
Warning Error
Note: The Transcript window also includes the Find in Files tab, Errors tab, and Warnings tab.
Using the Toolbars
The toolbars provide convenient access to frequently used Project Navigator commands. Click once on a toolbar button to execute a command. Depending on which tool you have open in the Workspace, the following toolbars are available:
Standard Toolbar: Always available Editor Toolbar: Always available
Tools Toolbar: This toolbar changes depending on the type of file you are modifying in the Workspace.
To see a short popup description of a toolbar button, hold the mouse pointer over the button for about two seconds. A longer description appears in the status bar at the bottom of the main window.
For Help on a toolbar button, click the Help toolbar button, as shown in the following figure, and then click the toolbar button on which you want Help. For more information on getting Help, see Using Xilinx Help.
Creating a Project
Project Navigator allows you to manage your FPGA and CPLD designs using an ISE™ project, which contains all the files related to your design. First, you must create a project and then add source files. With your project open in Project Navigator, you can view and run processes on all the files in your design. Project Navigator provides a wizard to help you create a new project, as follows.
To Create a Project
1. Select File > New Project.
2. In the New Project Wizard, do the following:
a. In the Project Name field, enter a name for the project.
b. In the Project Location field, enter the directory name or browse to the directory.
c. In the Top-Level Module Type drop-down list, select one of the following top-level design module types:
HDL
Select this option if your top-level design file is a VHDL, Verilog, or ABEL (for CPLDs) file. An HDL Project can include lower-level modules of different file types, such as other HDL files, schematics, and "black boxes," such as IP cores and EDIF files.
Schematic
Select this option if your top-level design file is a schematic file. A schematic project can include lower-level modules of different file types, such as HDL files, other schematics, and "black boxes," such as IP cores and EDIF files. Project Navigator automatically converts any schematic files in your design to structural HDL before implementation; therefore, you must specify a synthesis tool when working with schematic projects, as described in step 5.
EDIF
Select this option if you converted your design to this file type, for example, using a synthesis tool. Using this file type allows you to skip the Project Navigator synthesis process and to start with the implementation processes.
NGC/NGO
Select this option if you converted your design to this file type, for example, using a synthesis tool. Using this file type allows you to skip the Project Navigator synthesis process and start with the implementation processes.
3. Click Next.
4. If you are creating an EDIF or NGC/NGO project, do the following in the File Selection page of the New Project Wizard. If you are creating an HDL or schematic project, skip to the next step.
a. In the Input Design field, enter the name of the input design file, or browse to the file and select it. b. Select Copy Input Design to the Project Directory to copy your file to the project directory. If you
do not select this option, your file is accessed from the remote location.
d. Select Copy Constraint File to the Project Directory to copy your file to the project directory. If you do not select this option, your file is accessed from the remote location.
e. Click Next.
In the Device and Design Flow page of the New Project Wizard, set the following options. These settings affect other project options, such as the types of processes that are available for your design.
Device Family
Note: To target a Spartan-3L™ device, select Spartan -3™ as the family. When creating an EDIF project, the device family information is read from your EDIF project file, and changing the device family is not recommended.
Device
Note: To target a Spartan-3L device, select a device that ends in l, such as xc3s2000l. Package
Speed Grade
Top-Level Module Type This is automatically set. Synthesis Tool
Select one of the following synthesis tools from the Synthesis Tool drop-down list. A partner synthesis tool is only available as an option if the tool was installed on your computer. If a synthesis tool was installed, but it does not appear as an option, set the path to the synthesis tool in the Integrated Tools Options page of the Preferences dialog box.
Note: When creating an EDIF or NGC/NGO project, this option is not applicable. XST (Xilinx® Synthesis Technology)
XST is available with ISE Foundation™ software installations. It supports projects th at include schematic design files and projects that include mixed language source files, such as VHDL and Verilog sources files in the same project.
Synplify and Synplify Pro (from Synplicity®, Inc.)
The Synplify® software does not support projects that include mixed language source files. The Synplify Pro® software supports projects that include mixed language source files, such as VHDL and Verilog sources files in the same project. The Synplify and Synplify Pro software do not support projects that include schematic design files.
LeonardoSpectrum (from Mentor Graphics®, Inc.)
The LeonardoSpectrum™ software supports projects that include schematic design files. It does not support projects that include mixed language source files, such as VHDL and Verilog sources files in the same project.
Precision (from Mentor Graphics®, Inc.)
The Precision® software supports projects that include schematic design files and projects that include mixed language source files, such as VHDL and Verilog sources files in the same project. When you select the synthesis tool, you must also select one of the following HDL languages for your project:
VHDL Verilog
VHDL/Verilog
Note: This is a mixed language flow. If you plan to run behavioral simulation, your simulator must support multiple language simulation.
Simulator
From the Simulator drop-down list, select one of the following simulators: ISE Simulator (Xilinx Simulator)
This simulator allows you to run integrated simulation processes as part of your ISE design flow. ModelSim (from Mentor Graphics®, Inc.)
You can run integrated simulation processes as part of your ISE design flow using any of the following ModelSim® editions: ModelSim Xilinx Edition (MXE), ModelSim MXE Starter, ModelSim PE, or ModelSim SE™.
Note: For more information on ModelSim, including the differences between each edition, see Using the ModelSim Simulator.
Other
Select this option if you do not have ISE Simulator or ModelSim installed or if you want to run simulation outside of Project Navigator. This instructs Project Navigator to disable the integrated simulation processes for your project.
Generated Simulation Language
If you have a single language design, the language you set for your synthesis tool is already set in this field. The language you select determines the language in which to generate simulation netlists. In addition, this setting determines the language in which to write CORE Generator™ IP behavioral models, schematic files, instantiation templates, StateCAD HDL, test benches, and any other files that are generated within the Project Navigator flow.
6. If you are creating an EDIF or NGC/NGO project, skip to step 8. If you are creating an HDL or schematic project, click Next, and optionally, create a new source file for your project.
Note: You can only create one new source file while creating a new project. You can create additional new sources after your project is created.
7. Click Next, and optionally, add existing source files to your project. 8. Click Next to display the Information page of the New Project Wizard. 9. Click Finish to create the project.
Note If you prefer, you can create a project using the New Project dialog box instead of the New Project Wizard, as described above. To use the New Project dialog box, deselect the Use new project wizard option in the ISE General Options page of the Preferences dialog box.
What to Expect
Project Navigator creates the project file, project_name .ise, in the directory you specified. All source files related to the project appear in the Project Navigator Sources in Project window. Project Navigator manages your project based on the project properties (top-level module type, device type, synthesis tool, and language) you selected when you created the project. It organizes all the parts of your design and keeps track of the processes necessary to move the design from design entry through implementation to programming the targeted Xilinx device.
Note: For information on changing project properties, see Changing the Target Device and Design Flow.
What to Do Next
You can perform any of the following:
Create and add source files to your project. Add existing source files to your project. Run processes on your source files.
Using ISE Example Projects
To help familiarize you with the ISE™ software and with FPGA and CPLD designs, a set of example designs is provided with Project Navigator. The examples show different design techniques and source types, such as VHDL, Verilog, ABEL, schematic, or EDIF, and include different constraints and stimulus files.
To Open an Example
1. Select File > Open Example.
2. In the Open Example dialog box, select the Sample Project Name that you want to use.
To help you choose an example project, the Project Description field describes each project. In addition, you can scroll to the right to see additional fields, which provide details about the project. 3. In the Destination Directory field, enter a directory name or browse to the directory.
4. Click OK.
What to Expect
The example project is placed in the directory you specified in the Destination Directory field and is automatically opened in Project Navigator. You can then run processes on the example project and save any changes.
Note: If you modified an example project and want to overwrite it with the original example project, select File > Open Example, select the Sample Project Name, and specify the same Destination Directory you originally used. In the dialog box that appears, select Overwrite the existing project... and click OK.
Creating a Source File
A source file is any file that contains information about a design. Project Navigator provides a wizard to help you create new source files for your project.
What to Do First
Open a project in Project Navigator.
To Create a Source File
1. Select Project > New Source.
Note Alternatively, you can double-click Create New Source in the Processes for Source window. 2. In the New Source dialog box, select the type of source you want to create.
Different source types are available depending on your project properties (top-level module type, device type, synthesis tool, and language). Some source types launch additional tools to help you create the file, as described in Source File Types.
3. Enter a name for the new source file in the File Name field.
Note: Make sure your file name adheres to the file naming conventions. 4. In the Location field, enter the directory name or browse to the directory. 5. Select Add to Project to automatically add this source to the project.
Note: State machines created with State CAD cannot be automatically added to the project. You must add them manually.
6. Click Next.
7. If you are creating a source file that needs to be associated with an existing source file, select the appropriate source file, and click Next. If this does not apply, skip to the next step.
8. In the New Source Information window, read the summary information for the new source, and click Finish.
What to Expect
After you click Finish, the New Source wizard closes. In some cases, a related tool is launched in which you can finish creating your file. After the source file is created, it appears in the Project Navigator Sources in Project window. If you selected Add to Project when creating the source file, the file is automatically added to the project.
Source File Types
The following table shows the source file types that appear in the Project Navigator Sources in Project window. Available source types vary depending on your project properties (top-level module type, device type, synthesis tool, and language). The last column describes what to expect when creating the file with the New Source wizard and, if applicable, includes the tool launched when using the New Source Wizard or when editing the file from Project Navigator.
Note: For a list of all the file types generated by the ISE software, see the "Xilinx Development System Files" appendix in the Development System Reference Guide .
File Type Extension Ico Description New Source Wizard Behavior/To Launched
ABEL Test Vecto .abv Describes input stimulu and expected outputs f logic simulation of ABE design code.
Associates the file with the top-lev module and opens a skeleton te bench file in the text editor you specif in the Editor Options page of th Preferences dialog box.
ABEL-HDL Module
.abl Contains ABEL desig code.
Allows you to specify your pin name and then opens the file in the te editor you specify in the Editor Option page of the Preferences dialog box. Block RA Memory Ma (BMM File) .bmm Used in PowerPC™ an MicroBlaze™ process designs to describe th organization of Block RA memory.
Note Only one BM Module is allowed p project.
Opens the file in the text editor yo specify in the Editor Options page the Preferences dialog box. The CP executable code is automaticall inserted in the configuration file durin design implementation. Chipscope Definition an Connection (CD File) .cdc Contains generi information about th trigger and data ports the ChipScope™ core.
Adds the file to the project. Doubl click the CDC file in the Sources i Project window to run th implementation process and launc the ChipScope Pro™ Core Inserte For details, see the ChipScope Pr Debugging Overview.
Note ChipScope Pro must b installed for this source type to b available. Electronic Dat Interchange Format (EDIF) .edn, .ed .edif, .sedif
Specifies the design netli in an industry standard fil format.
N/A
Must be generated by a third-part design entry tool and added to th project.
as a top-level module, not as a lowe level module. If you are usin hierarchical EDIF files, lower-lev EDIF files are automatically processe during the implementation process. ELF .elf Contains an executabl
CPU code image.
Note Only one ELF file i allowed per project.
N/A
Must be generated by the Data2ME command line tool and added to th project.
Embedded Processor
.xmp Contains predefined logi functions.
Launches the Xilinx Platform Studio i which you can define the embedde processor system portion of yo design. For details, see the Embedde Development Kit Documentation. Implementation
Constraints File also known a User Constraint File (UCF)
.ucf Contains user-specifie logical constraints.
Adds the file to the project. Doubl click the UCF file in the Sources i Project window, or double-click Constraints Entry process in th Processes for Source window to ope the file. For details, see Constraint Entry Methods.
IP (Architectur Wizard)
.xaw Contains predefined logi functions that configur architecture features modules.
Launches one of the Xilin Architecture Wizards in which you ca define your IP. For details, se Working with Architecture Wizard IP . IP (CoreGen) .xco Contains predefined logi
functions.
Launches the Xilinx COR Generator™ software in which yo can define your IP. For details, se Working with CORE Generator IP. Memory Definitio
(MEM File)
.mem Used in Virtex-II Pro Power PC™ an MicroBlaze™ process designs to define th contents of a Read-Onl Memory (ROM).
Note Only one MEM file i allowed per project.
Opens the file in the text editor yo specify in the Editor Options page the Preferences dialog box. The CP executable code is automaticall inserted in the configuration file durin design implementation.
Project .ise Contains the project titl list of files, and informatio for managing the ISE project.
N/A
Schematic .sch Contains a schemati design.
Opens Schematic Editor in the Proje Navigator Workspace in which yo can define your schematic. For detail see the Schematic Overview.
State diagram .dia Contains a state diagra file.
Launches StateCAD in which you ca define your state diagram. For detail
see Working with State Machines. Targeted devic
package, an speed grade
N/A Shows the targete device, package, an speed grade. N/A Test Benc Waveform .tbw Contains a graphic representation of a te bench that can b converted to an HDL te bench or test fixture.
Prompts you to associate the file wit a source and opens the Test Benc Waveform Editor in the Proje Navigator Workspace with the signal populated. For details, see the IS Simulator Help.
Note This file is for use with th Xilinx® Test Bench Waveform Edit only.
Undefined N/A Not recognized by Proje Navigator and n implemented with th design.
N/A
Must be added to the project. User Document .doc, .tx
.wri
Contains user informatio that is not implemente with the project, f example, supportin documentation.
N/A
Must be added to the project.
Verilog Module .v Contains Verilog desig code.
Opens the file in the text editor yo specify in the Editor Options page the Preferences dialog box.
Verilog Te Fixture
.v Defines the stimulus to th ports of an HDL file.
Prompts you to associate the file wit a Verilog source module and the opens a skeleton test bench file in th text editor you specify in the Edit Options page of the Preference dialog box.
VHDL Library .vhd Contains a collection VHDL packages.
Adds a new directory to the vh library directory in the Library View the Sources in Project window. VHDL Module .vhd Contains VHDL desig
code.
Opens the file in the text editor yo specify in the Editor Options page the Preferences dialog box.
VHDL Package .vhd Contains definition macros, sub-routine supplemental type subtypes, constant functions, and other files.
Opens the file in the text editor yo specify in the Editor Options page the Preferences dialog box.
VHDL Test Bench .vhd Defines the stimulus to th ports of an HDL file.
Prompts you to associate the file wit a VHDL source and then opens skeleton test bench file in the te editor you specify in the Editor Option page of the Preferences dialog box.
FPGA Design Flow Overview
The ISE™ design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx® device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow. This section describes what to do during each step. For additional details on each design step, click a box in the following figure.
Design Entry
Create a Project Navigator project and specify your top-level design file as follows: 1. Create a Project Navigator project.
2. Create files and add them to your project, including a user constraints (UCF) file. 3. Add any existing files to your project.
4. Assign constraints such as timing constraints, pin assignments, and area constraints.
Functional Verification
You can verify the functionality of your design at different points in the design flow as follows: Before synthesis, run behavioral simulation (also known as RTL simulation).
Run functional simulation (also known as gate-level simulation) at the following points in the design flow:
After Synthesize (UNISIM library) After Translate (SIMPRIM library)
Design Synthesis
Synthesize your design.
Design Implementation
Implement your design as follows:
1. Implement your design, which includes the following steps: Translate
Map
Place and Route
2. Review reports generated by the Implement Design process, such as the Map Report or Place & Route Report, and change any of the following to improve your design:
Process properties Constraints
Source files
3. Synthesize and implement your design again until design requirements are met.
Timing Verification
You can verify the timing of your design at different points in the design flow as follows: Run static timing analysis at the following points in the design flow:
After Map
After Place & Route
Run timing simulation at the following points in the design flow: After Map (for a partial timing analysis of CLB and IOB delays)
After Place and Route (for full timing analysis of block and net delays)
Xilinx Device Programming
Program your Xilinx device as follows:
1. Create a programming file (BIT) to program your FPGA.
2. Generate a PROM, ACE, or JTAG file for debugging or to download to your device. 3. Use iMPACT to program the device with a programming cable.
FPGA Basic Flow
With designs of low to moderate complexity, you can process your design using the ISE™ Basic Flow as follows:
1. Create a Project Navigator project and specify your top-level design file as follows: a. Create a Project Navigator project.
b. Create files and add them to your project, including a user constraints (UCF) file. c. Add any existing files to your project.
d. Edit the design files to specify design functionality.
e. Optionally, use the Language Templates to assist in coding of the design.
f. Edit the design test bench or waveform files to drive stimulus for testing the design files. Optionally, do the following:
Use the Test Bench Waveform Editor to specify stimulus for the design. Use the Language Templates to assist in coding of the test bench.
g. Assign constraints such as timing constraints, pin assignments, and area constraints.
Note: If you are working with an EDIF or NGC/NGO top-level source file and performed behavioral simulation outside of Project Navigator, skip ahead to step 5.
2. Run behavioral simulation (also known as RTL simulation). 3. Repeat steps 1 and 2 until desired functionality is achieved. 4. Synthesize your design.
5. Implement your design as follows:
a. Run the Implement Design process, which automatically runs the following processes: Translate
Map
Place and Route
b. Review reports generated by the Implement Design process, such as the Map Report or the Place and Route Report, and change any of the following to improve your design:
Process properties Constraints
Source files
c. Modify the design as necessary, simulate, synthesize, and implement your design again until design requirements are met.
3. Run timing simulation to verify end functionality and timing of the design. 4. Program your Xilinx® device as follows:
c. Create a programming file (BIT) to program your FPGA.
d. Generate a PROM, ACE, or JTAG file for debugging or to download to your device. e. Use iMPACT to program the device with a programming cable.
FPGA Advanced Flows
In some cases, running your design through the FPGA Basic Flow is not sufficient. For example, if you have strict design requirements, such as dense area constraints, or aggressive timing requirements, or if you are designing for a large FPGA and splitting up the work among several engineers, you may want to use one of the following Advanced Flows.
FPGA Advanced Flow
1. Create a Project Navigator project and specify your top-level design file as follows: a. Create a Project Navigator project.
b. Create files and add them to your project, including a user constraints (UCF) file. c. Add any existing files to your project.
d. Edit the design files to specify design functionality.
e. Optionally, use the Language Templates to assist in coding of the design.
f. Edit the design test bench or waveform files to drive stimulus for testing the design files. Optionally, do the following:
Use the Test Bench Waveform Editor to specify stimulus for the design. Use the Language Templates to assist in coding of the test bench.
g. Assign constraints, such as timing constraints, pin assignments, and area constraints.
Note: If you are working with an EDIF or NGC/NGO top-level source file and performed behavioral simulation outside of Project Navigator, skip ahead to step 6.
2. Run behavioral simulation (also known as RTL simulation). 3. Repeat steps 1 and 2 until desired functionality is achieved. 4. Synthesize your design as follows:
a. If you do not want to use the default settings, set the synthesis properties. b. Run the Synthesize process.
5. Optionally, run post-synthesis functional simulation. 6. Implement your design as follows:
a. If you do not want to use the default settings, set the implementation properties. b. Translate your design.
c. Optionally, run post-Translate functional simulation. d. Map your design. Optionally, do the following:
Run static timing analysis (for a partial timing analysis of logic delays without routing).
Run post-Map partial timing simulation (for a partial timing analysis of logic delays without routing) e. Place and Route your design. Optionally, do the following:
Run static timing analysis.
Run back annotation for the following: Timing information
Pin locations
f. Review reports generated by the Implement Design process, such as the Map Report or the Place and Route Report, and change any of the following to improve your design:
Process properties Constraints
Source files
7. Optionally, consider the following advanced implementation strategies to improve design performance:
Use the Floorplanner at any of the following points in the design flow to manually place logic: Before Map
After Map but before Place and Route After Place and Route
Set the Perform Timing Driven Packing and Placement Map Property.
View the placed and routed design in FPGA Editor and manually route sections of the design.
Note: Manually routing is not recommended unless absolutely necessary. Set multiple place and route passes for your design.
8. Modify the design as necessary, simulate, synthesize, and implement your design, as appropriate, until design requirements are met.
9. Run timing simulation to verify end functionality and timing of the design. 10. Program your Xilinx® device as follows:
a. Create a programming file (BIT) to program your FPGA.
b. Generate a PROM, ACE, or JTAG file for debugging or to download to your device. c. Use iMPACT to program the device with a programming cable.
Optionally, run in-circuit verification.
Additional Advanced Flows
Following are additional advanced flows designed to help you meet your design requirements.
Advanced Flow More Information
Incremental Design Flow See the following:
Using Incremental Design
Development System Reference Guide : See th "Incremental Design" chapter.
Modular Design Flow Development System Reference Guide : See th "Modular Design" chapter.
Partial Reconfiguration Flow Development System Reference Guide : See th "Partial Reconfiguration" chapter.
Guided Synthesis and Implementation Flow Development System Reference Guide : See th following sections:
" Guided Mapping" section in the "MAP" chapter "Guided PAR" section in the "PAR" chapter
Multi-Cycle Paths Flow Synthesis and Verification Design Guide : See th "Using Pipelining" section in the "Coding Style for FPGA Devices" chapter.
Design Entry Overview
Design entry is the first step in the ISE™ design flow. During design entry, you create your source files based on your design objectives. You can create your top-level design file by using a Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or by using a schematic. You specify your top-level module type when you create your project as described in Creating a Project. You can use multiple formats for the lower-level source files in your design. Different source types are available, depending on your project properties (top-level module type, device type, synthesis tool, and language). You can create these source files in Project Navigator, as described in Creating a Source File. Some source types launch additional tools to help you create the file, as described in Source File Types.
For information on creating efficient designs, such as how to set up your design hierarchy and good coding practices, refer to the following Xilinx® documentation:
Synthesis and Verification Design Guide , which includes the following chapters: "Understanding High-Density Design Flow"
"General HDL Coding Styles" "Coding Styles for FPGA Devices"
XST User Guide , which includes HDL coding techniques.
Development System Reference Guide , which contains information about the command line software programs in the Xilinx Development System.
Application Notes, which discuss technical details.
Note: If you converted your design to an EDIF or NGC/NGO file, for example, using a synthesis tool, you can skip the design entry processes and start with the implementation process.
HDL Overview
You can use a hardware description language (HDL), such as VHDL, Verilog, or ABEL (for CPLDs), for your top-level or lower-level design files. HDL files describe the behavior and structure of system and circuit designs. Using HDLs to design high-density devices allows you to do the following:
Use a top-down approach
You can use HDLs to create complex designs that require many designers to work together. After an overall plan is determined, each designer works on a separate section of the design.
Run functional simulation early in the design cycle
You can verify your design functionality early in the flow by simulating the HDL description. Testing your design decisions at the register transfer level (RTL) or gate level before the design is implemented allows you to make changes early in the design process.
Use a synthesis engine to translate your design to gates
Synthesis decreases design time by eliminating the need to define every gate. Synthesis to gates reduces the number of errors that may occur during a manual translation of the hardware description to a schematic design. Also, the synthesis tool can apply automation, such as machine encoding styles or automatic I/O insertion during optimization, resulting in greater efficiency.
Retarget your code to different architectures
You can use the same HDL design for new architectures with a minimum of recoding. This works especially well if you inferred, rather than instantiated, components. For details, see Instantiation and Inference.
Additional details on the advantages of using HDLs are available in the Synthesis and Verification Design Guide . See the following chapters to help you with your design:
"Introduction," which includes an overview of HDLs.
"Understanding High-Density Design Flow," which discusses high-density designing, designing with hierarchy, and design size versus performance.
Note: You must understand how to properly create hierarchy in your HDL file, as opposed to creating a "flat" design.
"General HDL Coding Styles," which discusses general coding styles.
"Coding Styles for FPGA Devices," which discusses architecture-specific coding styles.
Review these chapters and consult any of the many HDL textbooks available. In addition, you can enroll in any of the Xilinx® training classes available from the Xilinx website. Click Education to view the available classes and to sign up.
Schematic Overview
Using schematics for your top-level or lower-level design files allows you to have a visual representation of your design. You can use schematics for your top-level design, your lower-level design files, or both, as follows:
Top-level schematic
You can use a schematic as your top-level design and create the lower-level modules using any of the following source types: HDL files, state diagrams, CORE Generator™ cores, Architecture Wizard IP, or schematic files. To instantiate a lower-level module in your top-level design, you must create a schematic symbol from the lower-level module, and instantiate the schematic symbol. For more information, see Creating a Top-Level Schematic.
Note: You do not need to create schematic symbols for CORE Generator cores or for Xilinx® Unified Library symbols. The CORE Generator software automatically generates schematic symbols, and library symbols are predefined.
Lower-level schematic
You can use schematics to define the lower-level modules of your design. If the top-level design file is a schematic, you must create a schematic symbol from the lower-level schematic, and then instantiate the symbol in the top-level schematic. If the top-level design file is an HDL file, you must create an HDL instantiation template from the schematic, and then instantiate the template in the top-level HDL file. For more information, see Creating a Lower-Level Schematic.
Entire design composed of schematics
You can create your entire design, including top-level and lower-level modules, using schematics. The design can be either flat or hierarchical. You must create schematic symbols from the lower-level schematics, and then instantiate them in the top-lower-level schematic design. For more information, see Creating a Top-Level Schematic and Creating a Lower-Level Schematic.
All schematics are ultimately converted to either VHDL or Verilog structural netlists before being passed on to your synthesis tool during the Synthesize process.
Note: For more information on working with schematics in Project Navigator, see the Schematic and Symbol Editors Help. For information on Xilinx Unified Library symbols, see the Components Overview and the Libraries Guides available from the ISE™ Software Manuals collection. For information on cores, see the Intellectual Property and Cores Overview .
Schematic Design Methods
When using a schematic as your top-level design, use either of the following methods to describe the lower-level modules.
Top-Down Schematic Design Method
Using this method, you create a top-level block diagram description of the design using a schematic. Then, you "push down" into each symbol and define its behavior using an HDL or schematic file. To use this method, do the following:
1. Create your top-level schematic as described in Creating a Project, selecting Schematic as your top-level module type.
2. To create individual top-level blocks for the design, use the Symbol Wizard, as described in Creating a Symbol. When using the Symbol Wizard, ensure that you use the following default settings:
Pin Name Source: Specify Manually Shape: Rectangle
Note: The Symbol Wizard allows you to add input, output, or bidirectional pins. You can create bus (multi-signal) pins using parentheses, for example: inbus(7:0).
After you click Finish, the symbol is added to the local symbol library for the project and it opens in the Project Navigator Workspace. If needed, you can edit the symbol in the Workspace.
3. In the Project Navigator Workspace, click the tab for your top-level schematic.
4. Instantiate your new symbol in the top-level schematic, as described in Adding a Symbol Instance. 5. Right-click the symbol you added, and select Symbol > Push into Symbol.
6. You are prompted to create one of the following template file types:
Schematic
The schematic contains I/O markers that correspond to the pins in the block symbol you created. Build the schematic by adding symbols as described in Adding a Symbol Instance. You can use Xilinx® Unified Library symbols or symbols that you create.
VHDL or Verilog
The template contains the HDL port descriptions that correspond to the pins in the block symbol you created. You can then add the behavior of the module. The ISE Language Templates provide a convenient method for you to insert pre-built language and functional code samples into your HDL file. For details, see Working with Language Templates .
Note: The next time you use the Push into Symbol command, the HDL or schematic file opens in the Project Navigator Workspace.
