MOS Field-Effect Transistors (MOSFETs)

MOS Field-Effect

Transistors (MOSFETs)

MOSFET – Metal Oxide Semiconductor Field Effect Transistor

• Requer menor área no circuito integrado

• Processo de fabricação mais simples

• Consumo de energia menor

É o transistor mais utilizado, principalmente em circuitos integrados BJT – Bipolar Junction Transistor

Tipos de MOSFETS:

• JFET – Junction FET

• Depletion - Depleção

• Enhancement - Crescimento

Circuitos Integrados VLSI – Very Large Scale Integration

200.000.000 transistores em um único circuito integrado

Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross- section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (t_ox) is in the range of 2 to 50 nm.

nm 50 a

= 2 t ox

m 3 a 1

0 . μ

= L

m 100 a 2

0 . μ

=

W

„ Operação do transistor sem tensão no gate

Resistência do canal = 10

Ω

Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

„ Criação do canal

V

– tensão de limiar ou threshold voltage

V

= 0,5 a 1 V

Figure 4.3 An NMOS transistor with v_GS > V_tand with a small v_DSapplied. The device acts as a resistance whose value is determined by v_GS. Specifically, the channel conductance is proportional to v_GS – V_t’ and thus i_D is proportional to (v_GS – V_t) v_DS. Note that the depletion region is not shown (for simplicity).

„ Operação com baixa tensão v _DS

Figure 4.4 The i_D–v_DS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, v_DS, is kept small. The device operates as a linear resistor whose value is controlled by v_GS.

„ Operação com baixa tensão v _DS

v

– V

- tensão efetiva de gate Qual o valor da resistência entre dreno

e fonte em cada reta?

Figure 4.5 Operation of the enhancement NMOS transistor as v_DS is increased. The induced channel acquires a tapered shape, and its resistance increases as v_DS is increased. Here, v_GSis kept constant at a value > V_t.

Figure 4.6 The drain current i_Dversus the drain-to-source voltage v_DSfor an enhancement-type NMOS transistor operated with v_GS > V_t.

Figure 4.7 Increasing v_DS causes the channel to acquire a tapered shape. Eventually, as v_DS

reaches v_GS– V_t’the channel is pinched off at the drain end. Increasing v_DSabove v_GS – V_t has little effect (theoretically, no effect) on the channel’s shape.

Figure 4.8 Derivation of the i_D–v_DS characteristic of the NMOS transistor.

ox ox t ox

C ₌ ε m

ox = 3 . 45 × 10 ^{− 11} F / ε

t ox

Capacitância por unidade de área na região do canal Permissividade do óxido de silício

Espessura da camada de óxido de silício A capacitância da faixa de largura dx é igual a C _ox Wdx

A quantidade de carga no canal, nesta região é igual a capacitância desta faixa multiplicada pela tensão efetiva no canal neste ponto [ v _GS − v ( x ) − V _t ]

] )

( )[

( _{GS t}

ox Wdx v v x V C

dq = − − −

O campo elétrico produzido pela tensão v

no ponto x é igual a:

dx x x dv

E ( )

)

( = −

dx x x dv

dt E

dx n n ( )

)

( μ

μ =

−

=

dx x V dv

x v v

W dt C

dx dx dq dt

i dq _{n ox GS t} ( )

] )

(

[ − −

−

=

=

= μ

dx x V dv

x v v

W C i

i _{D n ox GS t} ( )

] )

(

[ − −

=

−

= μ

) ( ] )

(

[ v v x V dv x

W C dx

i _D = μ _{n ox GS} − − _t

O campo elétrico E(x) faz com que a carga dq se mova em direção ao dreno com uma velocidade

A corrente de drift resultante pode ser calculada como

A corrente de dreno é então

Rearranjando esta equação

] )

)[(

)(

( ²

2 1 DS DS

t GS ox

n

D v V v v

L C W

i = μ − −

∫

∫ ^{= v}

n ox GS ^{− −} t L

D dx C W v v x V dv x

i

0 0

) ( ] )

( μ [

Integrando os dois lados desta equação de x = 0 até x = L correspondendo a v(0) = 0 até v(L) = v

Temos a equação do FET na região de triodo

Para a região de saturação tem-se v _DS = v _GS − V _t

2

2

1 ( _{n ox} )( )( _{GS t} )

D v V

L C W

i = μ −

ox n

n C

K ^' = μ Parâmetro de transcondutância do processo

Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant.

Símbolos do MOSFET

Figure 4.11 (a) An n-channel enhancement-type MOSFET with v_GSand v_DS applied and with the normal directions of current flow indicated. (b) The i_D–v_DS characteristics for a device with k’_n(W/L) = 1.0 mA/V².

Carracterística i

x v

] )

)[(

'

(

2 1

t GS n

D

v V v v

L K W

i = − −

2

2

1 _n ^' ( )( _{GS t} )

D v V

L K W

i = −

DS t

GS n

D v V v

L K W

i = ^' ( )( − )

Característica i

x v

] )

)[(

'

(

2 1

t GS n

D

v V v v

L K W

i = − −

2

2

1

( )(

)

D

v V

L K W

i = −

DS t GS n

D

v V v

L K W

i =

( )( − )

OV n

t GS n

DS

V

L K W V

L V K W r

'

'

( )

1

1 =

−

=

t GS

OV

V V

V = − Gate to source overdrive voltage

Figure 4.12 The i_D–v_GScharacteristic for an enhancement-type NMOS transistor in saturation (V_t = 1 V, k’_nW/L = 1.0 mA/V²).

2

2

1 _n ^' ( )( _{GS t} )

D v V

L K W

i = −

Região de saturação

Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.

Circuito equivalente para grandes sinais do MOSFET

Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode region and in the saturation region.

Figure 4.15 Increasing v_DS beyond v_DSsatcauses the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL).

Modulação do Comprimento do Canal

2

2

1 _n ^' ( )( _{GS t} )

D v V

L K W

i = −

Figure 4.16 Effect of v_DSon i_Din the saturation region. The MOSFET parameter V_A depends on the process technology and, for a given process, is proportional to the channel length L.

Tensão de Early (J. M. Early) V

2

2

1

( )(

)

D

v V

L K W

I = −

) (

) )(

( )

(

t A GS n

A DS D

A DS D D

D

v

V V L v

K W V v

I V v

I I

i 1

2 1 1

1 + 1 = −

+

= +

=

2

2

1

( )(

)

A D

o A

V L v

K W

V I

r V

−

=

=

Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance r_o. The output resistance models the linear dependence of i_D on v_DSand is given by Eq. (4.22).

2

2

1

( )(

)

A D

o A

V L v

K W

V I

r V

−

=

=

Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that v_GS and v_DS are negative and i_D flows out of the drain terminal.

Equações do FET canal P

Região de Triodo:

Região de Saturação:

] )

)[(

'

(

2 1

t GS p

D

v V v v

L K W

i = − −

DS t

GS p

D

v V v

L K W

i =

( )( − )

t GS

V

v ≤ v

≤ v

− V

t GS

DS

v V

v ≥ −

t GS

V

v ≤

Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region and in the saturation region.

Figure E4.8

V

= -1 V

K

= 60 μA/V

W/L = 10

Exercício 4.8

Body Effect

Em um circuito integrado do tipo NMOS o substrato é conectado à tensão mais negativa do circuito, impedindo assim a condução do diodo de substrato para fonte.

Esta polarização reversa (V

) tem como efeito, a redução da profundidade do canal, afetando portanto a corrente de dreno.

O efeito de V

é geralmente representado como uma alteração na

tensão de limiar. V

cresce com o aumento de V

.

Efeitos da Temperatura

V

– cai 2 mV para cada 1

C de aumento da temperatura.

K’ – diminui com o aumento da temperatura.

A corrente de dreno diminui com o aumento da temperatura.

Breakdown (Avalanche)

1 – A junção pn entre dreno e substrato entra em avalanche para tensões entre 20 V e 150 V.

2 – Quando a tensão entre gate e fonte atinge 30 V, rompe-se a rigidez

dielétrica do óxido de silício na região canal, danificando definitivamente

o dispositivo. Isto pode ocorrer mesmo com eletricidade estática.

Table 4.1

Figure 4.20 Circuit for Example 4.2.

Faça I

= 0,4 mA e V

= 0,5V Dados:

V

= 0,7 V

μ

C

= 100 μA/V

L = 1 µm

W = 32 µm

Exemplo 4.2

Figure 4.21 Circuit for Example 4.3.

Faça I

= 80 µA. Calcule R e V

. Dados:

V

= 0,6 V

μ

C

= 200 μA/V

L = 0,8 µm

W = 4 µm

Exemplo 4.3

Figure E4.12

Como continuação do exemplo anterior, com R = 25 KΩ, I

= 80 µA em Q1.

Calcule a corrente de dreno em Q

. Dados:

V

= 0,6 V

μ

C

= 200 μA/V

L = 0,8 µm

W = 4 µm

Exercício 4.12

Figure 4.22 Circuit for Example 4.4.

Faça V

= 0,1V e projete o circuito.

Qual a resistência entre dreno e source neste ponto de operação?

Dados:

V

= 1 V

K’

(W/L) = 1 mA/V

Exemplo 4.4

Figure 4.23 (a)Circuit for Example 4.5. (b) The circuit with some of the analysis details shown.

Analise o circuito.

Dados:

V

= 1 V

K’

(W/L) = 1 mA/V

Exemplo 4.5

Figure 4.24 Circuit for Example 4.6.

Projete o circuito para que o transistor opere na região de saturação com V

= 3 V e I

= 0,5 mA.

Qual a máxima resistência R

que ainda mantém o transistor na região de saturação?

Dados:

V

= -1 V

K’

(W/L) = 1 mA/V

Exemplo 4.6

Figure 4.25 Circuits for Example 4.7.

Calcule i

, i

e v

para:

v

= 0 V, 2,5 V e -2,5 V.

Dados:

- V

= V

= 1 V

K’

(W/L) = K’

(W/L) =1 mA/V

Exemplo 4.7

Figure E4.16

Exercício 4.16

Calcule i

, i

e v

para:

v

= 0 V, 2,5 V e -2,5 V.

Dados:

- V

= V

= 1 V

K’

(W/L) = K’

(W/L) =1 mA/V

Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of the amplifier in (a).

D DS D

D DD

v

R R

i = V − 1 Reta de carga

Característica de

Transferência

Figure 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q.

Característica de Transferência

VIQ vi v dto

A dv

=

=

Ganho do Amplificador

Figure 4.27 Two load lines and corresponding bias points. Bias point Q₁does not leave sufficient room for positive signal swing at the drain (too close to V_DD). Bias point Q₂is too close to the boundary of the triode region and might not allow for sufficient negative signal swing.

Figure 4.28 Example 4.8.

Figure 4.28 (Continued)

Figure 4.29 The use of fixed bias (constant V_GS) can result in a large variability in the value of I_D. Devices 1 and 2 represent extremes among units of the same type.

2

2

1

(

)

D

V V

L C W

I = μ −

Polarização do MOSFET fixando a tensão V

V

, C

, W e L variam de dispositivo para dispositivo da mesma família

V

, e μ

variam com a temperatura.

Figure 4.30 Biasing using a fixed voltage at the gate, V_G, and a resistance in the source lead, R_S: (a) basic arrangement; (b) reduced variability in I_D; (c) practical implementation using a single supply; (d) coupling of a signal source to the gate using a capacitor C_C1; (e) practical implementation using two

S GS

D G

R

V

I V −

=

Polarização com V

constante e resistor de fonte

S GS D SS

R

V

I = V −

Figure 4.31 Circuit for Example 4.9.

Projete o circuito para I

= 0,5 mA

Dados:

V

= 15 V V

= 1 V

K’

(W/L) = 1 mA/V

Qual a variação de I

quando o MOSFET é trocado por outro com V

= 1,5 V?

Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, R_G.

Polarização com resistor de realimentação entre dreno e gate

D GS D DD

R V

I V −

=

Figure 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the constant-current source I using a current mirror.

R V I

= V

+ V

−

2 2

2

2

1

(

)

D

V V

L K W

I ⎟ −

⎠

⎜ ⎞

⎝

= ⎛

2 1

1

2

1

(

)

D

V V

L K W

I ⎟ −

⎠

⎜ ⎞

⎝

= ⎛

Polarização com fonte de corrente constante

1 2 2

) / (

) / (

L W

L I W

I

=

Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

2

2

1

(

)

D

V V

L K W

I = − V

≥ V

− V

gs GS

GS

V v

v = −

2

2

1

(

)

D

V v V

L K W

i = + −

2 2

2 1 2

1

D

v

L K W v

V L V

K W V

L V K W

i =

( − ) +

( − ) +

Análise C.C.

Introduzindo agora o sinal:

corrente c.c. de polarização: I

amplificação distorção

2

2

1

t GS

n

v

L K W v

V L V

K

W ( − ) >>

)

(

gs

V V

v << 2 − v

<< 2 V

Condição de pequenos sinais:

d D

D

I i

i ≈ +

gs m gs

t GS n

d

V V v g v

L K W

i =

( − ) =

OV n

t GS n

m

V

L K W V

L V K W

g =

( − ) =

ganho de transcondutância

Desprezando o termo de distorção:

Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier.

VGS vGS GS m d

v g i

∂

= ∂

Interpretação gráfica do ganho de transcondutância

Figure 4.36 Total instantaneous voltages v_GSand v_D for the circuit in Fig. 4.34.

D D DD

D

V R i

v = −

)

(

D DD

D

V R I i

v = − +

gs D m d

D

d

R i g R v

v = − = −

D gs m

v d

g R

v

A = v = −

Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of i_Don v_DS in saturation (the channel-length modulation effect); and (b) including the effect of channel-length modulation, modeled by output resistance r_o = |V_A| /I_D.

Modelo de pequenos sinais do MOSFET

gs m

d

g v

i =

t GS t D

GS n

m

V V

V I L V

K W

g = − = 2 −

)

'

(

D o

I

r = | V |

Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.

Analise o circuito e determine o ganho, resistência de entrada e máxima excursão do sinal de saída.

Dados:

V

= 1,5 V

K’

(W/L) = 0,25 mA/V

V

= 50V

Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, r_ohas been omitted but can be added between D and S in the T model of (d).

Modelo T

Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance r_o. (b) An alternative representation of the T model.

Modelo T incluindo a resistência de saída

Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to the body.

Modelamento do Efeito Corpo (“Body”)

. . const vDS

const vGS

BS mb

v

g i

=

∂

= ∂ Transcondutância do corpo

Table 4.2

Modelos de Pequenos Sinais

Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier configurations.

Amplificadores com MOSFET de estágio único

Polarização utilizada nos exemplos:

Figure E4.30

Determine V

, V

, V

, V

. Calcule g

e r

.

Dados:

V

= 1,5 V

K’

(W/L) = 1 mA/V

V

= 50V

Table 4.3

Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the amplifier for small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with the MOSFET model implicitly utilized.

Amplificador fonte comum

Análise direta no circuito

Figure 4.44 (a)Common-source amplifier with a resistance R_Sin the source lead. (b) Small-signal equivalent circuit with r_oneglected.

Amplificador Fonte comum

com resistor de fonte

Figure 4.45 (a)A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit of the amplifier in (a). (c) The common-gate amplifier fed with a current-signal input.

Amplificador gate comum

(c) The common-gate amplifier fed with a current-signal input.

Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model.

Amplificador dreno comum

(c) Small-signal analysis performed directly on the circuit.

(d) Circuit for determining the output resistance Rout of the source follower.

Table 4.4

Amp. fonte comum

Amp. fonte comum com resistor de fonte

Table 4.4 (Continued)

Amp. gate comum

Amp. dreno comum

Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the case in which the source is connected to the substrate (body). (c) The equivalent circuit model of (b) with C_db neglected (to simplify analysis).

Figure 4.48 Determining the short-circuit current gain I_o /I_i.

Table 4.5

Figure 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response of the amplifier in (a) delineating the three frequency bands of interest.

Figure 4.50 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit;

(b) the circuit of (a) simplified at the input and the output;

Figure 4.50 (Continued) (c) the equivalent circuit with C_gd replaced at the input side with the equivalent capacitance C_eq; (d) the frequency response plot, which is that of a low-pass single-time-constant circuit.

Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, r_o is neglected.

Figure 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break frequencies are sufficiently separated for their effects to appear distinct.

Figure 4.53 The CMOS inverter.

Figure 4.54 Operation of the CMOS inverter when v_Iis high: (a) circuit with v_I = V_DD (logic-1 level, or V_OH);

(b) graphical construction to determine the operating point; (c) equivalent circuit.

Figure 4.55 Operation of the CMOS inverter when v_I is low: (a) circuit with v_I = 0 V (logic-0 level, or V_OL);

(b)graphical construction to determine the operating point; (c) equivalent circuit.

Figure 4.56 The voltage transfer characteristic of the CMOS inverter.

Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through Q_N; (d) equivalent circuit during the capacitor discharge.

Figure 4.58 The current in the CMOS inverter versus the input voltage.

Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the case the substrate (B) is connected to the source (S).

Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which V_t= –4 V and k^¢_n(W/L) = 2 mA/V²: (a) transistor with current and voltage polarities indicated; (b) the i_D–v_DS

characteristics; (c) the i_D–v_GS characteristic in saturation.

Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the triode and the saturation regions. The case shown is for operation in the enhancement mode (v_GS is positive).

Figure 4.62 Sketches of the i_D–v_GScharacteristics for MOSFETs of enhancement and depletion types, of both polarities (operating in saturation). Note that the characteristic curves intersect the v_GS axis at V_t. Also note that for generality somewhat different values of |V_t| are shown for n-channel and p-channel devices.

Figure E4.51

Figure E4.52

Figure 4.63 Capture schematic of the CS amplifier in Example 4.14.

Figure 4.64 Frequency response of the CS amplifier in Example 4.14 with C_S = 10 mF and C_S = 0 (i.e., C_S removed).

Figure P4.18

Figure P4.33

Figure P4.36

Figure P4.37

Figure P4.38

Figure P4.41

Figure P4.42

Figure P4.43

Figure P4.44

Figure P4.45

Figure P4.46

Figure P4.47

Figure P4.48

Figure P4.54

Figure P4.61

Figure P4.66

Figure P4.74

Figure P4.75

Figure P4.77

Figure P4.86

Figure P4.87

Figure P4.88

Figure P4.97

Figure P4.99

Figure P4.101

Figure P4.104

Figure P4.117

Figure P4.120

Figure P4.121

Figure P4.123