MODELING, SIMULATION AND FPGA IMPLEMENTATION OF FULL BRIDGE INVERTER

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MODELING, SIMULATION AND FPGA

IMPLEMENTATION OF FULL BRIDGE INVERTER

1

Payal Gupta,

2

Honey Singh,

3

Sonali Singh,

4

Rhea Nath,

5

Sandeep Gupta

1,2,3,4

UG,

Department of Instrumentation and Control Engineering,

5

Assit. Prof. Department of Electronics and Communication Engineering,

BIT Group of Institutions, Meerut, UP (India

)

ABSTRACT

This paper deals with studying the basic theory of a single phase Inverter, its Simulink model and implementation using FPGA. The paper will be commenced by a basic understanding of the circuitry of the Inverter,developing VHDL code to generate the gate pulses for the switches of inverter and implementation this VHDL code on FPGA board.The modelling and simulation are done in MATLAB/SimPowersystem and VHDL code is written in Xilinx software.After this experimental set up is prepared to verify the simulation results obtained by MATLAB model.

Keywords: Single Phase Inverter, FPGA, VHDL, MATLAB/Simpowerelectronics

I. INTRODUCTION

An inverter is basically a device that converts electrical energy of DC form into that of AC. The purpose of DC-AC inverter is to take DC power from a battery source and converts it to DC-AC. For example the household inverter receives DC supply from 12V or 24 V batteries and then inverter converts it to 240V AC with a desirable frequency of 50Hz or 60Hz. These DC-AC inverters have been widely used for industrial applications such as uninterruptible power supply (UPS), AC motor drives. Recently, the inverters are also playing an important role in various renewable energy applications as these are used for grid connection of Wind Energy System or Photovoltaic System. In addition to this, the control strategies used in the inverters are also similar to those in DC-DC converters. Both current-mode control and voltage-mode control are employed in practical applications.

The DC-AC inverters usually operate on Pulse Width Modulation (PWM) technique. The PWM is a very advance and useful technique in which width of the Gate pulses are controlled by various mechanisms. PWM inverter is used to keep the output voltage of the inverter at the rated voltage (depending on the user's choice) irrespective of the output load .

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The complexity of the circuit will increase as the number of gates increase. An FPGA is under your complete control, this means that you can design, program, and make changes to your circuit whenever you wish.

II.INVERTER

A device that converts dc power into ac power at desired output voltage and frequency is called an inverter. The dc power input to the inverter is obtained from an existing power supply network or from a rotating alternator a rectifier or a battery, fuel cell, photovoltaic array or magneto hydrodynamic generator. From the viewpoint of connections of semiconductor devices, inverters are classified as Bridge inverters, Series inverters, and Parallel inverters. In this paper we are going to analysis the single phase full wave inverter.

2.1 Single Phase Full wave Bridge Inverter:

It consists of two arms with a two semiconductor switches on

both arms with antiparallel freewheeling diodes for discharging the reverse current. In case of resistive-inductive load, the reverse load current flow through these diodes. These diodes provide an alternate path to inductive current which continue so flow during the Turn OFF condition.

2.2 Working Principle:

The switches are Q1, Q2, Q3 and Q4. The switches in each branch is operated

alternatively so that they are not in same mode (ON /OFF) simultaneously .In practice they are both OFF for short perod of time called blanking time ,to avoid short circuiting . The switches Q1 and Q2 or Q3 and Q4 should operate in a pair to get the output. These bridges legs are switched such that the output voltage is shifted from one to another and hence the change in polarity occurs in voltage waveform.

Fig.1 Single phase full wave Bridge Inverter Fig.2 Gate pulses for switches and output voltage

The individual control signal for the switches needs to be provided across the gate (base) and source (or emitter) terminals of the particular switch. The gate control signals are low voltage signals referred to the source (emitter) terminal of the switch. For n-channel IGBT and MOSFET switches, when gate to source voltage is more than threshold voltage for turn-on, the switch turns on and when it is less than threshold voltage the switch turns off. The threshold voltage is generally of the order of +5 volts but for quicker switching the turn-on gate voltage magnitude is kept around +15 volts where as turn-off gate voltage is zero or little negative (around –5 volts).

III. PULSE WIDTH MODULATION (PWM)

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the generation of both reference and carrier signals that are feed into the comparator and based on some logical output, the final output is generated. The reference signal is the desired signal output maybe sinusoidal or square wave, while the carrier signal is either a saw tooth or triangular wave at a frequency significantly greater than the reference. There are various types of PWM techniques and so we get different output and the choice of the inverter depends on cost, noise and efficiency.

3.1 Single Pulse Width Modulation:

In this modulation there is an only one output pulse per half cycle.

The output is changed by varying the width of the pulses. The gating signals are generated by comparing a rectangular reference with a triangular reference. The frequency of the two signals is nearly equal.

Fig.3 Single Pulse Width Modulation

IV. FPGA IMPLEMENTATION

The PWM frequency of the modulating signal is 50 KHz, this value calculated by experiment.Here we used Mission 10x-Unified Learning Kit R3.0 which includeSpartan-6 FPGA XC6SLX25T FPGA.

4.1 FPGA Design Flow

:

Fig.4 shows the sequence of steps followed when implementing PWM Generator

design on FPGA. These steps are discussed here as:

Fig. 4 FPGA Design Flow

4.2 Design Entity:

This is the first step of implementing a design on FPGA. In this step the VHDL (Very

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Fig.5 (a) New Project window

Fig.5(b) Project Summary

4.2 Behavioral Simulation:

The next step is behavioral simulation. This step verifies whether the design

entered is functionally correct or not. This simulation is called RTL simulation. For this simulation VHDL Test bench was written for PWM Generator architecture and simulation was seen in Xilinx ISE 12.1 Simulator. After it is verified it is functionally correct we move onto next step.

4.3 Design Synthesis:

The VHDL code of PWM Generator is then synthesized using Xilinx XST which is a

part of Xilinx ISE software. There is an option of Synthesis in process tab of Xilinx ISE which performs the operation of synthesis .The synthesis process is used for optimizing the design architecture selected. The resulting netlist is saved to an NGC file. After design synthesis, synthesis report is generated which gives information about how many logic blocks are used and what is the device utilization of the design architecture synthesized. Synthesis basically maps the behavioral design to gate level design.

4.4 Design Implementation:

After design synthesis, design implementation is done which comprises of

following three steps (a) Translate

(b) Map

(c) Place and Route

Before translating the design, User Constrained file (UCF) is written to assign pin configuration of the FPGA to the all blocks I/O’s. Once this is done Translate merges together this UCF file and netlist generated after synthesis into Xilinx design file Mapping is done to fit the design into the available resources of target device i.e. FPGA. This is also important step of design. Last step of Design Implementation is Placing and Routing which places the logic blocks of the design into FPGA and route them together so that they occupy minimum area and meet timing requirements. This operation produces NCD output file.

4.5 Xilinx Device (FPGA) Programming

:

There is a option of Generate programming file on the process

tab of Xilinx ISE which converts the NCD file generated after routing to BIT file. It produces a bit stream for Xilinx Device (FPGA in this case) configuration. This BIT file is used to create .xsvf file to program the FPGA.

4.6 Configuring Target Device:

There is option of Generate Target PROM/ACE on the process tab of

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directly into the FPGA’s memory cells. We have to make sure that FPGA is connected to the PC where we are developing this design. After we download the .xsvf file into the FPGA. Now the FPGA is ready to be used as gate pulse generator. The four out pins are connected to the drivers of the MOSFET’s (SW1,SW 2,SW3 and SW4).

V.

MODELLING

AND

SIMULATION

OF

SINGLE

PAHSE

INVERTER

IN

MATLAB/SIMULINK

A Single phase full bridge inverter is created using SIMULINK/SimElectronics blocks. We have taken scope, pulse generator, subsystem GoTo and From blocks from SIMULINK (Commonly used blocks) and MOSFET switches, Voltage and current measuring block , DC supply and R load from SimElectronics.Fig.6 shows the complete model with PWM.

Fig.6 Complete model of Single phase full bridge inverter using SIMULINK/Simelectronics

VI. EXPERIMENTAL SETUP

An Experimental setup is configured using ULK trainer Kit (Xilinx FPGA Spartan 6 +ARM+DSP) , Single phase inverter using MOSFET’s with their drivers on bread board , 12 Volt DC power Supply ,Rload (150 Ω), Digital Oscilloscope and a Computer having ULK control panel and Xilinx software.

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VII. SIMULATION & RESULTS

Fig.9 Gate Pulses For MOSFET’s(SW1,SW2,SW3 & SW4)

Fig10 Output Voltage waveform Vo at Rload

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Fig12 Output Voltage waveform Vo at Rload

VIII. CONCLUSION

In this paper, a single phase full bridge inverter is studied and simulated in MATLAB/Simelectronics.The PWM code is written in VHDL and synthesised using Xilinx software and implemented in FPGA board.The four gate pulses are taken out from FPGA I/O port and with gate drivers,MOSFET’s are connected to these I/O pins.The output voltage is obtained at Rload.

REFRENCES

[1] Karshenas and H.R. Niroomand, Design and implementation of a single phase inverter with sine wave tracking method for emergency power supply with high performance reference , Electrical Machines and Systems, Proceedings of the Eighth International Conference ,Vol.2 ,September 2005.

[2]Yaosuo Xue , Liuchen Chang , Sren Baekhj Kjaer , Bordonau and J. Shimizu.,Topologies of single-phase inverters for small distributed power generators: an overview , Power Electronics, IEEE Transactions on Volume.19 , Issue: 5, Sept. 2004.

[3]Dariusz Czarkowski, Member,David V. Chudnovsky, Gregory V. Chudnovsky, and Ivan W. Selesnick,Solving the Optimal PWM Problem for Single-Phase Inverters, IEEE Tranactions on Tractions on circuits and systems, Vol. 49, No. 4, April 2002.

[4] Freeman and R. User-programmable gate arrays,IEEE Spectrum, vol. 25, Issue: 13,Dec. 1988. [5] Pelleri and D. Thibault, Practical FPGA Programming in C, Prentice Hall PTR, April 22, 2005. www. i in .co /techno og /dsp/ TI techpaper.pd .