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Procedia Technology 17 ( 2014 ) 713 – 719

ScienceDirect

2212-0173 © 2014 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/3.0/).

Peer-review under responsibility of ISEL – Instituto Superior de Engenharia de Lisboa, Lisbon, PORTUGAL. doi: 10.1016/j.protcy.2014.10.197

Conference on Electronics, Telecommunications and Computers – CETC 2013

A New Testing Method for Hardware Trojan Detection

Fahimeh Nejadmoghadam

1

, Ali Mahani

1

*, Yousef S. Kavian

2 1Department of Electrical Engineering, Shahid Bahonar University of Kerman, Kerman, Iran, 76169133

2Faculty of Engineering, Shahid Chamran University, Ahvaz, Iran f.nejad.moghadam@eng.uk.ac.ir, amahani@uk.ac.ir, y.s.kavian@scu.ac.ir

Abstract

This paper presents a partitioning approach to improve the Trojan detection process. The proposed transition probability based method tries to partition combinational circuits for pseudo exhaustive testing. The nodes of digital circuit in which the transition probability is less than predefined threshold mark as the potential point for hardware Trojan insertion. Thus, our objective is new circuit partitioning method to increase the transition probability of the potential points. We propose I-PIFAN partitioning algorithm in which the optimal size of primary input cone (N) and Fan-out (F) values are selected to partition a given combinational circuit. The partitioning method determines the optimal values of N and F to increase the transition probability and minimize 1) the number of test vector, 2) the number of partitions and 3) the critical path delay. This work ensures that all nodes with low transition probability pass the threshold after partitioning. The proposed algorithm reduces the test time of digital combinational circuits and improves Trojan detection quality. The partitioning method is applied to the ISCAS’85 benchmark circuits and the simulation results show the test vectors reduction and improvement of transition probabilities.

© 2014 The Authors. Published by Elsevier Ltd.

Selection and peer-review under responsibility of ISEL – Instituto Superior de Engenharia de Lisboa.

Keywords : Circuit partitioning; I-PIFAN algorithm; Transitin Probability

* Corresponding author. Tel.: +98-341-320-2534; fax: +98-341-323-5900.

E-mail address: amahani@uk.ac.ir

© 2014 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/3.0/).

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1. Introduction

With spread of globalization of the semiconductor industry, in order to reduce the manufacturing cost, the ICs (Integrated Circuit) fabrication has led to the outsourcing to untrusted foundries. So, the Trust of ICs is recently an emerging problem for some critical applications, such as military and communication. An adversary can maliciously alter the integrated circuits (ICs) during design and fabrication process by the insertion of malicious circuitry. Hence, the ICs may include hidden functions that work in rare conditions that are called “Hardware Trojan”. They are located in low controllability and observability positions [1, 2, 3]. So they are inactive for the most time span and are triggered under very rare conditions at the internal nodes.

In order to detect the Trojans in a circuit, they must be activated and then their effects propagated to the primary output [4, 5]. Thus, the Trojan detection methods require test vectors to generate transition signal on rare transition nodes. Exhaustive testing methods for a circuits with M inputs requires2M test vector. For large M, exhaustive testing is a time consumed and impractical method [6].

The pseudo exhaustive testing is a fast testing method that proposed by McCluskey [7]. The pseudo exhaustive testing method partitions the circuit in which each partition contains fraction of primary inputs. Authors in [8] developed the PIFAN partitioning algorithm based on the primary input cone and the Fan-out of each gate. Shaer and Dip in 2002 propose the improved PIFAN, I-PIFAN which is more effective to minimize the number of test vector and the number of partitions [9, 10].

In this article, a transition probability based approach is proposed to increase the 0-controlability and 1-controlability of rare transition points in which the I-PIFAN algorithm is used to find optimal values of N and F. Also the proposed method minimizes the number of test vector, the number of partitions and decreases the longest path delay.

The rest of the paper is organized as follows. In Section 2, the I-PIFAN partitioning algorithm is presented. The transition probability based partitioning discussed in section 3. Experimental results are shown in Sections 4 and the paper is concluded in section 5.

2. The I-PIFAN Algorithm

The I-PIFAN partitioning algorithm uses primary inputs (PI) cone and the Fan-Out (FO) of each node to partition the circuit. The partition is made by adding a PI and a PO (Primary Output) to partition point. If the node is not an inverter or buffer, and its PI cone is greater than one, it would be partible. So the I-PIFAN contains two different phases and needs two predefined constant F and N. During Phase-I, the FO of all nodes is compared with F. Then a multiplexer as a partition point is located at that nodes in which FO is greater than F. In Phase-II, the primary input (PI) of each gate is compared with another constant (N), and if PI of that gate is greater than N and the gate is not a buffer or inverter, a partitioning point is located at the output of the gate. Then the new value of PI and FO of all gates is calculated [11].

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Fig.1. Flow chart of Phase I of I-PIFAN algorithm

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2.1. Partitioning representation

Figure 3 shows a sample circuit which is partitioned by the I-PIFAN algorithm. This circuit has 8 primary inputs and 1 primary output. So, the number of test vector required for exhaustive test is28 256 . In figure 3 the PI and FO are depicted on the gates as (PI, FO). To run the partitioning algorithm N=4 and F=3 are selected.

a) b) c)

Fig. 3.a) A sample circuit which the values of primary input (PI) and Fan-Out (FO) are shown as (PI, FO) b) The circuit after phase I of I-PIFAN; c) The circuit after phase II of I-PIFAN

The circuit is partitioned by the I-PIFAN algorithm and the figures (4-a) and (4-b) illustrate the phase-I and phase-II of the algorithm respectively.

The required test vectors for the partition circuit are (2*24 23) 40 which shows strongly reduced test vectors after partitioning.

3. The proposed fitness function for circuit partitioning

There are some points in circuit with very low transition probability which are potential location to insert hardware Trojan. Thus the circuit partitioning is needed to increase the transition probability and decrease the test time of large circuits. In this paper the controllability of SCOAP testability measures is used [14, 15]. Controllability reflects the difficulty of setting a signal line to a required logic value from primary inputs and the value of controllability measures range between 1 to infinite.

In our proposed method, to partition a given circuit and select the optimal value of N and F, five factors are considered: hardware overhead, testing time, longest path, improvement of transition probability and controllability. Hardware overhead is determined by the number of partitioning. Testing time is estimated using the number of test vectors after partitioning. On the other hand, we try to increase the transition probability of gates that their transition is less than the predefined threshold, Such that the transition probability of all gates reaches to the top of the threshold. Also, the partitions must be select to reduce the controllability measures. So, the proposed method improves the test time of circuits and increases the probability of Trojan detection.

The fitness function of proposed method is given by: ) . ( )) 1 , 0 (min( TP I avg contr contr avg CP TV P f     (1)

where

,

and

are the weight of factors and P is the number of normalized partition and TV is the number of normalized test vector and CP is normalized longest path. Avg (min (contr 0, contr 1)) is the average of minimum normalized 0-controllability or 1-controllability. Also, avg (I.TP) is the average of improvement in the transition probability of gates which their transition probability is less than the threshold.

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First, the transition probability of all gates is calculated and the gates with low transition probability are detected. If the transition probability is lower than the threshold so the gate is potentially suitable to place Hardware Trojan. To obtain transition probability, the P1 is considered as signal probability and the transition probability from 0 to 1 or 1 to 0 is given by Pt=P0*P1, where P0 =1-P1 [12,13].

Figure 4.a shows the transition probability calculation. In figure 4 random patterns of inputs, with signal probability of ½ is used. The gate marked with a red rectangle has transition probability less than the predefined threshold (Pt=

 1/256 256

/

255 0.004).

a) Transition probability threshold before partitioning: 0.003 b)Transition probability threshold after partitioning: 0.05 Fig.4. (a) P0 and P1 probability before partitioning; (b) P0 and P1 probability after partitioning

Figure 4.b shows the probability P0 and P1 after circuit partitioning. As shown in figure 4 the transition probability of all gates is modified.

The partitioning also affects the 0-controllability and 1-controllability which is shown in figure 5.

a) b)

Fig.5. (a) 0-controllability and 1-controllability before partitioning; (b) 0-controllability and 1- controllability after partitioning

4. Simulation Results

Our proposed partitioning algorithm is implemented in C++. The ranges of N and F would be selected and then the I-PIFAN algorithm is applied to understudy circuit. Then the main parameters such as: the number of partitions, the

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number of test vectors, the effect of partitioning on critical path and the improvement of transition probability and the average of minimum controllability 0 and 1 are obtained.

To evaluate the proposed partitioning algorithm the ISCAS’85 benchmark circuits are considered. The circuits are introduced in Table 1. Table 1 shows the number of primary input, the number of primary output, the number of test vector without partitioning, the transition probability threshold and the number of gates with transition probability less than the determined threshold as called “Trojan gate”. Table 2 shows the simulation results in which the weighting coefficients are equal. In this table, the optimal values of N and F, the number of partitions, the number of test vectors, the partitioning effect on critical path and the average of minimum controllability 0 and 1 each partitions respectively is shown. In Table 2 and 3, we try to optimize the number of partition, the number of test vectors and the critical path delay. The proposed partitioning algorithm reduces the critical path delay and also increases the transition probability of all gates. We choose another threshold in order to increase the transition probability and improving Trojan detection. As shown in table 4, in order to increase the transition probability threshold for improving Trojan detection, the number of partitions is increased.

Table 1. ISCAS’85 benchmark circuit.

Circuit # of PI # of PO # of TV without portioning

Threshold # of potential Trojan

C432 36 7 6.87 1010 4108 6 C499 41 32 2.20 10 12 8103 32 C880 60 26 18 10 15 . 1  C1355 41 32 2.2 10 12 5 10 5 11 3 10 8  32 Table2.I-PIFAN comparison based on equal weighting coefficient and # of partitions using fitness function f.

The weighting coefficient are equal

Circuit N F # of par #of TV %CP min(contr) N F # of par

best partitioning based on # of part

# of TV %CP min(contr) threshold C432 20 8 18 9.49105 33.1 10.3 20 8 18 9.49105 33.1 10.3 105 C499 15 8 8 1.47 105 45.45 26 14 12 8 1.47 105 45.45 26 8103 C880 14 8 20 1.86 105 29.1 10.8 14 8 20 C1355 16 9 8 1.47105 69.68 26 14 12 8 5 10 86 . 1  29.1 10.8 410 3 5 10 47 . 1  69.68 26 8103

Table3.I-PIFAN comparison based on # of test vector and % of critical path using fitness function f. Best partitioning based on # of Test Vector

Circuit N F # of par #of TV % CP min(contr) N F # of par

best partitioning based on % of CP

# of TV %CP min(contr) threshold C432 15 8 30 1.16105 73.1 9.4 17 13 23 3.12105 75.1 11.2 10 5 C499 16 10 8 1.47 105 45.45 26 15 11 8 1.47 105 45.45 26 8103 C880 14 8 20 1.86 105 29.1 10.8 16 42 7 C1355 16 10 8 1.47 105 69.68 26 16 11 8 6 10 34 . 3  54.2 12.8 410 3 5 10 47 . 1  69.68 26 8103

Table 4.the optimal partitioning with greater transition probability

Circuit N F # of Par # of TV % of CP min(contr) threshold C432 14 8 35 1.810 5 93.4 12.2 9 10 3

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C880 16 11 33 1.38106 C1355 12 9 47 4.410 4

63.4 13.3 510 2 86.21 28.2 10 2

5. Conclusion

In this paper, in ordr to partition the ciruits, the improvement in transition probability and controrllability is considered. Increasing the transition probability help us to reach the better test time and to detect the Trojans that inserts in the points with low transition probability. Also proposed fitness function lead to the optimal value of N and F for partitioning algorithm. The optimal values of N and F ensure the transition probability of all point is greater than the selected threshold and accelerate the testing process.

References

[1] G X. Wang, M. Tehranipoor and J. Plusquellic, “Detecting malicious inclusions in secure hardware: Challenges and solutions,” in Proc. Of the IEEE International Workshop on Hardware-Oriented Security and Trust(HOST 2008), pp. 15-19, 2008.

[2] M. Banga and M. S. Hsiao, “A Novel Sustained Vector Technique for the Detection of Hardware Trojans,” in Proc. of the International

Conference on VLSI Design, pp. 327-332, 2009.

[3] R. S. Chakraborty, F. Wolff, S. Paul, C. Papachristou, and S. Bhunia, “MERO: A statistical approach for hardware trojan detection,” in Proc.

Workshop on Cryptographic Hardware and Embedded Systems(CHES09), 2009, pp. 396–410.

[4] Salmani H, and Tehranipoor M, Layout-Aware Switching Activity Localization to Enhance Hardware Trojan Detection. IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY , FEBRUARY 2012, VOL. 7, NO. 1

[5] M. Tehranipoor and F. Koushanfar.A survey of hardware Trojan taxonomy and detection. IEEE Design Test of Computers,27(1):10-2, 2010. [6]Shaer, B., Landis, D., Al-Arian, S., 2000a. Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits. IEEE Trans.

Very Large Scale Integr. (VLSI) Syst. 8 (6), 750–754.

[7] E. J. McCluskey and S. Bozorgui-Nesbat, “Design for Autonomous Test”, IEEE Trans. Comput, vol. C-30, pp. 866-875, Nov. 1981.

[8] Shaer, B., Landis, D., and Al-Arian, S. “Partitioning Algorithm to Enhance Pseudoexhaustive Testing of Digital VLSI Circuits”, IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems, Volume: 8 Issue 6, Dec. 2000 pp. 750 -754.

[9] Shaer, B., Al-Arian, S., Landis, D., 2000b. Partitioning sequential circuits for pseudoexhaustive testing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 8 (5), 534–541.

[10] Shaer, B., Dib, K., 2002. An Efficient Partitioning Algorithm of Combinational CMOS Circuits. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 142–146.

[11] Ganesh K ,Venayagomoorhty, Scott C.smith ,“ Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits, Engineering Application of Artifical Intelligence,2007.pp,177-184.

[12] Salmani H and Tehranipoor M,ECE Department,” A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on,2012.pp,112-125.

[13] D. D. Wackerly, W. Mendenhall III and R. L. Scheaffer, “Mathematical Statistics with Application, 7th edition” Thomson Learning, Inc., 2008.

[14] L. H. Goldstein and E. L. Thigpen. SCOAP: Sandia controllabil- ity/observability analysis program. In Proceedings of the Design Automation Conference , pages 190–196, 1980.

[15] R. Drechsler, S . Eggersglüﻙ, G. Fey, A. Glowatz, F. Hapke, J. Schloeffel, and D. Tille. On acceleration of SAT-based ATPG for industrial designs. IEEE Transactions on Computer-Aided Design for Circuits and Systems, 27(7):1329–1333, 2008.

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