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hearing aid implementation. OTAs are versatile analog building blocks that allow the amplification and filtering of signals with minimum power consumption2.
1.1 Architecture of OTA
Low power System design depends on the topology of the OTA’s. The designing of the OTA suffers challenges of the supply voltage and channel length scale down with the advancement of new generation CMOS technology. Operational transconductance Amplifier is the main building block for the analog processing applications. The design challenges for the OTA are still present in terms of gain, power consumption and gain bandwidth product efficiency. The classification of the operational tranconductance amplifier is single ended output and differential ended output or fully differential OTA’s. The fully differential provides stable input common mode voltage and reduces the harmonic distortion. The realization of CMOS based OTA has resulted in low power and high performance, however, the era of CMOS is nearing its end1.The basic balanced OTA structure of the OTA based on CMOS is shown in fig. 2 where Vp and Vm are the non-inverting and inverting terminal of the OTA. The transistor M3 and M31 forms the current mirror. Similarly M4 and M41 form the current mirror. The W / L ratio of the transistor M3 and M31 are same and W / L ratio of the transistor M4 and M41 are same. It is desirable to operate all transistors in saturation region for the operation on operational tranconductance amplifier. For the operation of transistors in the saturation region it is required to maintain the condition Vgs>Vt and Vds >Vgs – Vt , Where the value of the current Id is such that
Id = µCox – (3)
Fig. 2 Conventional CMOS based balanced OTA Structure1
So the conduction of the current depends on the transistor sizing that is the value of the W/L.
2. Power Consumption
The power consumption refers to the total power consumption of the device and power dissipation is referred to the total power wasted through the undesirable components. The power dissipation is dependent on the supply
voltage and current. The power dissipation of the device is calculated easily from the total power dissipation and load power dissipation. Power dissipation is dependent on the load CL. In power dissipation, power is converted to heat and then radiated away from the device. then a better cooling mechanism would be required to keep the circuit in normal conditions. Also large power dissipation requires expensive and noise cooling machinery, batteries and power conservation circuits3. Due to this generated heat, device may get damaged on continuous use. Slew rate and unity gain frequency of the OTA depends on the value of the load capacitor. These factors are decreased with the increase of the value of load CL. conventional amplifiers require power supply voltages at least equal to the magnitude of the largest threshold voltages of the PMOS or the NMOS transistors plus necessary signal swing4. Power Consumption is the important parameter while designing any type of the integrated circuit. There is a trade of between the power and performance of the integrated circuit. The main aim of this paper is to maintain performance of the integrated circuit while reducing the power consumption because the cost of the system is dependent on the power. Power dissipation in CMOS circuits is the combination of three main components.
Static (leakage) power dissipation
Short circuit power dissipation
2.1 Static Power Dissipation
Static power dissipation is related to logical states of the circuits and it is independent of switching activities. The static power dissipation of a circuit is defined as the product of the device leakage current and the supply voltage. Total static power dissipation is-
P =I V (4) where Isat is the current that flows through the circuit when there is no switching event and V DD is the supply voltage.
2.2 Short Circuit Power Dissipation
Short-circuit power dissipation in CMOS inverter occurs for finite rise and fall times of input voltage waveforms. A direct current path is formed, When both NMOS and PMOS transistors are turned on in the circuit simultaneously for a short duration of time during switching, This causes a direct current path between powers supply and ground. During switching, the current does not contribute to the charging/discharging of capacitance and current components that flow through both PMOS and NMOS transistor are called short circuit components5.
2.3 Dynamic Power Dissipation
Dynamic power dissipation is the result of power dissipation during switching activity. A higher operating frequency leads to more switching activities in the circuits and results in increased power dissipation5. The most significant contributor to dynamic power dissipation in CMOS circuits is the charging/discharging of load capacitance. Consider the simple CMOS inverter and assume that a step voltage with negligible rise and fall time is applied.When input voltage switches from 0-V DD, load capacitance in this duration is being discharged through NMOS transistor as the NMOS transistor starts conducting and PMOS transistor is turned off. Thus, the current in load capacitance is equal to the instantaneous drain current of the NMOS transistor.
3. Technology Scaling
With the advancement of the low power battery operated portable devices, technology scaling is the main requirement for the electronic industry. Transistor manufactured now a days are faster than the transistors manufactured 20 years back. They also require less area. So chip size reduces. The reduction of minimum dimensions in CMOS technologies necessitates the downscaling of power supply voltage accordingly in integrated circuits (ICs)6. Modern CMOS technology downscales, the reduction of supply voltage in CMOS integrated circuits has led to smaller common-mode input range for traditional operational amplifiers (OpAmp) with a single input differential pair and a reduced signal-to-noise ratio7. Scaling down the transistor sizing has provided the technology such as 180nm, 90nm and 45nm. Is is difficult to scale the transistor from 60nm to the lower range due to the short channel effects and reliability factor. New efficient materials and devices need to be found to replace the existing silicon based MOSFETs and provides enhancement in the Moore’s Law. Low Voltage operation and optimized power-to-performance ratio are required by modern wireless and portable electronics in order to decrease battery weight and size and to extend battery lifetime8. The demand of these devices depends on various factor such that higher speed, lower delay, low area, low power consumption, small silicon area, longer battery life and high realibility9.
Fig. 3 Moore’s Law
technologies to nanometer dimensions has resulted in reduced headroom for analog operation3. Moreover, short channel effects such as drain induced barrier lowering have decreased the drain-source impedances reducing the transistor’s intrinsic gain3.Usually, the transistor sizing problem in integrated circuit design is solved using manual design and circuit simulators, some structure specific optimizers11. Today leakage power has become an increasingly important issue in processor hardware and software design5. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption10.
4. Bulk Driven Technique
Generally terminal of the MOSFET is used while designing the analog circuit with the help of the CMOS technology. MOSFET has one more terminal called bulk terminal or body terminal that is not used usually. Bulk Driven (BD) technique is developed for the use of body terminal as the fourth terminal. Input is applied to the body terminal instead of the gate terminal. Bulk-driven circuits are typically used to overcome issues of poor signal swing in such cases3, 4. Bulk driven technology can be implemented on the NMOS transistor but it suffer from the low transconductance amplifier. So It is better to use bulk driven technology on the PMOS transistor. Bulk driven technology is basically used to provide the low operating input range. It reduces the threshold voltage value that was fixed for the gate driven technology. The rail-to-rail differential input stage is commonly used to take advantage of the entire range of the power supply 18, 19. The operation of the Bulk-driven MOS transistor is much like a JFET i.e. a depletion type device, it can work under negative, zero, or even slightly positive biasing condition20.
5. Proposed Operational Transconductance Amplifier Design
The schematic of the proposed bulk driven operational tranducdauctance amplifier is implemented with the help of 180nm technology shown in fig.4. Ibias current is 50µA for designing of the 2 stage operational. The layout of the bulk driven OTA is shown in fig. 5.
Fig. 4 Bulk driven Operational Transconductance Amplifier
Fig. 5 Bulk driven Operational Transconductance Amplifier Transient Response layout at Vdd=1.5V
5.1 Simulated Result on Vdd= 1.5V
Fig. 6, 7, 8,and 9 shows the transient response, Power , Leakage current and Noise Wavefrom of operational Transconductance Amlipfer for the supply Voltage of 1.5V.
Fig..6 Bulk driven Operational Transconductance Amplifier Transient Response at Vdd=1.5V
Fig. 8 Bulk driven Operational Transconductance Amplifier Leakage Cuurent Waveform at Vdd=1.5V
Fig. 9 Bulk driven Operational Transconductance Amplifier Noise Response Waveform at Vdd=1.5V
5.2 Simulated Result on Vdd= 0.9V
Fig. 10, 11,12 ,and 13 shows the transient response, Power, Leakage current and Noise Wavefrom of operational Transconductance Amlipfer for the supply Voltage of 0.9V
Fig. 11 Bulk driven Operational Transconductance Amplifier Power waveform at Vdd=0.9 V
Fig.12 Bulk driven Operational Transconductance Amplifier leakage current Response at Vdd=0.9V
Fig. 13 Bulk driven Operational Transconductance Amplifier Noise waveform at Vdd=0.9V
6. Simulation Result
Table 1 shows the performance parameter of bulk driven OTA for the low voltage range at 180nm technology Table 1
OTA Parameter
Bulk-Driven OTA at VDD=1.5 V
Bulk-Driven OTA at VDD=0.9 V
Bulk-Driven OTA at VDD=0.8 V
Power
consumption(pW) 34.88 20.61 15.04
Noise(V/µsec) 7.79X10-11 6.35 X10-11 3.186 X10-11
Leakage Current(pA) 136.2 19.14 17.71
Fig. 14 Performance Parameter of the bulk driven OTA using 180nm
7. Conclusion
Table 1 shows that the power consumption is reduced with the reduction in the supply voltage from Vdd = 1.5V to 0.8V. Other parameter such as leakage current, leakage power and noise is reduced with the use of bulk driven technology. Bulk Driven technique is applied at the input stage of the operational transconductancce amplifier is used to reduce the threshold voltage requirement for the gate terminal. This effect causes the deduction in the leakage. So leakage current and leakage power is reduced. Bulk driven technique reduces the supply voltage required for the proper functioning of the operational transconductance amplifier for 180nm technology. Performance parameter is compared as shown in fig. 14 for the different supply voltage.
Acknowledgement
Authors would like to thank, Director, National Institute of Teacher Training and Research, Chandigarh for their inspiration, motivation and support throughout this research.
Reference
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0 5 10 15 20 25 30 35 40
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Power Consumption
Noise
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