Microchip PIC18F452 Core Hardware. CPU, Memory, Interrupts, and I/O Ports

Microchip PIC18F452 Core Hardware

CPU, Memory, Interrupts, and I/O Ports

PIC18F452 CPU

(Actually PIC18FXX2)

Harvard Architecture

Harvard Architecture

ƒ Separate instruction and data busses

ƒ Instructions (opcodes)

ƒ 16-bit wide instruction bus

ƒ 21-bit instruction address:

up to 2M bytes FLASH program memory (where 1M = 1Kx1K)

ƒ Data (operands & results)

ƒ 8-bit wide data bus

ƒ 12-bit data address:

up to 4K bytes data RAM

ƒ 256 bytes EEPROM (not on diagram) 18F452 has

ƒ 32K bytes FLASH (where 1K = 1024)

ƒ 1.5K bytes data RAM

Program Memory (Opcodes) 32K x 8-bit

FLASH

Data Memory (Operands) 1.5K x 8-bit

SRAM

CPU

Data Opcode Address

Opcode

Operand Address 15-bit

16-bit 8-bit

12-bit

4K x 8-bit 2M x 8-bit SRAM

FLASH

21-bit

18F4X2 Block

Diagram

ƒ 16-bit wide

instruction bus (blue)

(blue)

ƒ 8-bit wide data bus

(yellow)

(yellow)

ALU

ƒ 8-bit ALU

ƒ Working Register WREG behaves as an accumulator

ƒ Can also source operands and write

results anywhere in Data RAM, including SFRs Ö Register-to-Register architecture

ƒ 8x8 single-cycle multiplier

ƒ Hardware multiplier ~70 times faster than algorithm

MOVF ARG1, WREG MULWF ARG2

ƒ See code in Data Sheet for 16x16 multiplies

ƒ Also MATH18 files on MxLab Server

Programmer’s Model – “Core” SFRs

INDF0

7 0

POSTINC0

7 0

PLUSW0

7 0

PREINC0

7 0

POSTDEC0

7 0

INDF1

7 0

POSTINC1

7 0

PLUSW1

7 0

PREINC1

7 0

POSTDEC1

7 0

INDF2

7 0

POSTINC2

7 0

PLUSW2

7 0

PREINC2

7 0

POSTDEC2

7 0

PRODH

15 8

PRODL

7 0

FSR2H FSR2L

11 8 7 0

FSR2

FSR0H 11 8

FSR0L

7 0

FSR0

FSR1H 11 8

FSR1L

7 0

FSR1

PC Status

Register

Bank Select Register

FSR Registers

(pointers used for indirect addressing)

Product Register

PC Latch Register

Program Counter

Hardware Stack (21-bit x 31 deep)

20

PCH

15 8

PCL

7 0

PCU 16 BSR

11 8 Working

Register

W or WREG

7 0

20

PCLATH

15 8

PCLATU 16 PCLAT

4 0

STKPTR STATUS

7 0

20

TOSH

15 8

TOSL

7 0

TOSU 16 TOS

Top of Stack Stack Pointer

TBLPTR

Table Pointer

21

TBLPTRH

15 8

TBLPTRL

7 0

TBLPTRU 7 0 16

TABLAT

Table Latch

INTCON

7 0

PIE1

7 0

IPR1

7 0

PIR1

7 0

PIE1

7 0

IPR1

7 0

PIR2

7 0

INTCON2

7 0

INTCON3

7 0

Interrupt Control Registers

Status Register

STATUS: Status (Flags) Register 0xFD8

p. 52 U-0 U-0 U-0 R/W R/W R/W R/W R/W

Bit Names - - - N OV Z DC C

bit 7 bit 0

PO/BO Reset - - - x x x x x

MCLR Reset - - - u u u u u

bit 4 N: Negative bit.

1: Result was negative 0: Result was positive bit 3 OV: Overflow bit.

1: Overflow of bit 7 occurred during signed arithmetic operation 0: No overflow occurred

bit 2 Z: Zero bit.

1: Result of operation was zero 0: Result of operation was not zero bit 1 DC: Digit Carry bit.

1: Carry-out from the 4^th low order bit of result occurred 0: No carry from the 4^th low order bit of result occurred bit 0 C: Carry bit.

1: Carry-out from the MSB of result occurred on addition (OR No borrow occurred on subtraction) 0: Carry from the MSB of result did not occur on addition (OR Borrow occurred on subtraction)

Memory

Program Memory Data Memory

EEPROM

Program Memory

Program Memory

ƒ 21-bit PC (Program Counter) can address 2MB

ƒ 18F452 has 32KB of 8-bit FLASH

ƒ Can store 16K instructions

ƒ Reset address is 0x000000

ƒ High priority interrupt address is 0x000008

ƒ Low priority interrupt address is 0x000018

ƒ Unimplemented memory reads

Return Address Stack

ƒ Dedicated 31 x 21-bit hardware stack – calls and interrupts can nest 31 levels deep

ƒ PC is pushed on CALL, RCALL or interrupt response

ƒ PC is popped on RETURN, RETURNW or RETFIE

ƒ Stack pointer pre-increments on push, post-decrements on pop

ƒ TOS register contains contents of stack entry pointed to by STKPTR

ƒ STKPTR contains STKFUL, STKUNF (underflow) bits

ƒ Will reset on STKUNF, (address zero is popped) can reset on STKFUL if CONFIG4L<STVREN> is set

Low 5 bits

of STKPTR

(2

= 32)

STKPTR Register

STKPTR: Return Stack Pointer Register 0xFFC p. 38 R/W R/W U-0 R/W R/W R/W R/W R/W

Bit Names ^{STKFUL STKUNF - STKPTR4} STKPTR3 STKPTR2 STKPTR1 STKPTR0

bit 7 bit 0

PO/BO Reset 0 0 - 0 0 0 0 0

MCLR Reset 0 0 - 0 0 0 0 0

bit 7 STKFUL: Stack Full Flag bit.

Note: Can only be cleared by user software or a POR.

1: Stack is full (31 entries) or has overflowed.

0: Stack has not become full or has overflowed.

bit 6 STKUNF: Stack Underflow Flag bit.

Note: Can only be cleared by user software or a POR.

1: Stack underflow has occurred.

0: Stack has not underflowed.

bit 5 Not implemented – reads as 0.

bit 4-0 STKPTR4:STKPTR0: Stack pointer value bits.

This 5-bit field contains the hardware stack pointer value, between 0 and 31 inclusive.

Program Counter

ƒ The 21-bit PC is contained in the three registers PCU:PCH:PCL

ƒ Only PCL is directly readable

ƒ PCU and PCH can be updated through the (readable and writable) latch registers PCLATU, PCLATH

ƒ Operations that write PCL also copy PCLATUÖPCU and PCLATH ÖPCH

ƒ Operations that read PCL also copy PCUÖPCLATU and PCH ÖPCLATH

ƒ CALL, RCALL, GOTO and branch instructions directly load

PCU:PCH:PCL

Clocking & Instruction Cycle

ƒ Four internal phase clocks Q1 to Q4 derived from clock input OSC1 of period T

ƒ Fetch instruction cycle (instruction bus is active):

ƒ Q1: increment PC

ƒ Q2: write instruction address to program memory

ƒ Q3: fetch opcode on instruction bus

Clocking & Instruction Cycle

ƒ Execute instruction cycle (data bus is active)

ƒ Cycle varies – see instruction set. Typically:

ƒ Q1: decode instruction in instruction register

ƒ Q2: fetch operand from data memory

ƒ Q3: execute

ƒ Q4: write result to destination in data memory

ƒ So, one instruction executes every T

= 4°T

Ö pipelining

Byte Storage

ƒ Program words (opcodes) are 16-bit, stored in 2 successive byte locations

ƒ lsb of the PC always reads 0, Ö PC increments by 2 – but –

ƒ Fixed data (e.g. look-up tables) can be stored 2 bytes per

program word if TBLPTR and TBLAT are used to access

them – see later

Two-word Instructions

ƒ There are four 2-word instructions:

ƒ MOVFF (Move from f to f)

ƒ CALL (Subroutine Call)

ƒ GOTO (Unconditional Branch)

ƒ LFSR (Load FSR)

ƒ Each causes a pipeline stall, as two instruction fetch

cycles are needed before an execute cycle can occur

Data Memory

Data Memory

ƒ Data memory is Static RAM (SRAM)

ƒ 12-bit data address, can address 2 ¹² = 4096 bytes = 4K

ƒ Data memory is divided into 16 banks (pages), each containing 256 bytes (8-bit addressable within a bank)

ƒ 18F452 has 7 banks implemented: 0, 1, 2, 3, 4, 5 & 15, giving 1,664B of addressable data memory (including SFRs)

ƒ A bank is selected using a 4-bit field in the Bank Select

Register: BSR<3:0>

Data Memory Contents

Data memory contains

ƒ Special Function Registers (SFRs)

ƒ Some SFRs have ‘core’ functions – WREG, STATUS, etc

ƒ Most SFRs used to monitor and command the peripherals

ƒ SFRs begin at the highest address in Bank 15 (0x000FFF) and extend downwards to 0x000F80

ƒ Much more detail later…

ƒ General Purpose Registers (GPRs)

ƒ Available to the programmer (or compiler) for general use

Data Memory Addressing

Data memory can be addressed using either

ƒ Direct Addressing Ö Operand address(es) are embedded in the opcode, and fixed at run time

ƒ PIC18 has three direct addressing methods:

ƒ Banked

ƒ Access Bank

ƒ Address in Opcode

ƒ Indirect Addressing Ö Operand address(es) are separate from the opcode and determined at run time

ƒ Indirect addressing is using a pointer to refer to data

ƒ PIC18 has one direct addressing method

(although it has many flexible options)

Data Memory Map

Direct Addressing (Banked)

ƒ A bank selected by 4 BSR bits

ƒ A 16-bit opcode contains (only) one 8-bit address Ö full 12 bits

Direct Addressing (Access Bank) Access Bank is comprised of

ƒ Upper 128 bytes in Bank 15 (all of the SFRs)

ƒ Lower 128 bytes in Bank 0 (a few of the GPRs)

ƒ One instruction bit (called ‘a’) forces use of the Access Bank Ö 8 bit

address

Direct Addressing: Banked

ƒ Sixteen banks (or pages) of RAM

ƒ 4-bit Bank Select Register (BSR) choses a bank

ƒ 8-bit address from opcode selects one of the 256 registers in that bank

ƒ 4 + 8 = 12-bit address

selects on from 2

=

4096 registers

Direct Addressing: Access Bank

ƒ BSR is not used (implicitly zero)

ƒ 8-bit address selects one of the 128 Access Bank registers in Bank 0

ƒ High half of Bank 15 are

the SFRs

Direct Addressing: Address in Opcode

ƒ BSR is not used

ƒ Full 12-bit address is contained in the

opcode

ƒ Only used in four instructions:

MOVFF

CALL

GOTO

LFSR

Examples: Direct Data Memory Addressing

Many instructions have the form MNEMONIC, f, d, a

where

ƒ f is an 8-bit file register (0x00 to 0xFF)

ƒ d is the result destination: WREG (d = 0) or file register (d = 1)

ƒ a signifies access bank (a = 0) or banked addressing (a = 1)

ƒ a and d are optional and both default to 1 if omitted

ƒ Direct addressing (banked)

MOVLB 02 ; set BSR to Bank 2

ADDWF H’55’, 0, 1 ; ADD WREG to contents of addr. 55 (f=55)

; in bank 2 (a=1), result to WREG (d=0)

Operand is the contents of data memory address 0x02

Examples: Direct Data Memory Addressing

Again:

MNEMONIC, f, d, a where

ƒ f is an 8-bit file register (0x00 to 0xFF)

ƒ d is the destination of the result: WREG (d = 0) or file register (d = 1)

ƒ a signifies access bank (a = 0) or banked addressing (a = 1)

ƒ Direct addressing (using Access Bank)

; MOVLB not required

ADDWF 0xAA, 0, 0 ; ADD WREG to contents of address AA (f=AA)

; in access bank (a=0), result to WREG (d=0)

Operand is the contents of data memory address 0x00AA in

the Access Bank

Indirect Data Memory Addressing

ƒ Indirect Addressing Ö Operand address(es) are separate from the opcode and determined at run time

ƒ Indirect addressing is the same as using a pointer to refer to data

ƒ PIC18 has one direct addressing method (although it has many flexible options)

ƒ Requires the use of one of the three File Select Registers

FSRn, and a corresponding Indirect File Operand INDFn to

hold the 12-bit address of an operand

Indirect Data Memory Addressing

ƒ Use any of 3 FSRs (File Select Registers) FSR0, FSR1, FSR2 to store a 12-bit pointer to an operand

ƒ Any reference to an INDF register (Indirect File Operand) in an instruction actually operates on the operand pointed to by the corresponding FSR

LFSR FSR0, ADDR ; load FSR0 with value ADDR

MOVWF INDF0, W ; move WREG to register pointed to by FSR0

INDF0 is an example of an indirect file operand – it

represents the data at the address that is stored in FSR0

ƒ Cannot directly read or write any of the indirect file

operands – only the FSRs are physical registers

Indirect Data Memory Addressing

Indirect Data Memory Addressing

ƒ Pointer in a FSR can be post-decremented, pre- or post- incremented, etc. Ö step through tables etc.

ƒ Some examples:

MOVWF INDF0, W ; don’t change the pointer value FSR0 MOVWF POSTDEC1, W ; post-decrement FSR1

MOVWF POSTINC2, W ; post-increment FSR2 MOVWF PREINC0, W ; pre-increment FSR0

MOVWF PLUSW1, W ; offset value in FSR1 by value in WREG

Reading/Writing FLASH Program Memory

Reading/Writing FLASH Program Memory

ƒ During normal program execution, FLASH can be

ƒ Read – one byte at a time

ƒ Written – one 8-byte block at a time – see data sheet

ƒ Erased – one 64-byte block at a time – see data sheet

ƒ Code cannot be fetched during FLASH read/write

ƒ Reading FLASH needed to move constants from FLASH to data memory – operands can’t be in FLASH

ƒ Writing to FLASH can alter program at run-time (!!)

TBLRD /TBLWT: Table Read/Write

ƒ Operands cannot be in Program Memory

ƒ TBLRD, TBLWT instructions move data between Program Memory (FLASH) and Data Memory

ƒ All reads and writes are byte-wide

ƒ Data move through an 8-bit register, TABLAT (the Table Latch register)

ƒ The 21-bit Table Pointer in TBLPTR addresses (points to) a byte in Program Memory

ƒ It is contained in the three registers

TBLPRTU:TBLPTRH:TBLPTRL

TBLRD* Table Read

Table Read copies a byte from Program Memory to Data Memory

ƒ Write 21-bit table pointer value to TBLPRTU, TBLPTRH, TBLPTRL

ƒ Executing TABLWT* instruction moves byte from Program Memory location pointed at by TBLPTR to TABLAT register in data space

ƒ Move TABLAT into (say) WREG

TBLWT* : Table Write

Table Write copies a byte from Data Memory to Program Memory

ƒ Write 21-bit table pointer value to TBLPRTU, TBLPTRH, TBLPTRL

ƒ Move (say) WREG into the Table Latch Register TABLAT

ƒ Executing TABLWT* instruction moves byte from TABLAT to

Program Memory location pointed at by TBLPTR

TBLRD /TBLWT: Table Read/Write

ƒ TBLPTR can be post-decremented, pre- or post-incremented, etc.

Ö step through tables, etc.

ƒ The * represents the pointer (21-bit address) in TBLPTR

ƒ The 22nd bit is set to enable

access to the device config bits.

Post-decrement TBLRD *-

TBLWT *-

Post-increment TBLRD *+

TBLWT *+

TBLRD * None TBLWT *

Effect on TBLPTR Instruction

TABLRD * ; read value pointed to into TABLAT, don’t change TBLPTR value TABLRD *- ; read value pointed to into TABLAT, decrement TBLPTR value TABLWR +* ; pre-increment TBLPTR, write TABLAT to address pointed at

Table Read/Write Registers

ƒ Four associated Special Function Registers:

EECON1 : selects FLASH/EEPROM access, erase, EEPROM read/write, etc.

EECON2: not a physical register

TABLAT: 1-byte Table Latch register TBLPTR: 3-byte Table Pointer register

EECON1: EEPROM Control Register 1 0xFA6

p. 66 R/W R/W U-0 R/W R/W R/W R/W R/W

Bit Names EEPGD CFGS - FREE WRERR WREN WR RD

bit 7 bit 0

PO/BO Reset x x - 0 x 0 0 0

MCLR Reset u u - 0 u 0 0 0

TBLRD /TBLWT: Write and Erase

ƒ See data sheet for fine details of writing to and erasing

blocks of program memory (FLASH)

Data EEPROM Memory

Data EEPROM Memory

ƒ EEPROM = Electrically-Erasable Programmable Read-only Memory

ƒ Retains data even when powered-off

ƒ Use to store

ƒ Calibration constants

ƒ Save context on power fail, etc

ƒ PIC18F452 has 256 bytes of EEPROM – 8-bit address

ƒ More EEPROM easily added via SPI or I ² C expansion

Data EEPROM Registers

ƒ Four associated Special Function Registers:

EECON1 : selects FLASH/EEPROM access, erase, EEPROM read/write, etc.

EECON2 : not a physical register (but used in EEPROM write cycle) EEDATA : 8-bit data read/to be written

EEADR : 8-bit address of data read/to be written

EECON1: EEPROM Control Register 1 0xFA6

p. 66 R/W R/W U-0 R/W R/W R/W R/W R/W

Bit Names EEPGD CFGS - FREE WRERR WREN WR RD

bit 7 bit 0

PO/BO Reset x x - 0 x 0 0 0

MCLR Reset u u - 0 u 0 0 0

Data EEPROM Read

EEPROM Read

ƒ Write pointer value (address) to EEADR

ƒ Clear EECON1<EEPGD> (access EEPROM)

ƒ Set EECON1<RD> (initiate read)

ƒ Data is available in EEDATA the very next cycle, so

ƒ Read that data…

Data EEPROM Write

EEPROM Write – see Example 6-2 in data sheet

ƒ Write pointer value (address) to EEADR

ƒ Write data value to EEDATA

ƒ Clear EECON1<EEPGD> (access EEPROM)

ƒ Set EECON1<WREN> (enable EEPROM writes)

ƒ Clear INTCON<GIE> (disable interrupts)

ƒ Write 0x55 to EECON2 (required sequence)

ƒ Write 0xAA to EECON2 (required sequence)

ƒ Set EECON1<WR> (initiate write - required sequence)

ƒ Set INTCON<GIE> (enable interrupts)

ƒ Clear EECON1<WREN> (disable EEPROM writes)

Interrupt System

Interrupt System

ƒ Multiple (18) interrupt sources

ƒ Two interrupt response priorities: high and low

ƒ High priority response preempts any low priority interrupt service routine

ƒ All interrupts execute through 2 fixed addresses:

ƒ 0x0008: High priority interrupt address

ƒ 0x0018: Low priority interrupt address

ƒ ‘Compatibility mode’ (with PIC16XX) – no priorities

ƒ 0x0008: Interrupt address

Interrupt Sources

ƒ Up to four external pins

ƒ INT0 is RB<0>

ƒ INT1 is RB<1>

ƒ INT2 is RB<2>

ƒ Change on RB<7:3>

( RB is PORTB )

ƒ INT0, INT1, INT2 are edge triggered – selectable as rising or falling

ƒ Fourteen internal events

Low Voltage Detect Power Supply

PSP Read/Write Parallel

INT0 External Interrupt External Pins

(all on PORTB)

USART Tx Buffer Empty MSSP Interrupt

Synchronous Serial

I²C Bus Collision CCP1 Interrupt Capture/Compare/PWM

CCP2 Interrupt

A/D Conversion Done Analog Inputs

USART Rx Buffer Full USART Port

TMR3 Overflow TMR2 to PR2 Match TMR1 Overflow TMR0 Overflow Timer Interrupts

PortB Change Detect INT2 External Interrupt INT1 External Interrupt

Interrupt Registers

ƒ Ten associated Special Function Registers:

RCON<IPEN> (bit 7): enable high/low priority feature

INTCON, INTCON2, INTCON3 : these control

the “core” interrupt functions - enables, priorities, flags

PIR1, PIR2 ^: Peripheral Interrupt Request flags

PIE1, PIE2 ^: Peripheral Interrupt Enable flags

IPR1, IPR2 ^: Interrupt Priority flags control

the “peripheral” interrupt priorities

Enabling Interrupt Response

Generally, for interrupt response to occur, require:

ƒ Global Interrupt Enabled TRUE

ƒ Local (individual) Interrupt Enabled XXXXIE TRUE

ƒ Individual interrupt XXXX requested – sets XXXXIF

ƒ No other interrupt current at higher priority

ƒ Then, control will pass to either 0x0008 or 0x0018

which must pass control to the user’s ISR

Interrupt Control: Priority Mode

ƒ Interrupt source can be programmed as either High or Low Priority depending on a XXXXIP bit

ƒ High-Priority Global Int. Enable bit: INTCON<GIEH> (bit 7)

ƒ Enables/disables all High Priority interrupt responses

ƒ Low-Priority Global Int. Enable bit: INTCON<GIEL> (bit 6)

ƒ Enables/disables all Low Priority interrupt responses

ƒ Interrupt Enable (mask) bits: Names like XXXXIE

ƒ Enable/disable response to individual interrupt requests

ƒ No difference between “Core” and “Peripheral” interrupt sources

Interrupt Control: High Priority

ƒ Priority Enable bit:

IPEN ≡ RCON<7> ≡ 1

ƒ Global Interrupt Enable High Priority bit:

GIEH ≡ INTCON<7>

ƒ Enables/disables all high-priority interrupt responses

ƒ Local Interrupt Enable bits XXXXIE enable/disable response to individual interrupt requests

ƒ Interrupt Priority bits XXXIP must be 1 to set High Priority

ƒ An active High Priority interrupt inhibits all Low Priority interrupts

RCON = 1xxx xxxx

TMR0IF TMR0IE

RBIF RBIE

INT0IF INT0IE

INT1IF INT1IE

INT2IF INT2IE

GIEH=INTCON<7>

TMR1IF TMR1IE

xxxIF xxxIE

EEIF EEIE

Interrupt to CPU Vector at 0x0008 High Priority

EEIP TRM1IP

xxxIP INT2IP INT1IP RBIP TMR0IP

To Low Priority Interrupt System Note:

interrupt priority bits xxxxIP = 1

Interrupt Control: Low Priority

ƒ Priority Enable bit:

IPEN ≡ RCON<7> ≡ 1

ƒ Global Interrupt Enable Low Priority bit:

GIEL ≡ INTCON<6>

ƒ Enables/disables all low- priority interrupt responses

ƒ Local Interrupt Enable bits XXXXIE enable/disable response to individual interrupt requests

ƒ Interrupt Priority bits XXXIP must be 0 to set Low Priority

ƒ All Low Priority interrupts are

RCON = 1xxx xxxx

TMR0IF TMR0IE

RBIF RBIE

INT0IF INT0IE

INT1IF INT1IE

INT2IF INT2IE

GIEL=INTCON<6>

TMR1IF TMR1IE

xxxIF xxxIE

EEIF EEIE

Interrupt to CPU Vector at 0x0018 Low Priority

EEIP TRM1IP

xxxIP INT2IP INT1IP RBIP TMR0IP

Interrupt Request from High Priority Interrupt System

Note:

interrupt priority bits xxxxIP = 0

Interrupt Response Cycle: Priority Mode

When an interrupt request is responded to

ƒ GIEH or GIEL is cleared, disabling further interrupts

ƒ Return address is pushed onto the stack

ƒ PC is loaded with a specific address:

either 0x0008 (High) or 0x0018 (Low)

ƒ User ISR must do everything else – see following

ƒ User ISR must end in

ƒ RETFIE instruction – this causes hardware to pop

the return address and set GIEH or GIEL as appropriate

FAST Interrupt Return

ƒ Fast Register Stack (Shadow Registers)

ƒ Three byte-wide registers STATUSS, WREGS, BSRS

ƒ Not directly readable or writable

ƒ Always loaded with STATUS, WREG, BSR in hardware during interrupt response

ƒ User ISR can end in RETFEI FAST – this pops the

return address, STATUS, WREG, BSR and sets either GIEH or GIEL

ƒ Beware!! Will fail if both High and Low Priority interrupts enabled Ö values from High Priority interrupt overwrite values from Low Priority interrupt

ƒ If not used for interrupts, shadow registers can be used in a CALL

Configuring the Interrupt System

ƒ Your code should generally do the following

clear INTCON<GIEH> ; disable interrupt response clear INTCON<GIEL>

set RCON<IPEN> ; enable priority mode IPR1 = xxxxxxxx ; set interrupt priorities IPR2 = xxxxxxxx

PIE1 = xxxxxxxx ; enable individual interrupts PIE2 = xxxxxxxx

PIF1 = 00000000 ; clear all pending flag bits PIF2 = 00000000

set INTCON<GIEH> ; enable interrupt response set INTCON<GIEL>

ƒ Note that there are also some priority bits xxxxIP, enable bits xxxxIE

and flag bits xxxxIF in INTCON, INTCON2 and INTCON3

User Interrupt Service Routines

ƒ Only two vectors Ö only two ISRs

ƒ Inside an ISR, user code must

save STATUS ; save context

save BSR save WREG

if ( more than 1 source may have requested interrupt ) { for ( each interrupt used ) {

if ( xxxxIF and xxxxIE ) { service interrupt xxxx

clear xxxxIF ; often needed in software }

} }

restore WREG ; restore context

restore BSR

restore STATUS ; last - REG ops. change flags!!

RETFIE

Installing Interrupt Service Routines

ƒ When response to an interrupt request occurs, PC is loaded with either 0x08 or 0x18

ƒ User must arrange to place appropriate executable

code at one or both of these addresses. Good practice to always have at least a null ISR

ƒ Depends on language – e.g.

goto lowIsr

#pragma interruptlow lowIsr void lowIsr( void )

{ ... }

Summary of Interrupt Control Bits

PIE1<PSPIF>

PIE1<SSPIF>

PIE1<TXIF>

PIE1<RCIF>

PIE1<ADIF>

PIE2<CCP2IF>

PIE1<CCP1IF>

PIE2<TMR3IF>

PIE1<TMR2IF>

PIE1<TMR1IF>

INTCON<TMR0IF>

INTCON<RBIF>

INTCON3<INT2IF>

INTCON3<INT1IF>

INTCON<INT0IF>

Flag Bit

IPR1<PSPIR>

IPR1<SSPIP>

IPR1<TXIP>

IPR1<RCIP>

IPR1<ADIP>

IPR2<CCP2IP>

IPR1<CCP1IP>

IPR2<TMT3IP>

IPR1<TMR2IP>

IPR1<TMR1IP>

INTCON2<TMR0IP>

INTCON2<RBIP>

INTCON3<INT2IP>

INTCON3<INT1IP>

High Priority Only

Priority Bit

INTCON<INT0IE>

INT0 External Interrupt

PIR1<TXIE>

UART Tx Buffer Empty

PIR1<SSPIE>

MSSP Interrupt

PIR1<PSPIE>

PSP Read/Write

PIR1<CCP1IE>

CCP1 Interrupt

PIR2<CCP2IE>

CCP2 Interrupt

PIR1<ADIE>

A/D Conversion Done

PIR1<RCIE>

UART Rx Buffer Full

PIR2<TMR3IE>

TMR3 Overflow

PIR1<TMR2IE>

TMR2 to PR2 Match

PIR1<TMR1IE>

TMR1 Overflow

INTCON<TMR0IE>

TMR0 Overflow

INTCON<RBIE>

Change on PortB

INTCON3<INT2IE>

INT2 External Interrupt

INTCON3<INT1IE>

INT1 External Interrupt

Enable Bit

Source

Critical Regions

ƒ A Critical Region is a block of code (assembler or HLL) that must not be interrupted

ƒ Often occurs when

ƒ variable is accessed in both the main code and in an ISR and

ƒ The access (read or write) is non-atomic

(an atomic action is guaranteed to complete)

ƒ Solution 1 (For HLL or asm)

ƒ Disable interrupts

ƒ Access the variable

ƒ Re-enable interrupts

ƒ Solution 2 (For asm only)

ƒ Access variable using only instructions that do atomic read-modify-write

ƒ Peatman gives an example

Critical Regions - Example

ƒ Poor practice

MOVF PORTB, W ; copy PortB to WReg

ANDLW B’11111001’ ; AND literal with Wreg MOVWF PORTB ; copy result to PortB

ƒ Good practice

MOVLW B’11111001’ ; copy literal to WReg ANDWF PORTB ; PortB = PortB AND WReg

; this is a Read-Modify-Write op.

Interrupt Control: Compatibility Mode

ƒ Compatibility Ö Compatible with PIC16XXX

ƒ Priority Enable bit: IPEN ≡ RCON<7> = 0 (priority disabled)

ƒ Interrupt address is 0x08 in compatibility mode

ƒ “Core” Interrupt Sources

ƒ Five core sources: INT0, INT1, INT2, RB change, TMR0

ƒ Controlled through INTCON, INTCON1, INTCON2

ƒ Enabled/disabled only by GIE ≡ INTCON<7>

ƒ “Peripheral” Interrupt Sources

ƒ The other 13 sources are peripheral interrupts

ƒ Controlled through PIE1, PIE2

ƒ Enabled/disabled by GIE ≡ INTCON<7>

ƒ Can also be enabled/disabled by PEIE ≡ INTCON<6>

ƒ Individual Interrupt Enable bits XXXXIE enable/disable response to

individual interrupt requests

Interrupt Control: Compatibility Mode

RCON = 0xxx xxxx

TMR0IF TMR0IE RBIF RBIE INT0IF INT0IE INT1IF INT1IE

INT2IF INT2IE

GIE=INTCON<7>

TMR1IF TMR1IE xxxIF xxxIE

EEIF

PEIE=INCON<6>

5 ‘Core’ Interrupts Peripheral Interrupts

Interrupt to CPU Vector at 0x0008

Note: No interrupt priority bits now

Interrupt Response Cycle: Compatibility Mode

When an interrupt request is responded to

ƒ GIE is cleared, disabling further interrupts

ƒ Return address is pushed onto the stack

ƒ PC is loaded with address 0x0008

ƒ User ISR must do everything else

ƒ User ISR must end in

ƒ RETFIE instruction – pops the return address and sets GIE

ƒ Note: FAST return is not applicable in this mode

ƒ Configuration is similar to priority mode

I/O Port Hardware

Using I/O Ports as Digital I/O, not

as the Alternate Peripherals…

I/O Ports

ƒ PIC18F452 has five digital I/O ports: PORTA, PORTB, PORTC, PORTD, and PORTE

ƒ PIC18F2X2 parts omit PORTD, (the PSP) and

PORTE (PSP control bits or three analog inputs)

I/O Port Voltage Levels

ƒ Most I/O bits are either

ƒ TTL-compatible I/O, outputs with totem-pole drivers -or-

ƒ Schmitt trigger inputs with CMOS levels

Typical voltages at V _SS = 0V and V _DD = 5.0V supply are

ƒ TTL-compatible I/O

ƒ V

= 0.8V

ƒ V

= 2.0V

ƒ Schmitt trigger Inputs

ƒ V

= 1.0V

ƒ V

= 4.0V

ƒ V

= 0.6V

ƒ V

= 4.3V

Alternate Port Functions

Each bit (pin) on each port can be used as a general-purpose digital I/O pin, or

ƒ Port A: (7 bits)

ƒ Analog inputs (5 channels), A/D Reference voltage inputs, Low voltage detect input

ƒ Xtal oscillator input

ƒ System (machine cycle) clock output

ƒ Timer0 clock input

ƒ Port B: (8 bits)

ƒ Four external interrupt pins

ƒ In-circuit debug/programming pins

Alternate Port Functions (2)

ƒ Port C : (8 bits)

ƒ USART I/O pins

ƒ Synchronous Serial Port (SPI or I

R) pins

ƒ Capture/Compare/PWM I/O pins

ƒ Timer1 I/O pins

ƒ Port D : (8 bits) (not bonded on 28-pin devices)

ƒ Simplest hardware

ƒ Parallel Slave Port (PSP) data bus

ƒ Port E : (3 bits) (not bonded on 28-pin devices)

ƒ Three analog input channels – or –

ƒ Parallel Slave Port control bus (bits 2:0)

I/O Port Registers

ƒ Each port has three associated registers

ƒ TRISx: Data direction register

ƒ PORTx: Input latch – reads levels on the port pins

ƒ LATx: Output latch – useful for read-modify-write

operations

(x ∊ A, B, …, E)

Port D: PORTD, TRISD and LATD

ƒ PORTD is an 8-bit bidirectional port

ƒ TRISD is the Data Direction register

ƒ Setting (=1) a bit makes that pin an Input: 1 Ö I and makes the pin output driver high-impedance

ƒ Clearing (=0) a bit makes that pin an Output: 0 Ö O

ƒ Reading PORTD register will read the pin status

ƒ Writing PORTD register will write to the port latch

ƒ Reading/writing LATD has the same effect (!) – reads

come from PORTD, writes go to LATD

Port D: Registers and Circuit

Simplest hardware – 8-bit bidirectional port Not present on PIC18F2X2 (28 pin) parts Data Direction

ƒ On WR TRISD ↓ edge, data bit latched into TRIS latch

Digital Output Function (TRISD<n>=0)

ƒ On WR LATD ↓ edge, data bit latched into output (data) latch

ƒ On RD LATD high, data just written can be read back

Digital Input Function (TRISD<n>=1)

ƒ On RD PORTD high, data bit held in transparent latch can be read on data bus

ƒ Latch prevents changes during bus read

RD7:RD0 (I/O port mode)

Input Latch

Port D Bit Definitions

Alternate Pin Functions (See PIC18FXX2 Data Sheet for bit definitions)

ƒ Parallel Slave Port (PSP) data bus (bits 7:0)

PORTD: 8-bit Bi-directional Port 0xF83

p. 95 et seq. R/W R/W R/W R/W R/W R/W R/W R/W

Bit Names RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0 bit 7 bit 0

PO/BO Reset x x x x x x x x

MCLR Reset u u u u u u u u

Port A: PORTA, TRISA and LATA

ƒ PORTA is a 7-bit bidirectional port

ƒ Direction register TRISA and latch register LATA function

identically to those for Port D

Port A Bit Definitions

Alternate Pin Functions (See PIC18FXX2 Data Sheet for bit definitions)

ƒ Analog inputs (bits 5, 3:0)

ƒ A/D Reference voltage inputs (bits 3,2)

ƒ Low voltage detect input (bit 5)

ƒ OSC2 – Xtal oscillator input 2 (bit 6)

ƒ Clock output (bit 6)

PORTA: 7-bit Bi-directional Port 0xF80

p. 87 et seq. U-0 R/W R/W R/W R/W R/W R/W R/W

Bit (Pin) Name - RA6 RA5 RA4 RA3 RA2 RA1 RA0

- OSC2 AN4 - AN3 AN2 AN1 AN0 - CLKO SS TOCKI VREFP VREFM - -

- - LVDIN - - - - -

bit 7 bit 0

PO/BO Reset - x 0 x 0 0 0 0

MCLR Reset - u 0 u 0 0 0 0

Port A I/O Circuits

Direction register TRISA and latch register LATA function identically to those for Port D

Data Direction

ƒ On WR TRISA ↓ edge, data bit latched into TRIS latch

ƒ Must set (=1) TRISA for analog inputs!!

Digital Output Function (TRISA<n>=0)

ƒ On WR LATA ↓ edge, data bit latched into output (data) latch

ƒ Output driven high and low (totem pole output)

ƒ On RD LATA high, data just written can be read back

Digital Input Function (TRISA<n>=1)

ƒ On RD PORTA high, data bit held in transparent latch can be read on data bus

ƒ Latch prevents changes during bus read

RA5 and RA3:RA0

Input Latch

Port A I/O Circuits

Input Latch Input Latch

Note – output is open drain

RA4 (T0CLKI) RA6 (OSC2/CLKO)

Totem Pole (push-pull) outputs

Port B: PORTB, TRISB and LATB

ƒ PORTB is an 8-bit bidirectional port

ƒ Direction register TRISB and latch register LATB function identically to those for Port A

ƒ Each I/O pin has a weak pull-up, active only on inputs

ƒ All pullups enabled by clearing #RBPU ≡ INTCON2<7>

ƒ Typical pullup current 50µA, max 450 µA at V _pin =V _SS

ƒ RB2:RB0 have alternate functions INT2:INT0

ƒ RB7:RB4 have interrupt-on-change functionality

Port B Bit Definitions

Alternate Pin Functions (See PIC18FXX2 Data Sheet for bit definitions)

ƒ External interrupt inputs (bits 3:0)

ƒ Alternate (non-default) Capture/Compare/PWM 2 I/O pin (bit 4)

ƒ In-circuit serial programming inputs (bits 7:5)

PORTB: 8-bit Bi-directional Port 0xF81

p. 90 et seq. R/W R/W R/W R/W R/W R/W R/W R/W

Bit (Pin) Name RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

PGD PGC PGM - INT3 INT2 INT1 INT0 - - - - CCP2 - - -

bit 7 bit 0

PO/BO Reset x x x x x x x x

MCLR Reset u u u u u u u u

Port B I/O Circuits

Interrupt-on-change

ƒ Four pins RB7:RB4 can request interrupt on state change

ƒ Pin must be configured as input for this to be active

ƒ Any MOVxx instruction has execute cycle with

ƒ Q1 – decode

ƒ Q2 – read data

ƒ Q3 – process data

ƒ Q4 – write result

ƒ Schematic shows “set RBIF if the state read has changed from the previous state” – not quite correct?

Latch n-1 ? n ?

Port B I/O Circuits

External interrupt pins

ƒ Three pins can be configured as external interrupt pins:

RB2:RB0 ≡ INT2:INT0

ƒ Pin must be configured as input for this to be active

Input Latch

RB2:RB0 (INT2:INT0)

Port C: PORTC, TRISC and LATC

ƒ PORTC is an 8-bit bidirectional port

ƒ Direction register TRISC and latch register LATC function identically to those for Port A

ƒ All Port C pins have Schmitt trigger input buffers

ƒ Caution! Take care when setting the TRISC bits:

ƒ Some peripherals force the pin to be an input

ƒ Some peripherals force the pin to be an output

Port C Bit Definitions

Alternate Pin Functions (See PIC18FXX2 Data Sheet for bit definitions)

ƒ UART Asynchronous I/O(bits 7: 6)

ƒ UART Synchronous I/O (bits 7: 6)

ƒ Synchronous Serial Port (bits 5:3)

ƒ Default Capture/Compare/PWM I/O pins – CCP1 & CCP2 (bits2:1)

ƒ Timer1 I/O (bits 1:0)

PORTC: 8-bit Bi-directional Port 0xF82

p. 93 et seq. R/W R/W R/W R/W R/W R/W R/W R/W

Bit Names RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

RX TX SDO SDI SCK - T1OSI T1OSO DT CK - SDA SCL CCP1 CCP2 T1CKI bit 7 bit 0

PO/BO Reset x x x x x x x x

MCLR Reset u u u u u u u u

Port C Circuits

Note that

ƒ Peripheral Data Out bypasses the Output Data Latch

ƒ Peripheral Output Enable determines output buffer activity for peripheral writes (not TRISC)

ƒ Peripheral Data In bypasses the Input Latch

Input Latch

Multiplexer (MUX) MUX select line

Port E: Registers and Circuit

ƒ PORTE is a 3-bit bidirectional port

ƒ Direction register TRISE and latch register LATE function identically to those for Port A

ƒ Not present on PIC18F2X2 parts

ƒ All Port E pins have Schmitt trigger input buffers

RE2:RE0 (I/O port mode)

Input Latch

Port E Bit Definitions

Alternate Pin Functions (See PIC18FXX2 Data Sheet for bit definitions)

ƒ Analog inputs (bits 2:0)

ƒ Parallel Slave Port control bus (bits 2:0)

PORTE: 3-bit Bi-directional Port 0xF84

p. 99 et seq. U-0 U-0 U-0 U-0 U-0 R/W R/W R/W

Bit Names - - - - - RE2 RE1 RE0

- - - - - #CS #WR #RD - - - - - AN7 AN6 AN5 bit 7 bit 0

PO/BO Reset - - - - - 0 0 0

MCLR Reset ^{- - - - - 0 0 0}

Parallel Slave Port (PSP)

ƒ Can make custom ICs that interface directly to an 8-bit microprocessor bus

ƒ PORTD can be configured as an 8-bit PSP with control signals on PORTE

ƒ All Port D pins have TTL buffers in PSP mode

ƒ All Port E pins have Schmitt trigger input buffers

ƒ Not present on PIC18F2X2 parts (only 28 pins)

PORT D

RE<2>

3 Control Bits

8

DATA BUS

RE<1>

RE<0>

#CS

#WR

#RD

“New” Custom IC

Parallel Slave Port (PSP)

ƒ PSP Enabled by setting TRISE<PSPMODE>

ƒ Must also ensure

ƒ TRISE<2:0>=1

(Port E pins are inputs)

ƒ ADCON1 s.t. Port E pins are digital

ƒ Port D becomes an 8-bit data bus

ƒ Port E provides 3 control signals:

ƒ #CS ≡ RE<2> – Chip Select

ƒ #WR ≡ RE<1> – Write

ƒ #RD ≡ RE<0> – Read

PSP Read Timing

ƒ Read from (output from) the PSP begins when #CS and #RD are first detected to be low

ƒ #OBF (Output Buffer Full) set when available byte has not been read

from the PSP by external device

PSP Write Timing

ƒ Write to (input to) the PSP begins when #CS and #WR are first detected to be low

ƒ #IBF (Input Buffer Full) set when byte can be read by CPU

ƒ #IBOV (Input Buffer Overflow flag) set if next byte written by external

device before previous was read by CPU