Altium Designer Guide

Electronics and

Computer Systems Engineering

Altium Designer Guide

Tutorial part 2 – PCB Design

This is Part 2 of a beginner’s guide to PCB design using Altium Designer and is geared towards the

following individuals:

• P

OSSESS AMPLE THEORETICAL ELECTRONICS KNOWLEDGE

• H

AS LITTLE OR NO

PCB

DESIGN EXPERIENCE

2

Creating the PCB

O

NE OF THE REASONS WHY IT IS IMPORTANT TO DEFINE THE

PCB

FOOTPRINTS WHILE ENTERING IN THE SCHEMATIC IS TO BE ABLE TO PROVIDE A GOOD ESTIMATE OF HOW MUCH BOARD AREA YOU WILL NEED

.

• G

ENERALLY SPEAKING THE FOLLOWING THINGS MAKE PRODUCTION MORE EXPENSIVE

• L

ARGER AREA

• M

ORE LAYERS

• S

MALLER HOLES

• C

LOSER TOLERANCES

• C

LOSER TRACES AND SPACING

• T

HINNER OR

T

HICKER

PCB

O

UR GOAL IS TO KEEP COST AS LOW AS POSSIBLE WHILE STILL BEING ABLE TO TRANSFER A SCHEMATIC TO A FUNCTIONING

PCB.

T

HERE ARE NO SPECIAL CHARACTERISTICS OF THIS DESIGN THAT REQUIRE ANY EXOTICS

,

AND WE CAN USE A

2

LAYER

PCB

FOR LOW COST

F

ROM THE PROJECT TAB IN THE BOTTOM LEFT CORNER

,

CLICK THE

‘F

ILES

’

TAB AND CLICK THE UPWARD FACING ARROWS UNTIL YOU CAN SEE

3

Y

OU WILL GET A VERY FRIENDLY WIZARD SCREEN

,

CLICK NEXT TO CONTINUE

C

HOOSE THE BOARD UNITS AS

I

MPERIAL

4

T

HERE ARE MANY PREDEFINED TEMPLATES FOR EXOTIC DESIGNS OR STANDARD

PCB

COMPUTER INTERFACE FORMS

,

SUCH AS

AT

B

US

,

PCI

BUS

,

E

UROCARD

,

AND MANY OTHERS

.

C

HOOSE

CUSTOM

(

AT THE TOP

)

L

EAVE THE DEFAULT SETTINGS

(R

ECTANGULAR

,

5000

MILS X

4000

MILS

)

T

HE DIMENSIONS OF THE BOARD WILL BE ON A GENERIC

,

INFORMATION LAYER

(M

ECHANICAL LAYER

)

WHICH IS USED TO GIVE INFORMATION TO THE BOARD HOUSE

.

5

D

O YOU REMEMBER WHAT A POWER PLANE IS

?

H

OW DOES IT DIFFER FROM A SIGNAL LAYER

?

(HINT:

YOU CAN HAVE SIGNAL LAYERS INTERNAL OR EXTERNAL

,

AND YOU CAN HAVE POWER PLANES INTERNAL AND EXTERNAL

)

M

AKE SURE THE HOLE TYPE IS SET ON THRUHOLE VIAS ONLY

6

O

UR BOARD CONTAINS MOSTLY SURFACE MOUNT COMPONENTS

,

SO CHECK THIS OPTION

C

HOOSE THAT BOTH SIDES OF THE BOARD CAN CONTAIN COMPONENTS

.

NOTE:

T

HESE SETTINGS REALLY DON

’

T MATTER

.

T

HEY EXIST FOR THE AUTOROUTER WHICH WE WILL NOT BE USING

C

HANGE TRACK SIZE

(10

MILS

)

AND TRACE CLEARANCE

(8

MILS

)

W

HAT IS THE METRIC LENGTH OF

8

MILS

????

C

HANGE THE MINIMUM VIA HOLE SIZE TO

15

MILS

,

AND THE MIN

.

VIA WIDTH TO

30

MILS

7

T

HE WIZARD IS NOW COMPLETE AND YOUR

PCB

IS CREATED BASED ON THE VALUES YOU HAVE GIVEN

.

R

IGHT CLICK ON THE

PCB

>

C

LICK

‘O

PTIONS

’

8

U

NCHECK

‘D

ISPLAY

S

HEET

’

(

THIS HAS A USE

,

BUT FOR NOW WE WANT TO REDUCE CLUTTER

)

C

HANGE THE MARKERS FROM LINES TO DOTS AND CLICK

OK.

NOTE:

T

HE SNAP GRID AND COMPONENT GRID ARE VERY IMPORTANT

,

WE WILL GET INTO THIS LATER THOUGH

.

T

HE

PCB

HAS BEEN ADDED TO THE LIST OF DOCUMENTS

,

BUT HAS

NOT

BEEN ADDED TO THE PROJECT

(N

OTICE IT IS LISTED AS A FREE DOCUMENT

)

C

LICK AND DRAG THE

PCB

TO YOUR PROJECT

R

IGHT CLICK ON THE

PCB1.P

CB

D

OC FILE AND SAVE THE FILE IN YOUR PROJECT DIRECTORY

.

9

I

F YOU GET THE FOLLOWING WARNING

,

JUST CLICK

OK.

I

T IS TELLING YOU THERE MAY BE COMPATIBILITY ISSUES IF YOU TRY TO OPEN THE

PCB

DOCUMENT IN AN OLDER VERSION OF

A

LTIUM

.

I

F YOU SELECT YOUR SCHEMATIC AGAIN

,

CLICK THE

D

ESIGN BUTTON UP TOP AND THEN CLICK ON

‘UPDATE

PCB

DOCUMENT

DEV

BOARD.P

CB

D

OC

’

10

T

HIS WILL OPEN THE

ECO

(E

NGINEERING

C

HANGE

O

RDER

)

T

HIS IS ASKING WHICH CHANGES TO MAKE

.

V

ALIDATE CHANGES WILL CHECK FOR ERRORS IN THE PROCESS

E

XECUTE WILL ACTUALLY PERFORM THE CHANGE

C

LICK

‘V

ALIDATE

’

AT THE BOTTOM

.

T

HIS MAY TAKE A WHILE DEPENDING ON THE COMPLEXITY OF THE PROJECT

.

N

OTICE THE GREEN CHECK BOXES TO THE RIGHT

.

T

HIS MEANS THAT EACH STEP WITH THE GREEN CHECK MARK CAN BE PERFORMED SUCESSFULLY

.

11

B

ECAUSE THERE ARE USUALLY MANY DIFFERENT STEPS TO CREATING THE

ECO,

IT IS USUALLY HELPFUL TO CHECK THE BOX THAT SAYS

‘O

NLY SHOW ERRORS

’

AT THE BOTTOM

.

Y

OU ARE IN GOOD SHAPE WHEN NO ERRORS OCCUR AND THIS LIST IS EMPTY

W

HEN NO ERRORS APPEAR DURING THE VALIDATION STEP

,

YOU CAN CLICK THE

‘

EXECUTE CHANGES

’

TO ACTUALLY IMPORT THE SCHEMATIC TO THE

PCB

12

NOTE:

E

VERY TIME YOU PERFORM AN

ECO,

THE RESULTS ARE SAVED IN A TEXT FILE IN YOUR PROJECT DIRECTORY

E

XPORT THE

NETLIST

FOLLOWING THE MENU SEQUENCE BELOW

(Y

OU MUST BE ON THE

PCB

DOCUMENT

,

NOT THE SCHEMATIC DOCUMENT

13

T

HE

N

ETLIST CONTAINS INFORMATION SUCH AS PARTS

,

FOOTPRINT

,

AND VALUE

(

AS SHOWN BELOW

)

I

T ALSO CONTAINS CONNECTION INFORMATION AS SHOWN TO THE RIGHT

E

ACH

N

ETLABEL

(

EITHER ASSIGNED BY YOU OR THE SOFTWARE

,

EVERY NET HAS A NETLABEL

)

SHOWS WHICH COMPONENT AND PIN NUMBER CONNECTS TO THAT NODE

14

N

ETLIST

C

ONNECTIONS FOR

N

ET

MISO:

P3

PIN

9

P1

PIN

5

U1

PIN

16

A

QUICK LOOK AT THE SCHEMATIC SHOWS THAT THIS NET IS PROPERLY CONNECTED

Creating the Netlist

F

ORTUNATELY

,

A

LTIUM HANDLES THE

N

ETLIST TRANSPARENTLY TO THE END USER

,

BUT IT IS IMPORTANT TO AT LEAST BE FAMILIAR WITH THE TERM AND HOW THE SCHEMATIC IS TRANSFERRED TO THE

PCB

AND VICE VERSA

A

NY CHANGES THAT ARE MADE MUST BE MADE TO THE

N

ETLIST

.

T

HE

N

ETLIST IS THE

‘

LINK

’

BETWEEN THE

PCB

AND THE SCHEMATIC

.

I

T IS IMPORTANT THAT THE SCHEMATIC AND

PCB

AGREE ON CONNECTIONS

,

NETS

,

FOOTPRINTS

,

ETC

..

A

FTER EXECUTING CHANGES

.

I

F THERE ARE ERRORS OR NOT

,

WHATEVER THE SOFTWARE CAN IMPORT INTO THE

PCB

IT WILL DO SO

N

OTICE HOW THE SOFTWARE JUST SORT OF

‘

DUMPS

’

ALL YOUR PARTS

(PCB

F

OOTPRINTS

)

OFF TO THE SIDE OF THE BOARD

.

D

OES ANYONE KNOW WHY THE SOFTWARE DOESN

’

T PLACE THE PARTS

???

15

W

E WILL GET TO THAT LATER WHAT IT DOES

T

HIS IS CALLED A

S

PECIAL

S

TRING

N

OTICE HOW ALL THE PARTS ARE PLACED INSIDE A COLORED RECTANGLE BOX CALLED

‘M

AIN

’.

T

HIS IS CALLED A

ROOM.

R

OOMS ARE USED TO GROUP COMMON CIRCUIT TYPES

.

A

ROOM IS CREATED FOR EACH SCHEMATIC PAGE WE HAVE

S

INCE WE ONLY HAVE ONE PAGE

,

CALLED

‘MAIN’,

THERE IS ONLY ONE ROOM

R

OOMS ARE LIKE BORDERS FOR YOUR PARTS

.

A

N ITEM INSIDE A ROOM CANNOT ESCAPE WITHOUT AN ERROR MESSAGE

.

S

INCE WE ONLY HAVE ONE ROOM

,

WE CAN DELETE THE ROOM WITHOUT AFFECTING OUR LAYOUT AT ALL

.

C

LICK ANYWHERE IN THE ROOM AND HIT THE

DEL

KEY

T

HE ROOM WILL DISAPPEAR AND THE COMPONENTS WILL REMAIN

NOTE:

Y

OU CAN DISABLE THE USE OF ROOMS IN PROJECT OPTIONS

16

I

F YOU HIT THE

‘L’

KEY ON THE

PCB

PAGE

,

IT WILL BRING UP THE FOLLOWING DIALOG

.

C

HANGE THE OPTION UNDER MECHANICAL LAYERS THAT SAYS

‘U

SED

L

AYERS

O

NLY

’

N

OTICE THE DIFFERENT TABS AT THE BOTTOM OF THE SCREEN

.

T

HE SELECTED LAYER WILL LOOK DIFFERENT THAN THE OTHERS

(

IN THIS CASE

,

TOP LAYER

)

U

NLIKE A SCHEMATIC

,

WHICH IS

2D,

A

PCB

IS A

3D

ENTITY WITH A WHOLE BUNCH OF LAYERS ON TOP OF EACH OTHER

.

17

I

F WE ZOOM IN

,

NOTICE THAT

U2

(T

HE

FT232

CHIP

)

HAS SEVERAL GREEN PADS

,

AND SEVERAL RED PADS

.

T

HE RED PADS REPRESENT SOMETHING ON THE TOP LAYER

.

B

UT WHY ARE SOME OF THE PADS GREEN

??

I

F WE TYPE

‘L’

AGAIN

,

IT WILL BRING UP THE BOARD LAYER LISTS

.

S

INCE THE LAYERS ARE COLOR CODED

,

WE CAN QUICKLY LOOK FOR THE GREEN ONE AND NOTICE THAT THIS IS A

DRC

ERROR MARKER

(D

ESIGN

R

ULE

C

HECK

)

F

OR SOME REASON

A

LTIUM HAS A PROBLEM WITH OUR

FT232

C

HIP

18

I

F WE PUT THE MOUSE OVER ONE OF THE GREEN PADS

,

IT WILL TELL US INFORMATION ABOUT THE PAD

,

MOST IMPORTANTLY IT WILL TELL US WHAT THE ERROR IS

F

OR THESE PADS

,

THERE IS A CLEARANCE CONSTRAINT ERROR BETWEEN A PAD ON THE TOP LAYER

,

AND ANOTHER PAD ON THE TOP LAYER

NOTE:

I

T IS UP TO YOU TO DECIDE IS THIS IS A REAL ERROR

,

OR AN IMPROPERLY SET RULE

I

N THIS CASE IT IS AN INCORRECTLY SET RULE

.

T

HE PADS ON THIS FOOTPRINT ARE

8

MIL APART

,

THE CLEARANCE IS SET TO

10

MIL

,

HENCE THE ERROR

.

L

IKE THE SCHEMATIC

,

THERE ARE RULES WE NEED TO SET

.

C

LICK

D

ESIGN

>

R

ULES

(

OR

)

R

ULES WIZARD TO CREATE

/

MODIFY RULES

19

T

HE

DRC

EXPECTS A MINIMUM SPACING BETWEEN DIFFERENT NETS OF

8

MILS

.

M

AKE THE FOLLOWING RULE CHANGES

(

FROM TOP OF LIST DOWN

):

M

AX

T

RACE

W

IDTH

=

200

MILS

M

INIMUM

V

IA

S

IZE

=

15

MILS

,

M

IN

V

IA DIAMETER

=

30

MILS

21

T

RY USING TRIAL AND ERROR AND CHANGE THE SETTING FOR MINIMUM CLEARANCE TO

7

MILS AND YOU

’

LL NOTICE THE ERROR MARKERS GO AWAY

.

NOTE:

T

HERE ARE MANY BETTER WAYS OF DETERMINING THE ACTUAL SPACING

,

BUT WE WANT TO KEEP THINGS SIMPLE FOR NOW

N

OTICE THE SMALL LINES

,

THESE ARE COLLECTIVELY REFERRED TO AS A

R

ATSNEST

.

I

T IS A WAY OF TELLING YOU WHICH CONNECTIONS NEED TO BE MADE STILL

22

C

OMPONENTS ARE MOVED IN THE

PCB

THE SAME WAY THEY ARE MOVED IN THE SCHEMATIC

.

N

OTICE HOW THE

R

ATSNEST CONNECTIONS REMAIN AND WILL DYNAMICALLY CHANGE BASED ON HOW A COMPONENT IS ROTATED

.

T

HERE IS USUALLY A TRADEOFF WHEN PLACING COMPONENTS

.

T

HIS

USB

CONNECTOR MIGHT BE EASIER TO ROUTE IF IT IS IN THE MIDDLE OF THE BOARD

,

BUT WILL BE DIFFICULT FOR A USER TO USE A CONNECTOR IN THE MIDDLE OF THE BOARD

.

F

OR THIS DESIGN

,

DO THE BEST YOU CAN TO MAKE IT EASIER TO ROUTE

,

FOR YOUR PROJECT

,

IT SHOULD MAKE PHYSICAL SENSE TO AN END USER

,

EVEN IF IT MEANS HARDER ROUTING

EVERYONE’S

PCB

WILL

BE

DIFFERENT!!!

D

O NOT TRY TO MAKE YOURS EXACTLY LIKE MINE OR ANYONE ELSE

’

S

.

T

HIS DESIGN

I

WENT OUT OF MY WAY TO CREATE A MORE DENSE DESIGN FOR CLARITY AND TO RESIZE THE BOARD

.

F

EEL FREE TO USE THE ENTIRE BOARD AREA

.

U

SUALLY

,

COMPONENTS THAT ARE CLOSE TOGETHER IN THE SCHEMATIC ARE PLACED CLOSE TOGETHER IN THE

PCB.

23

F

OR THE

USB

CIRCUIT

,

WE WILL GROUP THE FOLLOWING COMPONENTS

24

N

EXT GROUP THE COMPONENTS AS THEY ARE ARRANGED IN THE SCHEMATIC

.

P

RIORITIZE THE PLACEMENT BY ORGANIZING THE HIGH SPEED OR CRITICAL COMPONENTS FIRST AT CLOSEST LENGTH

U

SUALLY THE MORE TIME YOU TAKE IN COMPONENT PLACEMENT

,

THE LESS TIME YOU WILL NEED FOR ROUTING

25

W

HICH PLACEMENT IS BETTER AND WHY

???

(L

OR

R)

W

HICH PLACEMENT IS BETTER AND WHY

???

(L

OR

R)

26

PCB Inspector

S

TART THE

PCB

I

NSPECTOR

.

27

H

OLD DOWN SHIFT AND

CLICK BOTH

R14

AND

C10

T

HE

PCB

INSPECTOR SHOWS TWO OBJECTS ARE DISPLAYED

/

SELECTED

.

C

HANGE THE LAYER FROM

TOP

TO

BOTTOM,

AND ALL SELECTED OBJECTS ARE IMMEDIATELY CHANGED TO THE BOTTOM LAYER

28

W

E CAN NOW PLACE

R14

AND

C10

UNDERNEATH THE

USB

CONNECTOR AND MAKE THE CONNECTION FROM THE BOTTOM OF THE BOARD

.

N

OTICE THE PADS ARE

BLUE

(

COLOR CODE BOTTOM LAYER

),

T

HIS LETS YOU KNOW THAT THESE COMPONENTS ARE ON THE BOTTOM OF THE BOARD

Component Placement

29

T

HE CURRENT LIMITING RESISTORS CAN BE PLACE ON THE BOTTOM OF THE BOARD

(

UNDER THE

FT232

CHIP

)

T

HE

RX

AND

TX

INDICATOR

LED

S SHOULD BE PLACED ON THE TOP OF THE BOARD

T

HIS IS BEGINNING TO LOOK VERY CRAMPED AND HARD TO SEE THINGS WHICH ARE OVERLAPPING

.

30

C

LICK ON THE

LS

AT THE LEFT OF THE LIST OF LAYERS

.

T

HIS IS TO CHANGE THE ACTIVE

L

AYER

S

ET

(V

ISIBLE LAYERS

)

T

HIS WILL BRING UP A SCREEN LIKE THAT ON THE RIGHT

.

C

HANGE THE SETTING TO

‘S

IGNAL

L

AYERS

’

T

HIS SHOWS ONLY

SIGNAL

LAYERS

OR LAYERS THAT CONDUCT ELECTRICITY AND HIDES THE REST OF THE LAYERS THAT WE DON

’

T CARE ABOUT AT THE MOMENT

.

M

OST OF ROUTING IS BEST DONE WITH THE

S

IGNAL

L

AYERS LAYERSET ACTIVE

I

T IS MUCH EASIER TO LOOK FOR LINES THAT CROSS OVER HERE AND MAKE CHANGES WITH COMPONENT PLACEMENT

.

NOTE:

B

E CAREFUL WHEN PLACING COMPONENTS IN THIS MODE

.

T

HE TOP

OVERLAY

(

SILKSCREEN

)

IS SOMETIMES USED FOR COMPONENT BOUNDARIES AND YOU MIGHT PLACE A COMPONENT INSIDE THE BOUNDARY OF ANOTHER PART

31

Routing

N

OW WE NEED TO MAKE ELECTRICAL CONNECTIONS BETWEEN THE COMPONENTS

C

LICK THE ICON TO INTERACTIVELY ROUTE CONNECTIONS

NOTE:

W

HICHEVER LAYER IS ACTIVE

,

THE TRACE WILL BEING ON THAT LAYER

M

AKE A CONNECTION BETWEEN TWO COMPONENTS AS SHOWN

.

N

OTICE THAT THE WIRE ITSELF IS ASSOCIATED WITH THE NET

VCC

B

Y LOWERING THE

‘M

ASKED

O

BJECTS

F

ACTOR

’

IN THE

‘M

ASK

L

EVEL

’

IN THE BOTTOM RIGHT CORNER

,

WHEN YOU CLICK ON A PAD TO WIRE

,

SUCH AS

VCC,

IT WILL DULL OUT THE OTHER CONNECTIONS TO MAKE IT EASIER TO SEE WHERE THE

32

Y

OU SHOULD ADJUST THIS SO YOU CAN EASILY SEE THE HIGHLIGHTED NET

,

BUT STILL SEE THE OUTLINES OF THE OTHER PADS

33

N

OTICE THE NEW

VCC

TRACE IS

15

MILS THICK

T

RY TO ROUTE THIS BOARD USING MOSTLY PERPENDICULAR TRACES

.

F

OR EXAMPLE

,

USE THE BOTTOM LAYER FOR HORIZONTAL TRACES

,

AND THE TOP LAYER FOR VERTICAL TRACES

.

T

HIS WILL MAKE THE ROUTING MUCH EASIER

(

AT THE EXPENSE OF MORE HOLES

)

T

HE CONNECTION ON THE RIGHT IS A DIFFERENTIAL PAIR AT A HIGH FREQUENCY

.

D

IFFERENTIAL PAIRS SHOULD BE KEPT CLOSER TOGETHER

A

LTHOUGH YOU ARE USING AN ORTHOGONAL METHOD OF LAYING OUT THE BOARD

,

C

RITICAL NETS DO NOT NEED TO APPLY

.

34

A

S A GENERAL RULE FOR

RIGHT NOW

,

YOU WANT TO MAKE THE TRACES ABOUT AS LARGE AS YOU CAN MAKE THEM

.

W

HY

?

W

HEN THE

USB

CONNECTOR IS COMPLETE

,

THERE SHOULD BE FOUR TRACES COMING FROM THE

USB

INTERFACE TO THE REST OF THE CIRCUIT

35

T

HE

TX

AND

RX

TRACES FROM THE

FT232

C

HIP TO THE REST OF THE CHIP CAN BE RELATIVELY HIGH SPEED

(1

MB/

S

)

F

OR REASONS WE WILL GO OVER LATER

,

THIS MEANS WE SHOULD TRY TO MAINTAIN THE SAME GEOMETRY THROUGHOUT THE TRACE

.

(D

ON

’

T VARY THE WIDTH

)

W

HEN THE ROUTING IS COMPLETE

,

YOU SHOULD HAVE SOMETHING THAT LOOKS LIKE THE PICTURE TO THE RIGHT

.

VCC

AND

GND

CONNECTIONS ARE NOT ALL COMPLETE THOUGH

.

36

I

N THE LEFT

-

HAND DROP DOWN BOX AT THE TOP

,

SELECT

VCC.

T

HIS WILL HIGHLIGHT THE

VCC

NET

NOTE:

T

HE BOX TO THE RIGHT WILL HIGHLIGHT AND JUMP TO A PARTICULAR COMPONENT

.

T

HE

VCC

NET IS HIGHLIGHTED AND THERE ARE THREE

‘

RATSNEST

’

WIRES THAT NEED TO BE CONNECTED

.

M

AKE THE CONNECTIONS TO CONNECT ALL THE

VCC’

S TOGETHER

37

W

HEN THE ROUTING IS COMPLETE

,

THERE SHOULD BE NO MORE

‘

RATSNEST

’

WIRES

W

E MUST RUN A

DRC (DESIGN RULE CHECK)

TO MAKE SURE THERE ARE NO ERRORS

.

C

LICK

TOOLS

>

D

ESIGN RULE CHECK

U

NCHECK THE BOX TO CREATE A REPORT FILE

C

LICK

R

UN

D

ESIGN

R

ULE

C

HECK

38

C

HANGE THE

L

AYER

S

ET

BACK TO

ALL

LAYERS

AND VIEW THE ENTIRE BOARD

.

A

S YOU CAN SEE

,

WE HAVE A LOT OF WASTED AREA

,

SO THIS GIVES US A CHANCE TO RESIZE THE BOARD

C

LICK AND DRAG THE PINK LINE TO THE RIGHT TO THE LEFT

,

LEAVING ABOUT

50

MILS SPACING BETWEEN THE PINK LINE AND THE

39

N

OTICE THE DIMENSIONS ARE AUTOMATICALLY FIXED TO THE NEW DISTANCE BETWEEN THE ARROWS

R

EPEAT THIS PROCESS WITH THE BOTTOM PINK LINE

T

HE BOARD SHOULD LOOK SOMETHING LIKE THIS

.

40

C

LICK

D

ESIGN

>

B

OARD

S

HAPE

>

D

EFINE FROM SELECTED OBJECTS

T

HE BOARD SHOULD NOW BE RESIZED TO THE NEW DIMENSIONS

41

Cleaning Up The Design

N

OW WE SHOULD CLEAN UP THE DESIGN

.

T

HE TOP OVERLAY

(

SILKSCREEN

)

ARE OVERLAPPING

VIA

S SO THEY WONT SHOW UP WELL

,

THE FONTS ARE TOO BIG

,

AND THE SPACING IS TOO CLOSE TOGETHER

R

IGHT CLICK ON ANY OF THE TOP OVERLAY

(

SUCH AS

D1)

AND CLICK

‘F

IND

S

IMILAR

O

BJECTS

42

Y

OU CAN SEE THAT ALL THE COMPONENT

DESIGNATORS ARE SELECTED

,

AND NOTHING ELSE

T

HE

PCB

INSPECTOR SHOWS THAT

99

OBJECTS ARE SELECTED

C

HANGE THE

‘T

EXT

K

IND

’

FROM

‘S

TROKE

F

ONT

’

TO

‘T

RUE

T

YPE

’

T

HE CHANGES ARE IMMEDIATELY MADE AND ALL

99

DESIGNATORS ARE CHANGED FROM STROKE FONT TO TRUE TYPE FONT

.

43

P4

AND

P5

ARE NOT VERY INTUITIVE TO THE END USER AND SHOULD PROBABLY BE CHANGED TO SOMETHING MORE DESCRIPTIVE

.

A

LSO

,

THE

8-

BIT

LED

DISPLAY CAN ALSO BE CHANGED TO

B

IT

0,

B

IT

1,

ETC

…

OR

1,2,4,8,…

SO A USER CAN EASILY ADD THE BINARY NUMBERS

G

O BACK TO THE SCHEMATIC

,

AND CHANGE

P5

TO

‘LED

INPUT’

C

HANGE

P1

TO

PORTB

C

HANGE

P4

TO

PORTD

C

HANGE

P2

TO

PORTC

C

HANGE

P3

TO

ISP

(I

N CIRCUIT SERIAL PROGRAMMING

)

C

HANGE

D9

TO

TX

C

HANGE

D10

TO

RX

44

C

LICK

DESIGN

>

U

PDATE

PCB

D

OCUMENT

D

EV

B

OARD

A

S A RESULT OF CHANGING THE COMPONENT NAMES

,

SOME NETS CHANGED ALSO

.

A

PPLY ALL CHANGES EXCEPT ADDING THE ROOM

T

HE CHANGES HAVE TAKEN PLACE AND NOW WE EACH CONNECTOR IS MORE DESCRIPTIVE

45

Y

OU CAN MAKE THE FONT LARGER OR IN BOLD

,

OR CHANGE THE FONT ITSELF IF YOU WANT TO

,

JUST DOUBLE CLICK THE TEXT TO BRING UP THE MENU

T

HESE CONNECTORS WILL HAVE PIN HEADERS ON THEM ONCE ASSEMBLED

,

SO THE

P

IN

1

INDICATOR WITH THE RECTANGULAR PAD WILL BE INVISIBLE TO US

.

W

E NEED TO ADD A BETTER

P

IN

1

INDICATOR

.

C

LICK THE PLACE ARC BY EDGE

P

LACE AN ARC ANYWHERE ON THE BOARD

D

OUBLE CLICK ON THE ARC TO GET THE PROMPT BELOW

,

CHANGE

:

R

ADIUS

=

5

MIL

W

IDTH

=

10

MIL

S

TART

A

NGLE

=

E

ND

A

NGLE

=

0

46

C

OPY

&

P

ASTE THE ARC

(

DOT

)

AND PLACE NEXT TO THE

P

IN

1’

S FOR THE

10

PIN HEADERS

W

E SHOULD CREATE TWO NEW BOARD LAYER SETS

.

O

NE WHERE ONLY ITEMS ON THE

TOP

OF THE BOARD ARE VISIBLE

O

NE WHERE ITEMS ON THE

BOT

OF THE BOARD ARE VISIBLE

C

LICK THE

‘LS’

AT THE BOTTOM OF THE SCREEN AND CLICK

47

C

LICK

‘N

EW

S

ET

’

IN THE BOTTOM LEFT

C

LICK

‘M

AKE

E

MPTY

N

AME THE SET

‘TOP

BOARD’

C

HECK THE FOLLOWING BOXES

:

T

OP

L

AYER

T

OP

O

VERLAY

48

C

REATE ANOTHER NEW SET

CALLED

‘BOT

BOARD’

C

HECK THE

‘V

IEW FROM BOTTOM SIDE

’

C

HECK THE FOLLOWING BOXES

:

T

OP

L

AYER

T

OP

O

VERLAY

M

ULTI

-L

AYER

S

ELECT THE

TOP

BOARD

FROM THE LAYER SET

.

49

T

HIS IS THE BEST VIEW TO MOVE THE TOP

OVERLAY

/

SILKSCREEN LAYERS AROUND TO MAKE SURE IT WILL LOOK GOOD WHEN YOU ARE DONE

.

NOTE:

Y

OU SHOULD AVOID THE HOLES WITH THE TOP OVERLAY

,

BUT DO NOT WORRY IF THE TOP OVERLAY IS ON TOP OF A TRACE

50

T

HIS IS ALSO THE TIME WHERE YOU SHOULD OPTIMIZE YOUR TRACES

.

T

HE TRACE ON THE TOP IMAGE LOOKS SILLY AND WAS PROBABLY DONE BECAUSE OF OPTICAL INTERFERENCE WITH THE BOTTOM LAYER

V

IEWING

ONLY

THE TOP LAYER CAN HELP SPOT ERRORS EASILY AND MAKE A CLEAN AND PROFESSIONAL LOOKING

PCB

S

ET THE ACTIVE LAYER SET TO THE

BOT

LAYER

YOU MADE

51

T

HE IMAGE TO THE LEFT SHOWS A

DRC

ERROR BECAUSE THE POLARITY MARKING FOR THE CAPACITORS ARE TOO CLOSE TOGETHER

.

T

HIS IS NOT A REAL ERROR AND WE DON

’

T CARE ABOUT IT

T

HE IMAGE ON THE RIGHT DOES NOT FLAG FOR AN ERROR

,

BUT THE BOTTOM OVERLAY FOR

C1

WILL NOT SHOW UP PROPERLY BECAUSE OF THE LOCATION OF THE VIA

.

D

OES ANYONE NOTICE ANYTHING ELSE WRONG WITH THE IMAGE TO THE RIGHT

???

52

O

UR BOARD LOOKS

OK,

BUT THERE IS A LOT OF UNUSED SPACE

W

E WILL ADD WHAT IS CALLED A

‘

COPPER POUR

’

OR

‘

POLYGON POUR

’

TO FILL IN THE EMPTY AREAS

C

LICK THE POLYGON PLANE ICON AS SHOWN TO THE RIGHT

53

C

LICK ABOUT

50-100

MILS AWAY FROM THE EACH CORNER AND THEN RIGHT CLICK

T

HIS WILL BEGIN THE POLYGON CALCULATION AND PLACEMENT

.

NOTE:

F

OR LARGE DESIGNS THIS CAN TAKE HOURS

N

OTICE HOW THE POLYGON POUR WILL AVOID A NET THAT IS DIFFERENT THAN THE NET ASSIGNED TO IT

.

54

O

N NETS THAT THERE IS A CONNECTION

(GND),

YOU CAN SEE IT HANDLES IT EXACTLY THE SAME AS ANY OTHER NET

,

BUT HAS A FEW SHORT CONNECTORS THAT CONNECT THE PAD

/

HOLE TO THE POUR

R

EPEAT THIS PROCESS ON THE BOTTOM LAYER OF THE BOARD

,

ALSO CONNECTING TO

GND

T

HAT

’

S THE

PCB

BASICALLY FINISHED