NR8576 Series
NIPPON PRECISION CIRCUITS INC.
Real-time Clock Modules
OVERVIEW
The NR8576 Series devices are serial-interface type real-time clock module ICs with built-in crystal oscillator elements. They feature timer counter cir-cuits that keep track of time from the current second to the current year, automatic leap-year adjustment, and a supply voltage detect function. Also, a 32.768 kHz/1 Hz select output function is incorporated for independent hardware control. They are available in compact 14-pin SOPs (NR8576A×) and miniature 18-pin SOPs (NR8576B×).
FEATURES
■ Crystal oscillator element built-in for
adjustment-free use
■ Timer counters for second, minute, hour, day, day
of the week, month, and year
■ 2.5 to 5.5 V operating voltage range
■ 1.7 ± 0.3 V supply voltage detection threshold ■ 1.0 µA at 3.0 V (typ) current consumption ■ Automatic leap-year calendar adjustment ■ 32.768 kHz and 1 Hz output selectable ■ Package
• 14-pin SOP (NR8576A×) • 18-pin SOP (NR8576B×)
SERIES CONFIGURATION
PINOUTS
14-pin SOP
18-pin SOP
Device Package Frequency deviation NR8576AA 14-pin SOP 5 ± 12 ppm NR8576AB 14-pin SOP 5 ± 23 ppm NR8576BA 18-pin SOP 5 ± 12 ppm NR8576BB 18-pin SOP 5 ± 23 ppm 1 CE 2 N.C 3 VSS 4 N.C 5 N.C 6 FOUT 7 10 9 8 14 13 12 11 FSEL WR FOE N.C N.C VDD CLK DATA
NR8576A
1 CE 2 N.C 3 VSS 4 N.C 5 N.C 6 FOUT 7 16 17 18 12 13 14 15 FSEL WR FOE N.C N.C VDD CLK DATA 8 11 N.C N.C N.C N.C 10 9NR8576B
查询NR8576AA供应商
PACKAGE DIMENSIONS
Unit: mm 14-pin SOP 1.27 3.2 0.1 0.10 0.05 5.0 0 10 0.35 0.1 0.15 10.1 0.2 0.6 0.2 7.4 0.2 18-pin SOP 1.27 1.8 0.1 0.05 0.05 5.4 7.8 0.2 0 10 0.4 0.1 0.15 11.4 0.2 0.6 0.2BLOCK DIAGRAM
OSC
Divider
Timer Counter
Shift Register
Voltage
Detect
I/O
Controller
Control
Circuit
VDD VSS DATA CLK CEOutput
Controller
FOUT WR FSEL FOE 32.768kHzNR8576 Series
PIN DESCRIPTION
SPECIFICATIONS
Absolute Maximum Ratings VSS = 0 V
Recommended Operating Conditions V = 0 V
Name I/O Description
VSS – Ground
CE I
Chip enable. HIGH: Enable
LOW: DATA goes high impedance; input on WR, CLK, and DATA stops; and the TM bit is cleared.
FSEL I
FOUT output frequency select. HIGH: 1 Hz
LOW: 32.768 kHz
WR I
DATA input/output control switch. HIGH: Data input mode (RTC write) LOW: Data output mode (RTC read)
FOE I
FOUT output enable control.
HIGH: The frequency selected by FSEL is output on FOUT. LOW: FOUT goes high impedance.
VDD – Supply voltage.
Connect a ≥ 0.1 µF capacitor between VDD and VSS. CLK I System clock input.
Data is input (RTC write mode) and output (RTC read mode) on the rising edge of CLK. DATA I/O Data read and write input/output
FOUT O
Frequency output (output controlled by FOE and frequency selected by FSEL). In 1 Hz output mode, the 1 Hz signal is synchronized to the internal 1 second signal. FOUT output is not affected by the CE signal.
N. C – No connection. Leave open for normal use.
Parameter Symbol Condition Rating Unit
Supply voltage range VDD Ta = 25 °C −0.3 to 7.0 V Input voltage range VIN Ta = 25 °C VSS− 0.3 to VDD + 0.3 V Output voltage range VOUT Ta = 25 °C VSS− 0.3 to VDD + 0.3 V Storage temperature range Tstg −55 to 125 °C
Soldering temperature Tsld 260 °C
Oscillator Characteristics
DC Electrical Characteristics
VSS = 0 V, VDD = 5.0 V ± 10%, Ta = −40 to 85 °C unless otherwise noted
Parameter Symbol Condition Rating Unit
Frequency deviation ∆f/fO Ta = 25 °C,
VDD = 5.0 V
NR8576×A 5 ± 12 ppm NR8576×B 5 ± 23 ppm Frequency temperature characteristic Top Ta = −10 to 70 °C,
VDD = 5.0 V, 25 °C std +10/−120 ppm Frequency voltage characteristic f/V Ta = 25 °C,
VDD = 2.0 to 5.5 V ±2 ppm/V Oscillator start time tSTA Ta = 25 °C, VDD = 2.5 V 3 s
Aging fA
Ta = 25 °C, VDD = 5.0 V,
first year ±5 ppm
Parameter Symbol Condition
Rating
Unit
min typ max
Current consumption IDD1 VDD = 5.0 V CE = VSS, FOE = VSS, FSEL = VDD, FOUT: floating – 1.5 3.0 µA IDD2 VDD = 3.0 V – 1.0 2.0 µA IDD3 VDD = 2.0 V – 0.5 1.0 µA IDD4 VDD = 5.0 V CE = VSS, FOE = VDD, FSEL = VSS, FOUT: 32 kHz output – 4.0 10.0 µA IDD5 VDD = 3.0 V – 2.5 6.5 µA IDD6 VDD = 2.0 V – 1.5 4.0 µA
HIGH-level input voltage VIH CE, FSEL, WR, FOE, CLK, DATA 0.8VDD – – V
LOW-level input voltage VIL CE, FSEL, WR, FOE, CLK, DATA – – 0.2VDD V
Input OFF leakage current IOFF CE, FSEL, WR, FOE, CLK;
VIN = VDD or VSS – – 0.5 µA
HIGH-level output voltage
VOH1 VDD = 5.0 V I
OH = −1.0 mA;
DATA, FOUT
4.5 – – V
VOH2 VDD = 3.0 V 2.0 – – V
LOW-level output voltage
VOL1 VDD = 5.0 V I
OL = 1.0 mA;
DATA, FOUT
– – 0.5 V
VOL2 VDD = 3.0 V – – 0.8 V Output load fanout N/CL FOUT 2 LSTTL/30 pF max.
Output leakage current
IOZH VOUT = 5.5 V; DATA, FOUT −1.0 – 1.0 µA IOZL VOUT = 0 V; DATA, FOUT −1.0 – 1.0 µA Supply voltage detect
NR8576 Series AC Characteristics
VDD = 3.0 V, VSS = 0 V, Ta = 25 °C unless otherwise noted
Parameter Symbol
Rating
Unit VDD = 5 V ± 10% VDD = 3 V ± 10%
min max min max
CLK clock period tCLK 0.75 7800 1.5 7800 µs CLK LOW-level pulsewidth tCLKL 0.375 3900 0.75 3900 µs CLK HIGH-level pulsewidth tCLKH 0.375 3900 0.75 3900 µs CE setup time tCES 0.375 3900 0.75 3900 µs
CE hold time tCEH 0.375 – 0.75 – µs
CE enable time tCE – 0.9 – 0.9 s
Write data setup time tSD 0.1 – 0.2 – µs Write data hold time tHD 0.1 – 0.1 – µs
WR setup time tWRS 100 – 100 – ns
WR hold time tWRH 100 – 100 – ns
DATA output delay time tDATD – 0.2 – 0.4 µs DATA output floating time tDZ – 0.1 – 0.2 µs
Clock rise time tr1 – 50 – 100 ns
Clock fall time tf1 – 50 – 100 ns
FOUT rise time (CL = 30 pF) tr2 – 100 – 200 ns FOUT fall time (CL = 30 pF) tf2 – 100 – 200 ns
Disable time (CL = 30 pF) tHZ – 100 – 200 ns tLZ – 100 – 200 ns Enable time (CL = 30 pF) tZH – 100 – 200 ns tZL – 100 – 200 ns
FOUT duty cycle (CL = 30 pF) Duty 40 60 40 60 %
Timing Diagrams Data read Data write WR CE CLK DATA tCE tWRS tCES tCLKH tCLK tDATD tCLKL tf1 tr1 tDZ tCEH tRCV tWRH WR CE CLK DATA tCE tWRS tCES tCLKH tCLK tSD tCLKL t f1 tr1 tCEH tRCV tWRH tHD
NR8576 Series
FOUT
Disable/Enable
Note that FOE and FSEL do not have chatter elimination circuits. Consequently, switching either FOE or FSEL during 32 kHz mode operation may generate chatter noise on the FOUT output. Also, note that the 1 Hz and 32 kHz oscillators are not synchronized to each other, so switching intervals shortens the duty cycle. Accordingly, a wait time (≥ chattering time + output frequency period) should be incorporated when switching intervals. FOUT tr2 tH t tf2 10% 50% 90% Duty= ttHX 100(%) FOE tHZ tZH 10% 50% 90% 50% FOUT FOE tLZ tZL 10% 50% 90% 50% FOUT
■ Automatic long/short month and leap-year adjustment ■ 24-hour time display
■ LSB first write and read data
1. * bit: Optional write bits.
2. FDT bit: Supply voltage detect bit
• The FDT bit is set to 1 when the voltage between VDD and VSS falls below 1.7 ± 0.3 V.
• The FDT bit is reset to 0 for data reads longer than 48 bits. Note that the FDT bit is not reset to 0 for data reads of 47 bits or less.
• The read/write data bits should be should be set to 0. After the supply voltage is applied, the FDT bit should be set to 0.
FDT S40 S20 S10 S8 S4 S2 S1
∗ mi40 mi20 mi10 mi8 mi4 mi2 mi1
h20 h10 h8 h4 h2 h1 ∗ ∗ w1 w2 w4 ∗ d20 d10 d8 d4 d2 d1 ∗ ∗
∗ ∗ mo10 mo8 mo4 mo2 mo1
TM
y80 y40 y20 y10 y8 y4 y2 y1
MSB LSB Second ( 0 to 59 ) Minute ( 0 to 59 ) Hour ( 0 to 23 ) Week ( 1 to 7 ) Day ( 1 to 31 ) Month ( 1 to 12 ) Year ( 0 to 99 ) VDD CE VDET FDT (READ MODE) Detected Pulse 0.5 second 0.5 second
NR8576 Series Data Read
Data is output when WR is LOW and CE is HIGH. Time and calendar data is loaded into shift registers on the first rising edge of the clock CLK, and the sec-onds’ digit LSB is output on DATA.
The data is then loaded and shifted in the sequence second, minute, hour, week, day, and month on the rising edge of CLK, and output on DATA. The output data is valid after 52 rising edges of the clock; data input after 52 cycles does not alter the first 52 bits of valid data. WR CE CLK DATA S1 second year FDT S40 S20 S10 S8 S4
S2 y8 y10 y20 y40 y80
1 2 3 52 53 54 54+n
OUTPUT MODE
NON CHANGE OUTPUT DATA
Within the 52 cycles of valid data, data already input can be output if there is a falling edge of CE after the corresponding number of cycles. For example, the data comprising the second-to-week is output is CE goes LOW after 28 clock cycles.
For continuous data reads, a wait time (tRCV) is required before the next data cycle if CE has gone LOW.
Note that if an update operation (a 1 s carry) occurs during a data read, an error of −1 s in the read data is generated.
The data read time should be completed after tCE≤ 0.9 s.
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome
Data is input when WR is HIGH and CE is HIGH. The seconds’ digit signal to the timer counter stops on the first falling edge of CLK and the counter remains stopped until the next rising edge of CE. The 1 Hz to 128 Hz frequency divider step counters are reset during the interval between the first and second rising edges of CLK.
The data is then input on DATA into the shift regis-ter, starting with seconds’ digit LSB synchronized with the rising edge of CLK.
After the final data is input into the shift register fol-lowing 52 cycles, the shift register contents are
trans-WR CE DATA S1 second year FDT S40 S20 S10 S8 S4
S2 y8 y10 y20 y40 y80
INPUT MODE
ferred to the timer counters. Note that a data write must contain 52 bits of input data. If CE goes LOW before 52 bits are input, the input data is invalid. If the input data exceeds 52 bits, data from the 53rd bit is ignored (the first 52 bits remain valid).
The data write time should be completed after tCE≤ 0.9 s.
If a data read occurs immediately after a data write, a wait time (tRCV) is required if CE has gone LOW. Note that writing null data will cause incorrect oper-ation. All bits must be valid data bits.
