Page 1 of 14
1. VHDL Code For Half Adder By Data Flow Modelling
library ieee;
use ieee.std_logic_1164.all; entity half_adder is
port(a,b: in bit;s,c: out bit); end half_adder;
architecture half_adder of half_adder is begin
s<=(a xor b); c<=(a and b); end half_adder;
2. VHDL Code For Full Adder By Data Flow Modelling
library ieee;use ieee.std_logic_1164.all; entity full_adder is
port(a,b,c: in bit;sum,carry: out bit); end full_adder;
architecture full_adder of full_adder is begin
sum<=((a xor b) xor c);
carry<=((a and b) or (b and c) or (c and a)); end full_adder;
3. (a) VHDL Code For Half Subtractor By Data Flow Modelling
library ieee;use ieee.std_logic_1164.all; entity half_subtractor is
port(a,b: in bit; difference,borrow: out bit); end half_subtrator;
architecture half_subtractor_dfm of subtractor is begin
difference<=(a xor b); borrow<=((not a) and b); end half_subtractor_dfm;
Page 2 of 14
3. (b) VHDL Code For Full Subtractor By Data Flow Modelling
library ieee;
use ieee.std_logic_1164.all; entity full_subtractor is
port(a,b,previous_borrow: in bit; difference,next_borrow: out bit); end full_subtractor;
architecture full_subtractor_dfm of full_subtractor is begin
difference<=((a xor b) or (b xor previous_borrow) or (a xor previous_borrow)); next_borrow<=(((not a) and (b or previous_borrow)) or (b and previous_borrow)); end full_subtractor_dfm;
4. VHDL Code For BCD To Decimal Decoder By Data Flow Modelling
library ieee;use ieee.std_logic_1164.all; entity bcd_to_decimal is
port(a,b,c,d: in bit; e: out bit_vector(0 to 9)); end bcd_to_decimal;
architecture bcd_to_decimal_dfm of bcd_to_decimal is begin
e(0)<=((((not a) and (not b)) and (not c)) and (not d)); e(1)<=((((not a) and (not b)) and (not c)) and d); e(2)<=(((not b) and c) and (not d));
e(3)<=(((not b) and c) and d); e(4)<=((b and (not c)) and (not d)); e(5)<=((b and (not c)) and d); e(6)<=((b and c) and (not d)); e(7)<=((b and c) and d); e(8)<=(a and (not d)); e(9)<=(a and d);
Page 3 of 14
5. VHDL Code For Binary to Gray Code Converter By Data Flow Modelling
library ieee;use ieee.std_logic_1164.all; entity binary_to_gray is
port(b0,b1,b2,b3: in bit;g0,g1,g2,g3: out bit); end binary_to_gray; architecture b_t_g of binary_to_gray is begin g3<=b3; g2<=b3 xor b2; g1<=b2 xor b1; g0<=b1 xor b0; end b_t_g;
6. VHDL Code For Gray to Binary Code Converter By Data Flow Modelling
library ieee;use ieee.std_logic_1164.all; entity gray_to_binary is
port(g0,g1,g2,g3: in bit;b0,b1,b2,b3: out bit); end gray_to_binary; architecture g_t_b of gray_to_binary is begin b3<=g3; b2<=g3 xor g2; b1<=(g3 xor (g2 xor g1));
b0<=(g3 xor (g2 xor (g1 xor g0))); end;
7.
VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling
library ieee;
use ieee.std_logic_1164.all; entity bcd_to_excess_3 is
port(b0,b1,b2,b3: in bit; e0,e1,e2,e3: out bit); end bcd_to_excess_3;
architecture bcd_to_excess_3_dfm of bcd_to_excess_3 is begin
e3<=((b3 or (b2 and b0)) or (b2 and b1));
e2<=(((not b2) and b0) or ((not b0) and (b1 xor b2))); e1<=(b1 xnor b0);
e0<=(not b0);
Page 4 of 14
8. (a) VHDL Code For 4×1 Multiplexer Using IF-ELSE Statements
library ieee;
use ieee.std_logic_1164.all; entity mux_4_1 is
port(s: in bit_vector(0 to 1); d: in bit_vector(0 to 3); y: out bit); end mux_4_1;
architecture mux_4_1_behavioural_if_else of mux_4_1 is begin process(s,d) begin if s="00" then y<=d(0); elsif s="01" then y<=d(1); elsif s="10" then y<=d(2); else y<=d(3); end if; end process; end mux_4_1_behavioural_if_else;
8. (b) VHDL Code For 4×1 Multiplexer Using CASE Statements
library ieee;use ieee.std_logic_1164.all; entity mux_4_1 is
port(s: in bit_vector(0 to 1); d: in bit_vector(0 to 3); y: out bit); end mux_4_1;
architecture mux_4_1_behavioural_case of mux_4_1 is begin process(s,d) begin case s is when "00" => y<=d(0); when "01" => y<=d(1); when "10" => y<=d(2); when others => y<=d(3); end case;
end process;
Page 5 of 14
9. VHDL Code For 2×4 Decoder By Data Flow Modelling
library ieee;
use ieee.std_logic_1164.all; entity decoder_2_4 is
port(a,b,e: in bit; d0,d1,d2,d3: out bit); end decoder_2_4;
architecture decoder_2_4_dfm of decoder_2_4 is begin
d0<= (((not a) and (not b)) and e); d1<= (((not a) and b) and e); d2<= ((a and (not b)) and e); d3<= ((a and b) and e); end decoder_2_4_dfm;
10.
VHDL Code For 2 Bit Multiplier By Data Flow Modelling
library ieee;
use ieee.std_logic_1164.all; entity multiplier_2_bit is
port(a: in bit_vector(1 downto 0);b: in bit_vector(1 downto 0); d: out bit_vector(3 downto 0));
end multiplier_2_bit;
architecture multiplier_2_bit_dfm of multiplier_2_bit is signal c: bit;
begin
d(0)<=(a(0) and b(0));
d(1)<=((a(1) and b(0)) xor (a(0) and b(1))); c<=((a(1) and b(0)) and (a(0) and b(1))); d(2)<=((a(1) and b(1)) xor c);
d(3)<=((a(1) and b(1)) and c); end multiplier_2_bit_dfm;
11.
VHDL Code For 2 Bit Comparator By Data Flow Modelling
library ieee;
use ieee.std_logic_1164.all; entity comparator_2_bit is
port(a,b: in bit_vector(1 downto 0); y: out bit_vector(2 downto 0)); end comparator_2_bit;
architecture comparator_2_bit_dfm of comparator_2_bit is begin
y(0)<= (((a(1) and (not b(1))) or (a(1) and a(0) and (not b(0)))) or ((not b(1)) and a(0) and (not b(0))));
y(1)<= ((((not a(1)) and b(1)) or ((not a(1)) and (not a(0)) and b(0))) or (b(1) and (not a(0)) and a(0))); y(2)<= ((a(1) xnor b(1)) and (a(0) xnor b(0)));
Page 6 of 14
12.
VHDL Code For Half Adder by Structural Modelling
library ieee;
use ieee.std_logic_1164.all; entity half_adder is
port(a,b: in bit; sum,carry: out bit); end half_adder;
architecture half_adder_struct of half_adder is component xor1 is
port(p,q: in bit; r: out bit); end component;
component and1 is port(u,v: in bit; w: out bit); end component;
begin
x1:xor1 port map(a,b,sum); x2:and1 port map(a,b,carry); end half_adder_struct; entity xor1 is
port(p,q: in bit; r: out bit); end xor1;
architecture xor_1_dfm of xor1 is begin
r<=p xor q; end xor_1; entity and1 is
port(u,v: in bit; w: out bit); end and1;
architecture and_1_dfm of and1 is begin
w<=u and v; end and_1;
Page 7 of 14
13.
VHDL Code For 4-bit Parallel Adder by Structural Modelling
library ieee;
use ieee.std_logic_1164.all; entity full_adder_4_bit is
port(a,b: in bit_vector(3 downto 0); carry_in: in bit;
sum: out bit_vector(3 downto 0); carry_out: out bit); end;
architecture structural_4_bit_full_adder of full_adder_4_bit is component full_adder
port(x,y,zin: in bit; s,c: out bit); end component;
signal carry: bit_vector(4 downto 0); begin
carry(0)<=carry_in;
GK:for i in 3 downto 0 generate
FA:full_adder port map(a(i),b(i),carry(i),sum(i),carry(i+1)); end generate GK;
carry_out<=carry(4); end;
entity full_adder is
port(p,q,r:in bit; u,v:out bit); end;
architecture data_flow_full_adder of full_adder is begin
u<=((p xor q) xor r);
v<=((p and q) or (q and r) or (r and p)); end;
14.
VHDL Code For 4-Bit Parallel Subtractor by Structural Modelling
library ieee;
use ieee.std_logic_1164.all; entity full_subtractor_4_bit is
port(a,b: in bit_vector(3 downto 0); borrow_in: in bit;
difference: out bit_vector(3 downto 0); borrow_out: out bit); end full_subtractor_4_bit;
architecture full_subtractor_4_bit_struct of full_subtractor_4_bit is component full_subtractor is
port(x,y,zin: in bit; diff,zout: out bit); end component;
signal borrow: bit_vector(4 downto 0); begin
borrow(0)<=borrow_in;
GK: for i in 3 downto 0 generate
Page 8 of 14 end generate GK;
borrow_out<=borrow(4);
end full_subtractor_4_bit_struct; entity full_subtractor is
port(r,s,t: in bit; u,v: out bit); end full_subtractor;
architecture full_subtractor_dfm of full_subtractor is begin
u<=((r xor s) xor t);
v<=(((not r) and t) or ((s and t) or ((not r) and s))); end full_subtractor_dfm;
15.
VHDL Code For 4×1 Multiplier By Data Flow Modelling
library ieee;
use ieee.std_logic_1164.all; entity mux_4_1 is
port(s: in bit_vector(1 downto 0);d: in bit_vector(3 downto 0); y: out bit); end;
architecture mux_4_1_dfm of mux_4_1 is begin
y<=d(0) when s="00" else d(1) when s="01" else d(2) when s="10" else d(3);
end;
16.
VHDL Code For 2×4 Decoder By Behavioral Modelling
library ieee;
use ieee.std_logic_1164.all; entity decoder_2_4 is
port(a: in bit_vector(0 to 1); d: out bit_vector(0 to 3)); end decoder_2_4;
architecture decoder_2_4_behavioural of decoder_2_4 is begin
process(a) begin
if a="00" then d<="0001"; elsif a="01" then d<="0010"; elsif a="10" then
Page 9 of 14 d<="0100"; else d<="1000"; end if; end process; end decoder_2_4_behavioural;
17. (a)VHDL Code For JK Flip Flop(Asynchronous) By Behavioral Modelling
library ieee;use ieee.std_logic_1164.all; entity J_K_flip_flop is
port(J,K,reset,clock: in bit; q: inout bit; qbar: out bit); end J_K_flip_flop;
architecture asynchronous_reset_J_K_flip_flop_behavioural of J_K_flip_flop is begin
process(clock,reset) begin
if reset='1' then q<='0';
elsif clock='1' and clock'event then q<=((J and (not q)) or ((not K) and q)); end if;
end process;
end asynchronous_reset_J_K_flip_flop_behavioural;
17. (b) VHDL Code For JK Flip Flop(Synchronous) By Behavioral Modelling
library ieee;use ieee.std_logic_1164.all; entity J_K_flip_flop is
port(J,K,clock,reset: in bit; q: inout bit; qbar: out bit); end J_K_flip_flop;
architecture synchronous_reset_J_K_flip_flop_behavioural of J_K_flip_flop is begin
process(clock) begin
if clock='0' and clock'event then if reset='1' then
q<='0'; else
q<=(((J and (not q)) or ((not K) and q)); end if;
end if;
end process; qbar<=(not q);
Page 10 of 14
18. (a)VHDL Code For D Flip Flop(Asynchronous) By Behavioral Modelling
library ieee;
use ieee.std_logic_1164.all; entity D_flip_flop is
port(d,clock,reset: in bit; q: inout bit; qbar: out bit); end D_flip_flop;
architecture asynchronous_reset_D_flip_flop_behavioural of D_flip_flop is begin
process(clock,reset) begin
if reset='1' then q<='0';
elsif clock='0' and clock'event then q<=d;
end if;
end process; qbar<=(not q);
end asynchronous_reset_D_flip_flop_behavioural;
18.(b)VHDL Code For D Flip Flop(Synchronous) By Behavioral Modelling
library ieee;use ieee.std_logic_1164.all; entity D_flip_flop is
port(d,clock,reset: in bit; q: inout bit; qbar: out bit); end D_flip_flop;
architecture synchronous_reset_D_flip_flop_behavioural of D_flip_flop is begin
process(clock) begin
if clock='0' and clock'event then if reset='1' then q<='0'; else q<=d; end if; end if; end process; qbar<=(not q); end synchronous_reset_D_flip_flop_behavioural;
Page 11 of 14
19. (a) VHDL Code For T Flip Flop(Asynchronous) By Behavioral Modelling
library ieee;use ieee.std_logic_1164.all; entity T_flip_flop is
port(T,reset,clock: in bit; q: inout bit; qbar: out bit); end T_flip_flop;
architecture asynchronous_reset_T_flip_flop_behavioural of T_flip_flop is begin
process(clock,reset) begin
if reset='1' then q<='0';
elsif clock='1' and clock'event then q<=((T and (not q)) or ((not T) and q)); end if;
end process;
end asynchronous_reset_T_flip_flop_behavioural;
19.(b) VHDL Code For T Flip Flop(Synchronous) By Behavioral Modelling
library ieee;use ieee.std_logic_1164.all; entity T_flip_flop is
port(T,clock,reset: in bit; q: inout bit; qbar: out bit); end T_flip_flop;
architecture synchronous_reset_T_flip_flop_behavioural of T_flip_flop is begin
process(clock) begin
if clock='0' and clock'event then if reset='1' then
q<='0'; else
q<=(((T and (not q)) or ((not T) and q))); end if;
end if;
end process; qbar<=(not q);
Page 12 of 14
20. VHDL Code For 3 Bit Counter By Behavioral Modeling
library ieee;
use ieee.numeric_std.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter_3_bit is
port(clock,reset: in bit; z: out unsigned(0 to 2)); end counter_3_bit;
architecture counter_3_bit_behavioural of counter_3_bit is begin
process(clock,reset)
variable temp: unsigned(0 to 2):=(others=>'0'); begin
if reset='1' then temp:=(others=>'0');
elsif clock='0' and clock'event then temp:=temp+1;
end if; z<=temp; end process;
end counter_3_bit_behavioural;
21. VHDL Code For Shift Register By Behavioral Modelling
library ieee;use ieee.std_logic_1164.all; entity shift_register is
port(clock,serial_input: in bit; serial_output: out bit); end shift_register;
architecture shift_right_register_8_bit_behavioural of shift_register is signal temp: bit_vector(7 downto 0);
begin
process(clock) begin
if clock='1' and clock'event then serial_output<=temp(0);
for i in 7 downto 1 loop temp(i-1)<=temp(i); end loop; temp(7)<=serial_input; end if; serial_output<=temp(7); end process; end shift_right_register_8_bit_behavioural;
Page 13 of 14
22. (a) VHDL Code For State Machine Modeling (Mealey) By Behavioral Modeling.
library ieee;use ieee.std_logic_1164.all; entity mealy_fsm is
port(a,clock: in bit; z: out std_logic); end mealy_fsm;
architecture mealy_fsm_behavioural of mealy_fsm is type mealy_type is(st0,st1,st2,st3);
signal p_state,n_state: mealy_type; begin seq_part: process(clock) begin if clock='0' then p_state<=n_state; end if;
end process seq_part; comb_part:process(p_state,a) begin case p_state is when st0 => if a='1' then z<='1'; n_state<=st3; else z<='0'; end if; when st1 => if a='1' then z<='0'; n_state<=st0; else z<='1'; end if; when st2 => if a='0' then z<='0'; else z<='1'; n_state<=st1; end if; when st3 => z<='0'; if a='0' then n_state<=st2; else n_state<=st1;
Page 14 of 14 end if;
end case;
end process comb_part; end mealy_fsm_behavioural;
23. (b) VHDL Code For State Machine Modeling (Moorey) By Behavioral
Modeling.
library ieee;
use ieee.std_logic_1164.all; entity moore_fsm is
port(a,clock: in bit; z: out std_logic); end moore_fsm;
architecture moore_fsm_behavioural of moore_fsm is type state_type is(st0,st1,st2,st3);
signal moore_state: state_type; begin process(clock) begin if clock='0' then case moore_state is when st0 => z<='1'; if a='1' then moore_state<=st2; end if; when st1 => z<='0'; if a='1' then moore_state<=st3; end if; when st2 => z<='0'; if a='0' then moore_state<=st1; else moore_state<=st3; end if; when st3 => z<='1'; if a='1' then moore_state<=st0; end if; end case; end if; end process; end moore_fsm_behavioural;
