Intel PCI-X to Serial ATA Controller

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Datasheet

Product Features

Warning: Intel Corporation products are not intended for use in life support appliances, devices or systems. Use of a Intel products in such applications without written consent is prohibited.

■ Four SATA Channels at 1.5 Gb/s

■ Serial ATA: High speed Serialized AT Attachment Specification, Revision 1.0e Compliant

■ 64-bit/133 MHz PCI-X Bus. Backwards compatible to 32-bit/33 MHz and 64-bit/66 MHz

■ Compatible with Existing Operating Systems

■ Supports Native PCI IDE

■ Hot-Plug Drives

■ Supports Master/Slave Mode for Compatibility with Existing Operating Systems

■ Supports SATA Direct Port Access (Master/Master Mode)

■ Independent DMA Masters for Each SATA Channel

■ 3.3 V and 2.5 V Supply, 2.0 W Maximum

Document Number: 273595-004 April 28, 2003

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Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The Intel® 31244 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Intel^® internal code names are subject to change.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

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1.0 General Description

The Intel^® 31244 PCI-X to serial ATA controller (GD31244) is a state-of-the-art, PCI-X-to-Serial ATA Controller with four Serial ATA ports running at 1.5 Gb/s. The device is targeted at embedded applications such as PC motherboards, as well as standalone PCI-X Host Bus Adapter cards and RAID controllers.

The GD31244 is both a PCI-X Bus Master and Slave, which automatically switches modes as required.

As a PCI-X Slave, the device supports:

As a PCI-X Bus Master, this device supports:

This device is compliant with the PCI-X bus operating at up to 64 bits at 133 MHz, resulting in burst data rates of 1064 MBps. The Intel^® 31244 PCI-X to serial ATA controller provides four Serial ATA ports running at 1.5 Gb/s transfer rate, which are compliant to the Serial ATA: High speed Serialized AT Attachment Specification, Revision 1.0e. The GD31244 derives its Serial ATA clocks from an internal PLL, with a reference clock of 37.5 MHz provided externally or from a crystal.

The GD31244 is fully compatible with parallel ATA operating system drivers and software. The chip can be configured in compatibility mode, mapping the PCI-X configuration space to match the x86 standard Primary and Secondary IDE ports. To support both on-board parallel IDE, plus the four Serial ATA ports, the chip can be configured for native PCI-X mode, allowing Plug-and-Play BIOS and operating systems to map the Serial ATA drives to non-conflicting task file and I/O address space.

For higher performance in systems where compatibility is not required, all four channels can be configured as Direct Port Access (DPA).

1.1 References

For more details regarding Serial ATA and PCI, the reader is referred to:

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PCI Local Bus Specification, Revision 2.2

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PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a

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Serial ATA: High speed Serialized AT Attachment Specification, Revision 1.0e

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AT Attachment with Packet Interface - 5 (ATA/ATAPI-5), T13/1321D, Revision 3

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I/O Reads

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Configuration Read

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I/O Writes

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Configuration Write

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Memory Read Bus Cycles

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Single Memory Reads

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Line Memory Reads

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Multiple Memory Reads

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Memory Writes

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Intel 31244 PCI-X to Serial ATA Controller Overview

2.0 Overview

The Intel^® 31244 PCI-X to serial ATA controller is a single-chip solution for a PCI-X-to-Serial ATA Host Bus Adapter (HBA). It accepts host commands through the PCI-X bus, processes them and transmits them to one of four Serial ATA targets. The Intel^® 31244 PCI-X to serial ATA controller supports Serial ATA speeds of 1.5 Gb/s of 8b/10b encoded data, which is equivalent to 150 MB/s of raw data. On the 64-bit PCI-X bus, when run at the maximum frequency of 133 MHz, the Intel^® 31244 PCI-X to serial ATA controller supports a maximum burst transfer rate of 1064 MB/s.

The Intel^® 31244 PCI-X to serial ATA controller may be used to build standalone PCI-X HBA cards (Figure 1) to interface Serial ATA Disk Drives, CD-ROMs, DVD ROMs or Tape drives. The Intel^® 31244 PCI-X to serial ATA controller is completely software compatible with all existing operating systems which support ATA interfaces:

In PC systems, the Intel^® 31244 PCI-X to serial ATA controller can also be configured to provide additional storage capacity to systems already supporting four ATA targets. In non-PC systems, the Intel^® 31244 PCI-X to serial ATA controller may be used as a generic storage controller in servers, RAID subsystems and Network Attached Storage (NAS) systems. The ease-of-use, flexibility, performance and low cost of the Intel^® 31244 PCI-X to serial ATA controller make it an ideal choice for all of these applications.

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Windows

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Linux

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Unix

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Windows NT

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Solaris

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Other

Figure 1. Block Diagram

Dual Port FIFO and

I/O Transport

Engine PCI-X

64-bit 133 MHz Interface

Serializer

00B Deserializer

Serializer

Deserializer Deserializer

Serializer

Deserializer

TX0P TX0N RX0N RX0P

00B

TX1P TX1N LED0

P_AD(63:0) LED1

LED2 LED3

RX1N RX1P

00B

TX2P TX2N RX2N RX2P

00B

TX3P TX3N RX3N RX3P P_CBE(7:0)

P_PAR P_PAR64 P_FRAME#

P_TRDY#

P_REQ64#

P_IRDY#

P_ACK64#

P_GNT#

P_CLK P_RST#

P_REQ#

P_STOP#

P_DEVSEL#

P_SERR#

P_PERR#

P_INTA#

Serial ATA Transport/Link

Layer

PHY I/F

Layer

PHY I/F

Layer

PHY I/F

Layer

PHY I/F

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2.1 Applications

The Intel^® 31244 PCI-X to serial ATA controller can be used to build a Serial ATA Host Bus Adapter which connects to the PCI-X bus. Control for external activity LEDs, a 37.5 MHz Crystal, a voltage regulator and some external resistors and capacitors are needed.

Figure 2. Quad-Serial ATA Host Bus Adapter

B0418-02

Intel^® 31244 PCI-X to Serial

ATA Controller PCI-X Bus JTAG

P_AD[63:0] VIO VCC

2.5V 3.3V

P_CBE[7:0]

P_PAR P_PAR64 P_FRAME#

CAP0

CAP1

VA1 P_TRDY#

P_REQ64#

P_IRDY#

P_ACK64#

P_GNT#

P_CLK

P_RST#

P_IDSEL P_REQ#

P_STOP#

P_DEVSEL#

P_SERR#

P_PERR#

VCC5REF P_INTA#

TDI TD0

TMS TCK

TRST#

CLKIN

CLKOUT

RBIAS

V18A V18B

Serial ATA Port 0

Connector

Oscillator

Regulator

37.5 MHz

0.1 µF 10 µF

1000 Ω, 1%

CAP2

CAP3

0.1 µF

0.015 µF

2.5V 2.5V

0.01 µF 0.01 µF

18 pF

0.1 µF 10 µF

0.01 µF 0.01 µF

Connector

0.01 µF 0.01 µF 0.01 µF 0.01 µF

Connector

0.01 µF 0.01 µF 0.01 µF 0.01 µF

Connector

0.01 µF 0.01 µF 0.01 µF 0.01 µF RX0P RX0N TX0P TX0N RX1P RX1N TX1P TX1N RX2P RX2N TX2P TX2N RX3P RX3N TX3P TX3N

LED0 LED1 LED2 LED3

VA0

.1µF, 0603, x7R

.1µF, 0603, x7R 22µF, TANT, EIA-A, 6.3V

22µF, TANT, EIA-A, 6.3V

20Ω 0603, 1%

10 µH

10 µH .1µF,

0603, x7R

.1µF, 0603, x7R 22µF, TANT, EIA-A, 6.3V

+

+ 22µF,

TANT, EIA-A, 6.3V

20Ω 0603, 1%

+ +

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2.2 PCI-X Interface

The 64-bit, 133 MHz PCI-X interface is fully compliant with the PCI Local Bus Specification, Revision 2.2 and the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. The PCI-X bus supports up to 1064 MB/s transfer rate of burst data. The Intel^® 31244 PCI-X to serial ATA controller is backwards compatible with 32-bit/33 MHz, 32-bit/66 MHz and 64-bit/66 MHz operation. The PCI logic supports Plug-n-Play operation, which allows hardware and firmware to resolve all setup conflicts for the user. The Intel^® 31244 PCI-X to serial ATA controller supports both slave and master data transfers. The devices responds to the following bus cycles as a slave:

As a master, the Intel^® 31244 PCI-X to serial ATA controller responds to:

During system initialization, the Configuration Manager of the host system reads the configuration space of each PCI-X device. After hardware reset, the Intel^® 31244 PCI-X to serial ATA controller only responds to PCI-X Configuration cycles in anticipation of being initialized by the

Configuration Manager. Each PCI-X device is addressable individually by the use of unique IDSEL signals which, when asserted, indicate that a configuration read or write is occurring to this device. The Configuration Manager reads the setup registers of each device on the PCI-X bus and then, based on this information, assigns system resources to each supported function through Type 0 configuration reads and writes. Type 1 configuration cycles are ignored. This scheme allows the Intel^® 31244 PCI-X to serial ATA controller and its external activity LEDs to be relocated in the memory and I/O space. Interrupts, DMA Channels and other system resources can be reallocated appropriately.

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I/O Reads

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Configuration Read

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I/O Writes

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Configuration Write

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Memory Read Bus Cycles

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Single Memory Reads

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Line Memory Reads

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Multiple Memory Reads

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Memory Writes

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2.3 Serial ATA Interface

Four 1.5 Gb/s Serial ATA ports are located on the Intel^® 31244 PCI-X to serial ATA controller, to support point-to-point connectivity to disk drives, CD ROMs, DVD ROMs or any other Serial ATA target device. Each port is compliant with the “Serial ATA: High speed Serialized AT Attachment Specification, Revision 1.0e. High speed differential duplex serial lines send 8B/10B encoded data to and from the Intel^® 31244 PCI-X to serial ATA controller and the target at a maximum raw data rate of 1.2 Gb/s (150 MB/s). Copies of the targets’ Task File Registers are maintained on the Intel^® 31244 PCI-X to serial ATA controller and transferred as needed to the target. The Serial ATA protocol is software compatible with all existing operating systems that support ATA devices, however, performance and reliability are improved since all data is CRC checked.

2.3.1 Direct Port Access (DPA)

The SATA Direct Port Access architecture allows for independent control of the SATA devices.

Unlike ATA master/slave configuration where only one drive can operate at a time, DPA allows multiple drivers to be accessed concurrently. In addition, each port supports its own DMA channel allowing each port to transfer data independently (between a device and memory).

The DPA mode does change the register layout from PCI IDE. Therefore, legacy device drivers do not support this mode. DPA requires the registers (including the Command Block, Control Block, DMA, and SATA superset) for each drive to be available at all times. Instead of using I/O space, these registers are mapped to a single 4 KB memory mapped block. Each port has 512 Bytes; the remaining 2 KB are for the common port registers. The 4 KB block is mapped using one PCI BAR register.

Figure 3. SATA Unit Register Mapping in Direct Port Access Mode

SATA Port 0 Registers 0

200H 3FCH 400H 5FCH 600H 7FCH SATA Port 3 Registers 800H

9FCH SATA Port 1 Registers

Offset

SATA Port 2 Registers Common Port Registers

1FCH

2 KBytes 512 Bytes

(4 x 512 Bytes) PCI Configuration Space

10H 14H Offset

Base Address Register Upper Base Address Register 0

31

000H

A00H

FFCH

Reserved 1536 Bytes

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2.3.2 Extended Voltage Range

The SATA voltages were designed primarily for a cable connection to the hard drives. In certain applications, such as NAS/SAN enclosures, the hard disk drives (HDD) are connected to a backplane, not a cable (typically in desktop systems). Due to the frequency of the SATA interface, the backplane creates a significant attenuation of the SATA signals. In an effort to simplify system designs, the Intel^® 31244 PCI-X to serial ATA controller offers an extended voltage range to help alleviate the issue. This extended voltage range allows standard SATA HDD to be used with SATA backplanes.

Each SATA transmit channel of the Intel^® 31244 PCI-X to serial ATA controller can be

independently placed into the External Voltage Mode by setting the Extended Voltage Range bit (Bit 14) in the appropriate PHY Feature Register to 1. This causes the SATA transmit channel of the Intel^® 31244 PCI-X to serial ATA controller to operate with this extended voltage range. More information on designing SATA backplanes is available in the Intel^® 31244 PCI-X to Serial ATA Controller Design Guide.

2.3.3 Activity LEDs

Serial ATA interfaces on disk drives, do not include the traditional ATA output, which drives an LED to indicate that the drive is active. The GD31244 compensates for this missing function by adding four LED out-puts. In Master/Slave compatibility mode, LED0 goes LOW to turn on an Activity LED, anytime there is activity on either Channel 0 or Channel 1. Likewise, LED1 goes LOW to turn on an Activity LED, anytime there is activity on either Channel 2 or Channel 3. These two outputs may be wire-ORd together to use one LED for all four ports.

When GD31244 is configured in Direct Port Access mode (DPA_MODE# is LOW), then each port is assigned its own LED as follows:

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Port 0 on LED0

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Port 1 on LED1

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Port 2 on LED2

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Port 3 on LED3

Table 1. Normal Mode (Extended Voltage Range Bit = 0)

Parameter Description Minimum Maximum Units

∆V_OUT TXx output differential peak-to-peak voltage swing 400 600 mVp-p

∆V_IN RXx input differential peak-to-peak voltage swing 325 600 mVp-p

Table 2. Extended Voltage Range (Bit = 1)

Parameter Description Minimum Maximum Units

∆V_OUT TXx output differential peak-to-peak voltage swing 800 1200 mVp-p

∆V_IN RXx input differential peak-to-peak voltage swing 175 1200 mVp-p

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2.4 Serial ROM Interface

In add-in card applications, firmware may be downloaded to the system from a Serial EEPROM or Serial Flash ROM, via the Serial ROM Interface. This industry standard, 4-pin interface, allows any size of device, up to 128 KB, to be connected to the Intel^® 31244 PCI-X to serial ATA controller. This SPI interface was designed for compatibility with an ST Microelectronics* M25P10-A or Atmel*

AT25F1024 device.

Two of the pins are dual purpose to support four LED port activity indicators. This four pin interface is defined as follows:

1. SDI INPUT: Connects to the serial data output (SO) of the Serial EEPROM. Data is shifted out of the EEPROM on the falling edge of SCLK. Customers are recommended to add pads for both a pull-up and a pull-down resistor for possible use in the future.

2. SDO OUTPUT: Connects to the serial data input (SI) of the Serial EEPROM. Data is latched into the Serial EEPROM on the rising edge of SCLK. This is also the activity LED output for Channel 3 when all four LEDs are activated (active LOW).

3. SCLK OUTPUT: Connects to the clock input (SCK) of the Serial EEPROM. This is also the activity LED output for Channel 2 when all four LEDs are activated (active LOW).

4. SCS# OUTPUT: Connects to the chip select input (CS#) of the Serial EEPROM.

2.4.1 JTAG Interface

An IEEE 1149.1 compatible JTAG interface and boundary scan functionality is provided to assist on-board testing of the device. A BSDL test file is provided by Intel.

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Intel 31244 PCI-X to Serial ATA Controller Package Information

3.0 Package Information

3.1 Package Introduction

3.1.1 Signal Pin Descriptions

This section defines the pins and signals.

Table 3. Pin Description Nomenclature

Symbol Description

I Input pin only O Output pin only

I/O Pin can be either an input or output OD Open Drain pin

- Pin must be connected as described

Async Asynchronous. Inputs may be asynchronous relative to all clocks. All asynchronous signals are level-sensitive.

(Configuration Pin)

These pins are used during reset to configure the component.

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3.1.2 Serial ROM Interface Pin Descriptions

The following pins are used for configuring the 4-pin serial ROM interface:

3.1.3 Reference Clock Generation

A 37.5 MHz reference clock with a +/- 100 ppm accuracy is required for proper operation of the Intel^® 31244 PCI-X to serial ATA controller. This can be generated from an external oscillator connected directly to the CLKIN input. Optionally, a 37.5 MHz crystal may be connected between the CLKIN and CLKout pins with a 20 pF capacitor from CLKIN to ground and another from CLKOUT to ground. The following are the crystal characteristics:

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Frequency: 37.5 MHz +/- 100 ppm

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Mode: Fundamental

Table 4. Serial ATA Signals Pin Descriptions

Name Type Count Description

TX0P, TX0N, TX1P, TX1N, TX2P, TX2N, TX3P, TX3N

OUTPUT - Differential High Speed Outputs: These are the differential serial outputs for each channel. When disabled, these outputs are driven to their DC-Bias point.

RX0P, RX0N, RX1P, RX1N, RX2P, RX2N, RX3P, RX3N

INPUT - Differential High Speed Inputs: These are the differential serial inputs for each channel.

CLKOUT OUTPUT - LVTTL: This is connected to one side of the 37.5 MHz crystal.

CLKIN INPUT - LVTTL: This is the reference clock input for the clock multiplier unit at 37.5 MHz. It can be connected to either an external clock source or one side of a crystal.

CLKO Buffered output of the 37.5 MHz clock.

RBIAS INPUT - ANALOG: This pin should be pull-down to ground with a 1000Ω, 1% resistor in order to set the internal termination resistors to 100Ω.

CAP0, CAP1 Analog: An external 0.1µF (+/- 10%) capacitor is connected between these pins to set the Clock Multiplier PLL loop filter response.

LED0, LED1,

LED2, LED3 OUTPUT - LVTTL: These are the Activity LED outputs for channel 0, channel1, channel 2 and channel 3 (active LOW with10 mA maximum sink capability).

Table 5. Serial ROM Interface Pin Descriptions

SDI INPUT - LVTTL with Pull Up: Connects to the serial data output (SDO) of the Serial ROM. Customers are recommended to add pads for both a pull-up and a pull-down resistor for possible use in the future.

SDO (LED3) OUTPUT - LVTTL: Connects to the serial data input (SDI) of the Serial ROM. This is also the activity LED output for Channel 3 when all four LEDs are activated (active LOW).

SCLK (LED2) OUTPUT - LVTTL: Connects to the clock input (SCLK) of the Serial ROM. This is also the activity LED output for Channel 2 when all four LEDs are activated (active LOW).

SCS# OUTPUT - LVTTL with Pull Up: Connects to the chip select input (SCS#) of the Serial ROM.

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Type: “Parallel” resonant

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ESR: 30 Ohms maximum

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Load Capacitance: 20 pF

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Shunt Capacitance: 7 pF

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Drive Level: 500 mW maximum

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Recommended Vendor/Part Number: Fox Electronics, Part number: 278-37.5-8 (This is an HC-49SD surface mountable package.)

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The crystal should be placed near the Intel^® 31244 PCI-X to serial ATA controller and isolated fro m noisy circuits as much as possible.

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Table 6. PCI-X Bus Pin Descriptions (Sheet 1 of 2)

CAP2, CAP3 Analog: An external 0.015µF (+/- 10%) capacitor is connected between these pins to set the PCI PLL loop filter response.

P_ACK64# BIDIRECTIONAL - LVTTL: Indicates that the device has positively decoded its address as the target of the current access and the target is willing to transfer data using the full 64-bit data bus.

P_AD[63:0] BIDIRECTIONAL - LVTTL PCI Address and Data: The address and data lines are multiplexed on these pins. A bus transaction consists of an address phase followed by one or more data phases. P_AD[63:56]

contains the most significant byte and P_AD[7:0] contain the least significant byte.

P_C/BE[7:0]# BIDIRECTIONAL - LVTTL: Command and Byte Enable. The bus command and byte enable signals are multiplexed on these pins. During the address phase, the P_CBE# lines define the bus command. During the data phase, the P_CBE# lines are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data.

P_CLK All PCI bus signals are referenced to this clock.

P_DEVSEL# BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Device Select. This signal is asserted by the target once it has detected its address. As a bus master, the P_DEVSEL# is an input signal to the Intel^® 31244 PCI-X to serial ATA controller indicating whether any device on the bus has been selected. As a bus slave, the Intel^® 31244 PCI-X to serial ATA controller asserts P_DEVSEL# to indicate that it has decoded its address as the target of the current transaction.

P_FRAME# BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Cycle Frame. This signal is driven by the current master to indicate the beginning and duration of a transaction. P_FRAME# is asserted to indicate the start of a transaction and de-asserted during the final data phase.

P_GNT# INPUT - LVTTL. Grant: This signal is asserted by the bus arbiter and indicates to the Intel^® 31244 PCI-X to serial ATA controller that access to the bus has been granted. This is a point-to-point signal and every master has its own GNT#.

P_IDSEL INPUT - LVTTL. Initialization Device Select: This signal is used as a chip select during PCI-X configuration read and write transactions. This signal is provided by the host in PCI-X systems.

P_INTA# OUTPUT - Open Drain Interrupt A: This signal is used to request an interrupt by the Intel^® 31244 PCI-X to serial ATA controller. This is an active low, level triggered interrupt signal.

P_IRDY# BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Initiator Ready. This signal indicates the bus master’s ability to complete the current data phase and is used in conjunction with the target ready (P_TRDY#) signal. A data phase is completed on any clock cycle where both P_IRDY# and P_TRDY# are asserted LOW.

P_PAR BIDIRECTIONAL - LVTTL: Parity. Parity is even across P_AD[31:0] and P_CBE[3:0]# lines. It is stable and valid one clock after the address phase.

For data phases, P_PAR is stable and valid one clock after either P_IRDY#

is asserted on a write or P_TRDY# is asserted on a read.Once P_PAR is valid, it remains valid until one clock after the completion of the current data phase. The master drives P_PAR for address and write data phases; and the target, for read data phases.

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P_PAR64 BIDIRECTIONAL - LVTTL: Parity for 64-bit Accesses. Parity is even across P_AD[63:0] and P_CBE[7:0]# lines. It is stable and valid one clock after the address phase. For data phases, P_PAR64 is stable and valid one clock after either P_IRDY# is asserted on a write or P_TRDY# is asserted on a read.Once P_PAR64 is valid, it remains valid until one clock after the completion of the current data phase. The master drives P_PAR64 for address and write data phases; and the target, for read data phases.

P_PERR# BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Parity Error. This signal is used to report data parity errors during all PCI-X transactions except a Special Cycle. This signal is asserted two clock cycles after the error was detected by the device receiving data. The minimum duration of P_PERR#

is one clock for each data phase where an error is detected. A device cannot report a parity error until it has claimed the access by asserting P_DEVSEL# and completed a data phase.

P_REQ# OUTPUT - LVTTL. Request: This signal indicates to the bus arbiter that the Intel^® 31244 PCI-X to serial ATA controller desires use of the bus.

This is a point-to-point signal and every bus master has its own P_REQ#.

P_REQ64# BIDIRECTIONAL - LVTTL: Indicates the attempt of a 64-bit transaction on the PCI bus. If the target is 64-bit capable, the target acknowledges the attempt with the assertion of P_ACK64#.

P_RST# INPUT - LVTTL Reset: This signal is used to place PCI-X registers, sequencers, and signals into a consistent state. When P_RST# is asserted, all PCI-X output signals will be tri-stated.

P_SERR# OUTPUT - Open Drain with Pull-Up Resistor: System Error. This signal is used to report address parity errors. When an error is detected, P_SERR# is driven LOW for a single PCI-X clock.

P_STOP# BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Stop. This signal is driven by the target to indicate to the initiator that it wishes to stop the current transaction. As a bus slave, P_STOP# is driven by the Intel^® 31244 PCI-X to serial ATA controller to inform the bus master to stop the current transaction. As a bus master, P_STOP# is received by the Intel^® 31244 PCI-X to serial ATA controller to stop the current transaction.

P_TRDY# BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Target Ready. This signal indicates the selected device’s ability to complete the current data phase and is used in conjunction with P_IRDY#. A data phase is completed on any clock cycle where both P_IRDY# and P_TRDY# are asserted LOW.

TEST0 INPUT - LVTTL: Test input. Set LOW for normal operation.

TOUT OUTPUT - Test pin. Do not use.

Table 6. PCI-X Bus Pin Descriptions (Sheet 2 of 2)

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Table 7. Configuration Pin Descriptions

32BITPCI# Pin number A2. This pin controls the state of the “64 bit device” status bit 16, in the PCI-X Status Register. If pulled down, reports a 0, a 32-bit bus. If pulled up, reports 1, a 64-bit device.

DPA_MODE# INPUT - LVTTL: When HIGH or open, selects Master/Slave Mode for software compatibility. When LOW, selects Master-Master mode for high performance.

SSCEN INPUT - When HIGH or Open, this pin enables Spread Spectrum Clock Generation in all four transmit channels.

Table 8. JTAG Pin Descriptions

TDO TEST DATA OUTPUT: is the serial output pin for the JTAG feature.

TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At other times, TDO floats.

The behavior of TDO is independent of P_RST#.

TDI TEST DATA INPUT: is the serial input pin for the JTAG feature. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. This signal has a weak internal pull-up to ensure proper operation when this signal is unconnected.

TCK TEST CLOCK: is an input which provides the clocking function for the IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the component on the rising edge and data is clocked out of the component on the falling edge.

TMS TEST MODE SELECT: is sampled at the rising edge of TCK to select the operation of the test logic for IEEE 1149.1 Boundary Scan testing.

This signal has a weak internal pull-up to ensure proper operation when this signal is unconnected.

TRST# TEST RESET: asynchronously resets the Test Access Port (TAP) controller function of IEEE 1149.1 Boundary Scan Testing (JTAG).

This signal has a weak internal pull-up.

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3.1.4 VA0, VA1 (V

_CCPLL

) Pin Requirements

To reduce clock skew, the VA0 and VA1 balls for the Phase Lock Loop (PLL) circuit are each isolated on the package. The lowpass filter, as shown in Figure 2, reduces noise induced clock jitter and its effects on timing relationships in system designs. The 22 µF bulk capacitors must be low ESR solid tantalum and the 0.1 µF ceramic capacitor must be of the type X7R. The node connecting VA0 and VA1, must be as short as possible.

Table 9. Power Supply Pin Descriptions

V18A, V18B OUTPUT: This is the regulated 1.8 V supply generated internally.

Bypass with 0.1 and 10µF capacitors.

V18A and V18B are each outputs of internal voltage regulators. They need to be separately bypassed to ground with 0.1 and 10µF capacitors separately, they must not be connected together.

V_CC5REF Voltage Clamp I/O: In 5 V tolerant systems, this should be connected to a 5 V supply. In 3.3V powered systems this should be connected to 3.3 V. In PCI add-in cards, this would normally be connected to I/O Power (10 A, 16 A, 19 B, 59 A and 59 B). The user must ensure that the value of V_CC5REF is high enough to ensure compliance to the V_IH(MAX) specification on every input to the Intel^® 31244 PCI-X to serial ATA controller not just PCI inputs. For example, if the Serial ROM device is 5 V I/O this pin must be 5 V regardless of the PCI bus.

VA0, VA1 2.5 V Analog Power Supply: Separate filtering is recommended.

VA0 supplies the PCI PLL. VA1 supplies the CMU.

V_SS Ground.

V_CC 2.5 V Digital Logic Power Supply.

V_IO 3.3 V PCI I/O Power Supply.

V_CC0, V_CC1, V_CC2, V_CC3

2.5 V High Speed I/O Power Supply for each channel.

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3.1.5 Package/Marking Information

The package is marked with three lines of text as shown in Figure 4 (not to scale). See Table 10 and Figure 5 for package dimensions.

Figure 4. Package Information: 256-pin PBGA

A9626-02 Pin A1

Indicator A

B 1 32 5 4 76 9 8 1110 1312 1514 16

C D E F G H J K L M N P R T

1.81± 0.21

17mm

1.0 mm, Typ 17mm 3x 0.50 R

BOTTOM VIEW TOP VIEW

SIDE VIEW

Intel^® 31244 XX Pin A1 Identifier

#### AAAA

Part Number Package Suffix

Lot Tracking Code Date Code

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Table 10. Package Dimensions

Symbol Minimum Nominal Maximum Units

A 1.6 1.81 2.02 mm

A1 0.3 0.4 0.5 mm

A2 0.75 0.8 0.85 mm

D 16.8 17 17.2 mm

D1 14.95 15 15.7 mm

E 16.8 17 17.2 mm

E1 14.95 15 15.7 mm

e 1.0 (solder ball pitch) mm

C 0.55 0.61 0.67 mm

Figure 5. Dimension Symbols

D D1

E E1

TOP VIEW Pin A1 I.D.

45º Chamfer (4 places) Pin A1Corner

A 30º

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3.1.6 Intel

^®

31244 PCI-X to Serial ATA Controller Pinout

Figure 6. Intel^® 31244 PCI-X to Serial ATA Controller Pinout

B0419-02

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A A

B B

C C

D D

E E

F F

G G

H H

J J

K K

L L

M M

N N

P P

R R

T T

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PCI-X Interface Pins SERDES section

VIO 3.3V VSS

VCC is 2.5V JTAG Section VSS 32BIT

PCI# LED3 TX0N RX0P TX1N RX1P CAP0 CAP1 TX2N RX2P TX3N RX3P CLKIN CLKOUT VSS VCCREF VSS VSS TXOP RX0N TX1P RX1N VSS VA1 TX2P RX2N TX3P RX3N VSS VSS VCCREF

LED2 VCC P_AD32

VCC

SCS# VSS VCC0 VCC1 VSS VSS VSS VSS TDO

VSS P_RST# P_INTA# VSS LED0 MS_DA SSCEN VCC VSS TRST# TCK VSS P_AD33 P_

PAR64 VSS

P_REQ# P_AD31 P_GNT# CLKO VIO SDI LED1 TOUT TEST0 RBIAS TDI TMS P_AD36 P_AD35 VI0 P_AD34 VCC2

VSS VCC3

VSS

P_AD28 VIO P_AD29 P_AD30

P_AD25 VSS P_AD26 P_AD27

P_AD23 P_IDSEL P_CBE3 P_AD24 P_AD46 P_AD45 VIO P_AD44

P_AD39 P_AD38 VSS P_AD37

P_AD43 P_AD42 P_AD41 P_AD40 VSS VSS

VSS VSS VSS VSS

VIO VIO VIO

VSS VSS

VSS VSS VSS VSS VSS VSS

VSS VSS VSS VIO

VSS VIO

VIO

P_AD19 P_AD20 P_AD21 P_AD22

P_AD18 VSS VCC VCC

V18A VIO P_

IRDY# P_AD17

P_

TRDY#

P_

DEVSEL#P_AD16 P_

FRAME#

P_ VSS SERR#

P_

PERR#

P_CBE2 VCCREF

P_

STOP# VSS P_AD13

P_PAR VSS P_AD15 VIO

VSS P_CBE1 P_AD14 VSS VIO VIO

P_AD10

P_AD9 VIO

VIO

P_AD12

VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS

VSS VSS VSS VSS

VSS

VSS P_AD4

P_AD11 P_CBE0 VSS P_CLK VSS VSS P_

REQ64#P_CBE7

VIO P_AD6 VA0 VSS P_AD3 VIO P_CBE6

P_AD7 P_AD5 CAP3 CAP2 P_AD2 P_

ACK64#P_CBE5 VIO

VIO

P_AD0 VSS VSS

VIO

P_AD1 VIO

VCCREF VIO

VCCREF

VIO VIO VIO

P_AD8

P_AD54

VCCREF P_AD57

P_CBE4 VSS P_AD59

P_AD63 VSS

VSS VIO

VSS P_AD62 P_AD61 P_AD49 P_AD48 VSS P_AD47

VCC VCC P_AD51 P_AD50

P_AD53 P_AD52 VSS V18B

VSS VIO VCCREF

P_AD56 P_AD55

P_AD58

P_AD60

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Table 11. 256-Lead PBGA Package — Signal Name Order (Sheet 1 of 3)

Signal Ball # Signal Ball # Signal Ball #

32BITPCI# A2 P_AD24 H4 P_AD62 T14

CAP0 A8 P_AD25 G1 P_AD63 R14

CAP1 A9 P_AD26 G3 P_CBE0 P6

CAP2 T9 P_AD27 G4 P_CBE1 T2

CAP3 T8 P_AD28 F1 P_CBE2 N3

CLKIN A14 P_AD29 F3 P_CBE3 H3

CLKO E4 P_AD30 F4 P_CBE4 P13

CLKOUT A15 P_AD31 E2 P_CBE5 T12

DPA_MODE# D6 P_AD32 C16 P_CBE6 R12

LED0 D5 P_AD33 D14 P_CBE7 P12

LED1 E7 P_AD34 E16 P_CLK P8

LED2 / SCLK C1 P_AD35 E14 P_DEVSEL# M2

LED3 / SDO A3 P_AD36 E13 P_FRAME# M4

P_ACK64# T11 P_AD37 F16 P_GNT# E3

P_AD0 N12 P_AD38 F14 P_IDSEL H2

P_AD1 N11 P_AD39 F13 P_INTA# D3

P_AD2 T10 P_AD40 G16 P_IRDY# L3

P_AD3 R10 P_AD41 G15 P_PAR R1

P_AD4 N9 P_AD42 G14 P_PAR64 D15

P_AD5 T7 P_AD43 G13 P_PERR# P1

P_AD6 R7 P_AD44 H16 P_REQ# E1

P_AD7 T6 P_AD45 H14 P_REQ64# P11

P_AD8 N6 P_AD46 H13 P_RST# D2

P_AD9 T5 P_AD47 J16 P_SERR# N1

P_AD10 R5 P_AD48 J14 P_STOP# P2

P_AD11 P5 P_AD49 J13 P_TRDY# M1

P_AD12 N5 P_AD50 K16 RBIAS E10

P_AD13 P4 P_AD51 K15 SCS# C2

P_AD14 T3 P_AD52 L14 SDI E6

P_AD15 R3 P_AD53 L13 RX0N B5

P_AD16 M3 P_AD54 M13 RX0P A5

P_AD17 L4 P_AD55 N16 RX1N B7

P_AD18 K1 P_AD56 N15 RX1P A7

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TCK D12 V_IO E15 V_SS C7

TDI E11 V_IO F2 V_SS C8

TDO C15 V_IO F5 V_SS C10

TEST0 E9 V_IO F12 V_SS C12

TMS E12 V_IO G5 V_SS C14

TOUT E8 V_IO G12 V_SS D1

TRST# D11 V_IO H5 V_SS D4

TX0N A4 V_IO H12 V_SS D10

TX0P B4 V_IO H15 V_SS D13

TX1N A6 V_IO J5 V_SS D16

TX1P B6 V_IO J12 V_SS F6

TX2N A10 V_IO K5 V_SS F7

TX2P B10 V_IO K12 V_SS F8

TX3N A12 V_IO L2 V_SS F9

TX3P B12 V_IO L5 V_SS F10

V18A L1 V_IO L12 V_SS F11

V18B L16 V_IO M5 V_SS F15

VA0 R8 V_IO M6 V_SS G2

VA1 B9 V_IO M7 V_SS G6

V_CC C13 V_IO M8 V_SS G7

V_CC D8 V_IO M9 V_SS G8

V_CC D9 V_IO M10 V_SS G9

V_CC K3 V_IO M11 V_SS G10

V_CC K4 V_IO M12 V_SS G11

V_CC K13 V_IO M15 V_SS H6

V_CC K14 V_IO R4 V_SS H7

V_CC0 C4 V_IO R6 V_SS H8

V_CC3 C11 V_SS B2 V_SS H11

V_CCREF B1 V_SS B3 V_SS J6

V_CCREF B16 V_SS B8 V_SS J7

V_CCREF M16 V_SS B14 V_SS J8

V_CCREF N4 V_SS B15 V_SS J9

V_CCREF N7 V_SS A1 V_SS J10

V_CCREF N10 V_SS A16 V_SS J11

V_CCREF N13 V_SS C3 V_SS J15

V_IO E5 V_SS C5 V_SS K2

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V_SS K6 V_SS L10 V_SS P10

V_SS K7 V_SS L11 V_SS P14

V_SS K8 V_SS L15 V_SS R2

V_SS K9 V_SS M14 V_SS R9

V_SS K10 V_SS N2 V_SS R15

V_SS K11 V_SS N8 V_SS T1

V_SS L6 V_SS P3 V_SS T4

V_SS L9

Intel PCI-X to Serial ATA Controller

Datasheet

Product Features

Contents

Figures

Tables

Revision History

This Page Intentionally Left Blank

1.0 General Description

1.1 References

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2.0 Overview

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2.1 Applications

2.2 PCI-X Interface

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2.3 Serial ATA Interface

2.3.1 Direct Port Access (DPA)

2.3.2 Extended Voltage Range

2.3.3 Activity LEDs

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2.4 Serial ROM Interface

2.4.1 JTAG Interface

3.0 Package Information

3.1 Package Introduction

3.1.1 Signal Pin Descriptions

3.1.2 Serial ROM Interface Pin Descriptions

3.1.3 Reference Clock Generation

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3.1.4 VA0, VA1 (V

) Pin Requirements

3.1.5 Package/Marking Information

3.1.6 Intel

31244 PCI-X to Serial ATA Controller Pinout