AN APPROACH TOWARDS OPTIMISED LOW POWER
NANOSCALE REVERSIBLE DECODER USING
QUANTUM-DOT CELLULAR AUTOMATA
R. Jayalakshmi
1and R. Amutha
21
Sri Chandrasekharendra Saraswathi Viswa Maha Vidyalaya, Enathur, Kanchipuram, Tamil Nadu, India 2
Department of Electronics and Communication Engineering, Sri Sivasubramaniya Nadar College of Engineering, Kalavakkam, Chennai, Tamil Nadu, India
E-Mail: [email protected]
ABSTRACT
The Nano computing paradigm is in need of design and modelling of reversible digital circuits. Reversible digital circuits like adders, subtractors, shift registers, comparators, and decoders have been already proposed. In this paper an approach towards optimized reversible nanoscale decoder using QCA2 gate with Quantum Dot cellular Automata has been proposed. The proposed Reversible decoder uses QCA layout of QCA2 gate and has optimized cell count, area and latency.
Index Terms: QCA, QCA1 gate, QCA1 gate, decoder, QCA designer.
1. INTRODUCTION
The quantum–mechanical phenomena can be realized for the manipulation, storage and transmission of information. [1]. As per Moore’s law, as the feature sizes on integrated circuits reaches the scaling limits the quantum effects begin to take hold. In classical computing, bit is the unit of information. In quantum computing the unit of information is Qubit [1]. The quantum gates are reversible in nature since the interactions of subatomic particles are symmetrical in time. Energy dissipation in a Nano computing paradigm is ideally zero because reversible computation. The reversible computation of quantum computing has very low power dissipation less than kBTln2 joules. The bijective properties between inputs and outputs are used for the execution of a circuit in reversible computation [2].The reversible circuits are easy to observe and control since there is symmetry between the inputs and the outputs. [3].The currently existing complementary metal oxide semiconductor has high power dissipation and scaling issues. To overcome the issues in the existing systems, alternative paradigms are developed by researchers all around the world. One such alternative is quantum dot cellular automata, which can carry information and can also perform computation.
The quantum dot cellular automata device has very low power consumption and is extremely smaller in size. The QCA contains quantum cells with quantum dots which can carry electrons. The position of the electrons inside the quantum well determines the polarization of the cell which specifies the state of the cell as ‘0’ or ‘1’.The data transfer in the QCA cell is accomplished through the coulomb’s law of attraction and repulsion between the neighborhood cells. Numerous designs have been proposed using QCA for both combinational and sequential circuits [3-10]. In this Paper, an optimal design of reversible decoder using Quantum Dot Cellular Automata with Quantum gate QCA2 has been explored. The proposed decoder has been constructed using reversible QCA2 gate. The proposed design has been explored for the parameters like circuit complexity, cell
count, area and the clock cycles and compared with the existing layout. The simulation of the proposed design is performed with the bistable approximation engine on QCA Designer platform [16].
This organization of the paper is given as follows. The existing designs have been explained in Section II. In Section III, the proposed 1 to 2 and 2 to 4 reversible decoder is designed and implemented. In section IV, comparison of the proposed design with the existing layouts is evaluated. The conclusion and the future scope is described in Section V.
2. EXISTING REVERSIBLE DECODER
The output of the QCA computation depends on the majority voter. Various reversible quantum gates have been proposed. The reversible gates QCA1 and QCA2 are the recently proposed which can be used for majority voter QCA computing [17]. The QCA1 and QCA2 gates have three inputs A, B, C and three outputs P, Q, R with their logic functions and the truth table. The reversible quantum computing gates are utilized to construct reversible adders, subtractors, decoders, comparators and code convertors [3 - 10]. In processors, decoders are used along with the memory arrays for determining the storage location. Reversible decoders have been proposed with various reversible Quantum gates. Jadav et al., has utilized QCA1 Gate to implement reversible decoder with 1 to 2 decoder, 2 to 4 decoder and 3 to 8 decoder structures. The reversible QCA1 gate has bijective mapping between the Inputs and the outputs in the following logic,
Figure-1. Block diagram of QCA1 gate.
A B C P Q R
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
1 1 1 1 1 1
Figure-2. Truth table of QCA1 gate.
Figure-3. QCA schematic of QCA1 gate.
considered as general input W0 [15] as in the block diagram in Figure-6.
Figure-5. QCA1 gate as 1 to 2 decoder.
The output of the reversible decoder using QCA1 gate is given by,
Y1 = EnW0 and Y0 = EnW0´. The output R is termed as the garbage output.
3. PROPOSED DECODER USING QCA2 GATE
The Algorithm of the Proposed Design is,
a) The Lay out with Majority gate for the Logic
Function of the QCA2 has been obtained.
b) The QCA layout of QCA2 gate has been proposed.
c) Design of 1 to 2 Decoder and 2 to 4 Decoder has been
implemented.
d) The Proposed is evaluated for Cell count, Area and
Latency with the existing design.
The QCA2 gate is a reversible quantum gate, where the input vectors are A, B, C and the output vector s are P, Q, R where the vector mapping is given by the following expressions., P = AB + BC + CA , Q = AB + BC + C´A , R = A´B + BC´ + C´A´ . The Vector mapping of QCA1 gate and QCA2 gate are same except for the Output function R.
Figure-6. QCA2 gate.
A B C P Q R
0 0 0 0 0 1
0 0 1 0 0 0
The QCA2 gate can be represented using Majority Voters in Quantum Dot cellular Automata [17]. As proposed by Jadav Das et al., the layout of the QCA2 gate with modifications in the placement of QCA cells is given in Figure-9.
Figure-8. QCA schematic of QCA2 gate.
Figure-9. QCA layout of QCA2 gate.
b) Reversible decoder 1-to-2 decoder
The QCA2 gate can be utilized to implement the function of a 1-to-2 decoder, by fixing the input A of QCA1 gate to logic ‘0’ as in Figure-1. The input B is considered as enable Input En and the input C is considered as general input W0 of the reversible 1-to-2 decoder as shown in the block diagram in Figure-10.
Figure-10. a) Block diagram b) Layout of QCA2 gate as 1 to 2 decoder.
As the Input A = 0, the output Y1 = EnW0 and the output Y0 = EnW0´. The third output which is mapped to R is termed as Garbage output. The Layout has slight
Figure-11. a) Simulation output b) Truth table of QCA2 gate as 1 to 2 decoder.
The QCA layout of reversible 1-to- 2 decoder using QCA2 gate has reduced complexity than 1-to- 2 decoder using QCA1 gate[ ]. The result of the simulation as shown in the Figure is verified with the theoretical values.
4. RESULTS AND DISCUSSIONS
The reversible 1 to 2 decoder using QCA2 has an optimized cell count, area and latency. The simulation used is QCA designer version 2.0.3 [14] [16]. The engine
used for the simulation is bi-stable approximation engine with the following parameters, number of samples 12800, convergence tolerance 0.001000, radius of effect 65.000000 nm, relative permittivity 12.900000, clock high 9.800000e-022, clock low 3.800000e-023, clock amplitude factor 2.000000, layer separation 11.500000, maximum iterations per sample 100, cell height 18nm, cell width 18 nm and dot diameter 5 nm. the cell count and area is reduced which further reduces the circuit complexity as in Figure-12.
Figure-12. Existing and proposed system complexity.
The number of clock used is considerable less than the proposed design [15] and hence the latency has been improvised.
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