Defects Reduction of Nano-Semiconductor Dual Damascene Process Development

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Defects Reduction of Nano-Semiconductor

Dual Damascene Process Development

Chun-Jen Weng

[email protected], [email protected]

Department of Technology Management

Leader University

Tainan, 709

Taiwan, R.O.C.

ABSTRACT

To be successful in the competitive nano-semiconductor industry, the need to reduce cost per die is necessary and always challenging. Such defect data consist of systematic and random defects that may be yield limiting or may be just cosmetic issue with low probability of yield impact. Nano semiconductor process manufacturing defects can often impact product yields, depending upon the type, size, and location of the defect, as well as the

design and yield sensitivity of the respective semiconductor product devices. This paper presents

comprehensive the investigating a process defects monitor and integration on semiconductor copper manufacturing process and technology, and module process integration of the problem of defects reduction on semiconductor etching manufacturing processes. This paper presents our study on the cause of sphere defects in dual damascene trench isolation etching process. As device geometries are reduced, understanding and minimizing the sources of process-induced defects is critical to achieving and maintaining high device yields. In this paper, systemic identification and classification approach has been introduced to improve process yield by defect sampling for SEM review. Experiments were performed to identify the defect source and determine the mechanism of defect formation. The solutions implement to eliminate this issue are presented

Keywords:Defects, Wafer, BEOL, Process Integration, Copper Dual Damascene

1. Introduction

Semiconductor process defect data consist of systematic and random defects that may be yield limiting or may be just cosmetic issue with low probability of yield impact. However, the overall yield impact from manufacturing process defects has been difficult to assess since the defect sensitivity, capture rates, and classification for these defects has often been poor on product wafers. As device geometries are reduced, understanding and minimizing the sources of process-induced defects is critical to achieving and maintaining high device yields. Low-k dielectrics and Cu patterns have been extensively investigated as materials that can reduce the parasitic capacitance of ULSI interconnect. Defects and the corresponding product yield impact were observed to vary significantly between silicon wafer manufacture processes. Abnormal phenomena lead to yield loss during electrical device test and productivity yield losses. Dual damascene processes demand cleanliness since defects at trough etch result in opens of electrical device, but could also cause problems in later via etch process steps.

The efficient yield of integrated circuits (IC's) wafer fabrication, successful development and implementation of new processes technologies requires optimization of all parameters. In semiconductor fabrication industry, the tight geometries found in small feature sizes, higher pattern density and high aspect ratio contribute to the faster chips the market demands, but also require improved performance with respect to

defect density. The patterns missing phenomena were always occurred on sub-micron semiconductor

processes. The higher pattern density and high aspect ratio always result in pattern abnormal and collapse, because of the not optimal parameter for process feasibility. In the semiconductor submicron process area, it is difficult to maintain the high effects on yield and device performance owing to process control, the complicated structure of physical geometry and stress induced on the semiconductor wafer. The abnormal phenomena will

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leads to yield loss on electrical device test and productivity yield losses. Therefore, for deep submicron semiconductor module process, optimal technology process step integration is desired for achieving a high performance device.

Jean et al. [1] investigated the process development characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the 65 nm complementary metal oxide semiconductor (CMOS) technology. It has been common knowledge that pattern collapse of this back-end-of-line (BEOL) duel damascene process could be prevented by optimal the process. To control pattern collapse, Koba et al. [2] indicated and demonstrated that tri-layer resist process had a high applicability for device fabrication in BEOL. Su et al. [3] proposed a hybrid BEOL dual damascene interconnect approach with organic ultra-low-k for gap filling. The traditional photoresist approach with via-first process for dual damascene suffers from ashing damage for chemical vapor deposition (CVD) ultra-low-k. The approach is able to circumvent the issues mentioned above without introducing process complication.

It is important to use inspect and classify wafers for defect inspection check for advanced semiconductor

wafer manufacturing processes. Moreover, BEOL defects have increasing occurrence probability than

front-end-of-line (FEOL) defects in nanometer technologies. Epitaxial defects (e.g., stacking faults, epi-spikes, mounds, hillocks, and pits) can often impact product yields, depending upon the type, size, and location of the defect, as well as the design and yield sensitivity of the respective semiconductor product devices. Williams et

al. [4] evaluated the yield impact of epitaxial defects on advanced semiconductor technologies. Advanced

bright field inspection tools available today applied on development wafer may often result in 100k to 1M defects per wafer. Such defect data consist of systematic and random defects that may be yield limiting or may be just cosmetic issue with low probability of yield impact. Moreover, Yeh and Park [5] propose novel technique described here provided a way of detecting and identifying such systematic defect, enabling wafer manufactures to quickly resolve the defects inspection issue.

Dual damascene processes demand cleanliness since defects at trough etch result in opens, but could also cause problems with later via etch process steps. Therefore, for deep sub-micron era, high pattern density technology is desired for achieving a high performance device. Consequently, for semiconductor sub-micron process integration and development, it is difficult to maintain high effects on yield and device performance due to process control especially on BEOL process operation, because of the complicate physical pattern structure and defects induced on semiconductor wafer processes. Biolsi et al. discussed a defect reduction program of a manufacturing line through inline metrology and yield controls. It included the determination of source of defects, correcting marginal hardware and verifying the defect improvement. The new pattern wafer detection was needed to find the particles responsible for yield loss on production wafers. A statistical approach was used to reduce the variability of the line control.

A defect reduction program of a manufacturing line through inline metrology and yield controls. It included the determination of source of defects, correcting marginal hardware and verifying the defect improvement. Nagaishi et al. [7] investigated defect reduction measures performed during the development of a 130-nm Cu dual-damascene process. A copper hillock induced interconnect failure mechanism is presented. The copper hillock is frequently generated during a copper dual damascene process and hillock formation is found to degrade the interconnect integrity by affecting the following process steps. Kim et al. [8] observed a copper hillock induced defect model is proposed and a new copper process is suggested to reduce copper hillocks. Hichri, [9] outlined yield improvements in the integration of damascene copper in low-k SiCOH irtermetal dielectric at 65 nm dimensions. Large defect reductions were seen by Reactive Ion Etching (RIE), wet cleans and CMP process optimization. RIE improvements led to reductions of thirty three percent for missing pattern defects while wet clean optimization resulted in more man a fifty percent reduction in metal voids CMP carrier head changes provided a more corrosion resistant process and higher throughput. Copper (Cu) line shorts defects have a high potential of becoming yield killers for device manufacturing. As design rules shrink the importance of a process free of metal shorts becomes essential to increase FAB yield performance. One of the main challenges of analyzing short defects caused by various physical mechanisms is that when reviewed by top view SEM image after the each process step. Porat et al. [10] resolved the root cause mechanisms of the chemical mechanical polish (CMP) process defects by using in line focused ion beam (FIB) cross.

2. Results and Discussion

2.1 BEOL Dual Damascene Processes Technology

Defect inspection metrology is an integral part of the yield ramp and process monitoring phases of semiconductor manufacturing. High aspect ratio structures have been identified as critical structures where

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there are no known manufacture solutions for defect detection. A serious problem in wafer fabrication is the defects issue during the pattern development process, because it decreases the yield of wafer production. Abnormal patterning phenomena lead to yield loss during the electrical device test and productivity yield losses. The present study relates to the field of semiconductor fabrication and, more particularly, to optimal method for

processes integration approach for forming BEOL damascene patterning processes. Dual damascene

processes demand cleanliness since defects generated during trough etching result in abnormal data of the electrical device, and can also cause problems in later process steps of next interconnect layer. Therefore, in the deep submicron era, high-pattern-density technology is desired for achieving a high-performance device. The use of etching and lithography technologies to improve the submicron process has been known for years and many semiconductor process technologies have been proposed.

However, it has been known that abnormal pattern and numerous defects could be prevented by numerously process module tuning. Copper is used widely for metal interconnection in ULSI due to its lower resistivity and superior resistance against electro-migration. As copper duel damascene process is complicated and critical in semiconductor wafer processes manufacturing. The process development characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the sub-micro CMOS technology defects reduction was presented. Traditional excursion monitoring relies on defect count or density. However, process or tool induced problems may arise during wafer fabrication that cause scratches and other spatial signatures on the wafer that will not be caught by statistical process control (SPC) methods if the raw wafer defect count or density is low.

A dual damascene process can be used to form an interconnection on semiconductor. As via first scheme is employed for dual damascene patterning, trench patterning process has been posed many challenges to the patterning process. Film deposing and interconnect cross-section structure of BEOL copper dual-damascene scheme was shown in Fig.1 and Table1. For the electrical device special needs leads to film stack increasing, then results process challenges on lithography and etching processes. As metal interconnect line aspect ratio, pattern density, and metal interconnect layers increased, these schemes could be more complicate and challengeable than traditional process on etching and lithography module fabrication processes. One of the significant difficulty in multi-level interconnects that may be implemented by process tuning and optimal manufacturing processes integration.

Fig.1 Semiconductor standard copper process metal physical Table 1 Physical dimension and metal inter-connect scheme

2.2 Defects Inspection

As design rules continue to shrink, the demand increases for effective inspection tools to detect defects that affect device yields. Performance is essential to enable the manufacturing of advanced devices, and to ensure acceptable line yields from a defect perspective and fabrication yields from a device perspective. Interconnect line shorts defects have a high potential of becoming yield killers for device manufacturing. To be successful in the competitive semiconductor industry, the need to reduce cost per die is necessary and always challenging. It is important to produce better yield of die per wafer by minimizing the cycle time to detect and fix yield problems associated with the advanced process module technology. Defect inspect metrology refers to the techniques and procedures for determining physical and electrical properties of the wafer during the fabrication. One of the main challenges of analyzing short defects caused by various physical mechanisms is that when reviewed by top view SEM image after etching patterning process step. The way for us to resolve the root cause mechanisms of the above mentioned defect types is by using in line SEM review and FIB cross sectioning analysis. Productivity yield, or wafer electrical sort yield can be separated into three components on process:

random defect limited yield, systematic yield, and repeating yield loss. Systematic yield losses are

process-related problems that can affect all die on a wafer, some die on a wafer, or die by region on a wafer. Top wide Metal / Via connection Inter connection Metal / Via BEOL FEOL Dielectric film

Shallow Trench Isolation

N-Well P-Well N -N -P -P -N+ _N+ P+ P+ Si

Metal interconnect trace

Top wide Metal / Via connection Inter connection Metal / Via BEOL FEOL Dielectric film

Shallow Trench Isolation

N-Well P-Well N -N -P -P -N+ _N+ P+ P+ Si

Metal interconnect trace

Before etching Line Width =140 nm Wide Line Width =280 nm Film deposition Depth ~5000 A ~8500 A Inter-Connect Aspect Ratio ~3.57 ~3.04

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The defects images show various types of topographic defects such as hills, islands, holes and valleys. These types of topographical defects could prevent proper adhesion of some films, and lead to delamination of interconnects.

Before selecting the appropriate method for removing the wafer defects, defects images classifications were examined from several production process wafers to better understand the cause and extent of the defects. The abnormal pattering is easily found in etching process. The BEOL in-line process defect monitor maps and classification of AEI (After Etching Inspection) were shown in Fig.2. Defect reduction and process change experiments are typically evaluated based on defect density, which is susceptible to previous layer or process module induced defects. Such defect data combine systematic and random defects that may be yield limiting or just nuisance defects. It is difficult to identify systematic defects from defect wafer map by l defect classification where random sample defects are reviewed on review scanning electron microscope (SEM). Missing important systematic defect types by traditional sampling technique can be very costly in device introduction. To systemic classification defects, 100 defects were reviewed and categorization. In-line defect monitoring in manufacturing, the majority of defects inspection is to class process excursions and identify the sources of yield-limiting (killer) defects. The result was compared against design layout to confirm that the defects were occurring at certain locations of design layout. Afterwards the defect types were reviewed using SEM and in-line focused ion beam (FIB) for further confirmation. Based on the inspection technique, we were able to filter out a systematic defect type quickly and efficiently from wafer map that consist of random and systematic defects.

Fig.2 In-line wafer maps of process defect inspection

As circuit design becomes more complex, more circuit failures will be caused by defects. Etching bi-products, processing chamber defects are the killer impact defects, and abnormal patterning process defects, which were shown in Fig. 3 to Fig.6. There yield killer defects may be resulted from abnormal pattern developments, material, and process limitations. In wafer processing, a series of tradeoffs always exists —

balancing chemical cost, process throughput, and removal efficiency. Particle performances were conducted

to determine the effectiveness of integrated processes. While the inspection revealed that the defects were particles of processing equipment chambers and etching polymer residuals, approximately 10—20%. Figure 3

shows the inspection of particles of processing chamber and process bi-products. Product yield is greatly

improved after the reduction of defectivity. Figure 4 demonstrates BEOL etch-polymer characteristics also

have varying properties due to feature density, exposed films, and etch chemistries. Semiconductor studied problems resulting from insufficient solvent cleaning of metal lines and via holes that can lead to killer particle defects. The work also focused on residual etch-polymer issues, which cause yield loss and reliability problems. It was discovered how inappropriate BEOL cleans and process defects originating from cleaning tools themselves were limiting yield. After etching, the photoresist and some etch polymer is removed using an oxygen plasma process. Some polymer remains after ash, due to polymer increase on the sidewall. Compounding the problem is an even higher amount of polymer seen on metal lines in areas where a large amount of metal was removed. BEOL cleans also must maintain very low defectivity levels to prevent yield loss.

Fig.3 In-line processing chamber cleanness results in defects increasing Fig.4 Polymer residue defects by patterning etching process

Fig.5 Photolithography process abnormal patterning defects. Fig.6 Etching patterning process defects due to abnormal patterning Wafer 1 Wafer 2 Wafer 3

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Most of the systematic pattern related defects are detected during the process development. These defects are detectable with abnormal patterning structures or process. As geometries continue to shrink, the ramp up time to reach stabilised yield is increasing while the yield at maturity is declining. This is primarily due to systematic pattern related defects and needs to be addressed more effectively. Optimal methodologies are required to improve manufacturability by reducing the number of systematic defects. To develop these abnormal patterning issue results process issues include pattern missing, peeling, dielectric breakdown, and serious defects line process development control strategies. The abnormal pattern related defects were shown in Fig.5 and Fig.6 for lithography and etching process, respectively. Systematic defects preferentially occur in certain design layouts due to either printability issues or process-layout interactions. Eliminating these systematic mechanisms early in a semiconductorfabricator’s technology ramp is essentialtoachieving an efficient yield targets. The mechanism of pattern related defect is related to dual damascene litho process that could not correctly define the interconnect line, thus creating shorts between metal lines.

2.3 Processes Improvement

As technology scales down from one node to the other, interconnects become the limiting factor affecting circuit performance. The BEOL stack has to be finely tuned through material and process optimizations to meet speed requirements. As the progress of the semiconductor process develops to achieve miniaturization and attain better performances for the electronic device, next-generation IC chips with deep sub-micron Cu/low-k stacked structures adopting the fabrication of dual damascene are developed to meet the urgent requirements of reducing high RC delay; the purpose of this is to obtain high-speed signal communication. Moreover, owing to the reduction of pitch and thickness materials, the process variability control will become a major issue to resolve. The major reliability challenges that must be overcome to achieve the scaling targets for future integrated circuits (ICs) are at the BEOL process. A novel method for BEOL manufacturing processes is provided for enabling fabricating using a metal interconnects fabrication process.

As via first scheme is employed for dual damascene patterning, trench lithography and etching processes have been posed many challenges to the patterning process. One of the significant difficulty in multi-level

interconnects that may be implemented by process tuning and optimal integration. As semiconductor

fabrication process is complicated, standard copper dual damascene manufacturing method of a BEOL metal trench was presented in Fig 7. A dual damascene process can be used to form an interconnection on semiconductor. These demonstrations are important because of the density and interconnect sizes achieved by the potential extension to wafer-scale stacking. A first dielectric layer is formed on a semiconductor substrate having a device layer formed thereon. Vias were formed and patterned on the dielectric layer so that an opening is formed to expose the gate device therein. The metal trench penetrating through the dielectric layer is formed, and the device layer within the contact window is exposed. It is challenge on via and metal lithography and trench process especially for physical and electrical device in dual damascene process.

The abnormal pattern issue results process issues include pattern missing, peeling, dielectric breakdown, and serious defects on process development control strategies. Fig.8 shows the in-line process abnormal pattern phenomena, and the abnormal pattern collapse phenomena which will results in the electrical bridge and open during wafer electrical accept test and yield loss in mass production. Therefore, the etching selectivity in pattern developing becomes a critical concern from lithography pattern developing process. The abnormal process development phenomena indicate that photo-resistant abnormal phenomena may result pattern collapse, photo-resistant shortage on pattern developing process. To be successful in the competitive semiconductor industry, the need to reduce cost per chip is necessary and always challenging. It is important to produce better die chip per wafer by minimizing the cycle time to detect and fix yield problems associated with the advanced process module technology. Systematic yield losses are process-related problems that can affect all die chips on a wafer. The abnormal process induced defects increasing in process as show in Fig.8. To systemic classification defects and yield improving, the majority of defects classification is to class process excursions and identify the sources of yield-limiting (killer) defects.

Fig.7 Standard semiconductor via first BEOL dual damascene process

PR

PR PR

PR

(a) Film (b) Via developing (c) Via etching (d) Cleaning (d) Trench developing

PR

PR PR

PR

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Gap-filling process is a technique that has many applications in semiconductor production. In semiconductor wafer manufacturing, the gap-filling process is often used after openings are formed. The gap-filling material treatment may include etching the dielectric layer and the gap-filling material layer to

planarize the gap-filling material layer. In addition, the gap-filling material treatment may also include

performing a plasma processing, an ultraviolet curing or a chemical immersion of the gap-filling material layer to form a protective layer over the gap-filling material layer. However, the width and pitch of metal interconnect trace scare down as electrical device needed, and the aspect ration of trace line was also increased. This phenomenon will result in difficulties in manufacturing process. From Fig.9, gap-filling photo-resistant is not enough to coating via gap because of high aspect ratio and properties of gap fill material especially in dense patterns. The abnormal developed patterns will continuous found on trench developing process. Fig.10 demonstrates the abnormal phenomena especially in dense patterns.

Fig.8 Comparison of photo-resistant abnormal and pattern missing on dense pattern Fig.9 Comparison of gap-fill between

As damascene structure, a photo-resist pattern missing, etching selectivity and chemical mechanical polish are especially challengeable during damascene structure of wafer fabrication. As BEOL film stack depends on the electrical device required and manufacturing process module process needed, the dielectric film buffer is extreme high for etching selectivity and CMP buffer loss as Fig.11 shown. The photo-resistant height is also increased in proportion to the film stack deposition. Consequently, lithography and etching process of BEOL dual damascene become complicate and difficult.

Fig.10 Photo-resistant abnormal between isolation/dense patterns Fig.11 Fabrication process buffer and physical structure for BEOL layer Novel approach to solve the problem of pattern collapse was shown in as Fig.12. The present study is to provide a lithography gap-filling and BARC (Bottom Anti Reflect Coating) process capable of producing improved surface planarity so that a subsequently formed photo-resist layer over the gap-filling material layer also has a better flat surface for sub-micron device manufacturing processes. A gap-filling material treatment of the surface of the gap-filling material layer and the BARC plasma etching treatment are carried out to planarize the gap-filling material layer so that a subsequently formed bottom material coating layer over the interconnect traces can have a high degree of planarity. The photo resistant material treatment may include lightly plasma etching back the dielectric layer and gap material layer to planarize the gap surface. The aspect ration is increasing as electrical device needed. Significant modifications and improvements have been implemented to overcome those challenges as design rules shrink, via/trench processes optimization. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling photo-resistant material and BARC material properties as Table 2 shown, etching back plasma treatment of the surface of the gap-filling material, BARC layer and the dielectric layer is carried out to planarize coating surface.

As etching selectivity, loading effects, and aspect ratio, the photo-resistant easily to collapse and abnormal phenomena after lithography developed process, this study describes a new process integration step to be added in the interconnect fabrication process. The verifications of process were also demonstrated by step by check. For sub-micro via first BEOL integration process, the depth of via is high and etching process results were shown as Fig.13. For via etching process, there is no abnormal physical geometry on interconnect line even dense pattern. However, the trench patter developing is more difficult than via developing. The gap-filling material layer is etched to form a planar surface. Hence, any layer deposited over the gap-filling material layer can have a high level of planarity that facilitates the formation of a correct pattern in subsequent photolithographic and etching operation. Following Fig.12 proposed modified manufacturing process flow, there will be a more flat plane gap-filling material layer and BARC for photolithographic and etching processes even on dense patterns. In Fig.14, the physical cross-section of isolation trench pattern (line/space=0.14/0.42um)

456nm 538nm

(a) Isolation pattern (a) Dense pattern

850nm 538nm 456nm 850nm

(a) Isolation pattern (a) Dense pattern

850nm 850nm

CMP process loss buffer ~1000 A Etching process loss buffer ~ 1000 A

SiNx SiOx

Unit:A SiNx

SiOx

Photo resistant Etching selectivity on pattern ~ Film depth

CMP process loss buffer ~1000 A Etching process loss buffer ~ 1000 A

SiNx SiOx

Unit:A SiNx

SiOx

Photo resistant Etching selectivity on pattern ~ Film depth

Isolation pattern Dense pattern

Line- 0.14 / Space-0.14um Line- 0.14 / Space-0.42um

(a) Defects map (b) SEM (C) cross-section

Isolation pattern Dense pattern

Line- 0.14 / Space-0.14um Line- 0.14 / Space-0.42um

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and dense trench pattern (line/space=0.14/0.14um) were perfect after lithography developing process. There is not any pattern collapses or pattern missing on dense and isolated pattern around wafer center and edge on process even high aspect ratio metal interconnect by present novel integrated treatment process. In this present integrated process, any layer deposited over the gap-filling material layer and BARC can have a high level of planarity that facilitates the formation of a correct pattern in subsequent lithographic and etching process.

Fig.12 Proposed optimal new dual damascene interconnect Table 2 A gap-filling photo-resistant and BARC material properties

Fig.13 In-line pattern cross-section inspection after via etching process. Fig.14 Comparison of photo-resistant developing

Moreover, to verify not any pattern collapses and missing the trench pattern after etching process developed for tight dense interconnect pattern on critical dense trench pattern (line/space=0.14/0.14um). Fig.15 indicates the pattern the high-density pattern for AEI (After Etching Inspection) on process in-line check points. There is no pattern collapse, missing phenomena found. After via etching process, via interconnects profile are good, and the etching selectivity issue by photo-resistant was not found. As electrical device needs, the semiconductor BEOL process is challengeable and marginal in module process integration. Furthermore, the physical cross-section of interconnects trench pattern were also shown in Fig.16. From cross-section check, the top and bottom trench patterns were not found rounding and abnormal physical geometry. From Fig.13 to Fig 16, there is no pattern missing and abnormal physical geometry found on BEOL trace pattern by step-by-step in-line check and verification by the present novel and optimal manufacturing process.

For the electrical test verification, the electrical resistance and bridge were also included in present study. The comparison of bridge current was shown in Fig.17, the present novel integrated processes technique found tight than existing manufacturing process. This test pattern is always to check the semiconductor process

in-line electrical and physical checking. The drain voltage (VD=1V), source voltage (VS) and substrate voltage

(VSUB) =0V, Measure electrical current (Id), Electrical resistance Rc = VD/ Id. in Fig.18, electrical resistance

indicates electrical device test performance of copper metal trace line for electrical device requirements. These data distribute tight and no open electrical test data found. To prevent the metal short of the isolated pattern next to or surrounding by the wide metal, the minimum space with wide neighboring metal was defined. Using these proposed optimal and novel integrated processes, the physical geometry and electrical performance could be better performance than original existed process.

Fig.15 In-line verification after etching inspection (AEI) process Fig16 In-line pattern cross-section inspection after trench etching process

Dense pattern

140 nm

(a) Dense pattern profile

Isolation pattern

420 nm 140 nm

(b) Isolation pattern profile

Dense pattern

140 nm

Dense pattern

140 nm

(a) Dense pattern profile

Isolation pattern

420 nm 140 nm

Isolation pattern 420 nm 140 nm Isolation pattern 420 nm 140 nm Isolation pattern 420 nm 140 nm

140 nm 140 nm 140 nm 140 nm 140 nm 140 nm 140 nm 140 nm 140 nm 140 nm Dense Isolation wide pattern

~ 800 nm

~ 800 nm 280 nm

Dense Isolation wide pattern

~ 800 nm

~ 800 nm 280 nm

(b) Via developing (c) Via etching (d )Cleaning

(a) Film (e) GFP_1 Coating

Photo-resistan t Photo-resistant

(f) GFP_2 Coating Proposed optimal techniques

(b) Via developing (c) Via etching (d )Cleaning

(a) Film (e) GFP_1 Coating

Photo-resistan t Photo-resistant

(f) GFP_2 Coating Proposed optimal techniques

(k) Trench etching (h) BARC (j) Trench_developing

B ARC1

BARC2

(g) GPF_2 Etching back

Ph oto -resistant

(i) BARC (k) Trench etching (l) cleaning Copperprocess (h) BARC (j) Trench_developing

B ARC1

BARC2

(g) GPF_2 Etching back

Ph oto -resistant

(i) BARC (l) cleaning Copperprocess

Solids 14 ± 1% Optimal Thickness - 37.0nm Viscosity @ 25

Deg C 5.4 ± 0.5 cstks n @ 193nm 1.51

Refractive index 1.55 k @ 193nm 0.57

Film thickness 3,900 ± 200 Å @ 4,000_rpm n@633nm 1.52 Appearance Clear, Yellow Flash Point >100°F (>38°C) Initial transmission

(365 nm) < 6.5 Ions: Al, K, Cu, Mg, Mn <25 ppb Final transmission

(365 nm) > 83.5 Ions: Fe, Ca, Na <50 ppb

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Fig.17 Electrical bridge current comparison Fig.18 Electrical Resistant device comparison

3. Conclusions

This is primarily due to systematic pattern related defects and needs to be addressed more effectively by optimal methodologies. The present novel and optimal BEOL technique is to provide a gap-filling and BARC etching back treatment process capable of producing a improved surface planarity so that a subsequently formed a bottom photo-resist layer coating over the gap-filling and BARC material layer also has a better surface planarity. This paper presents a new and optimal process integration step to be added in the BEOL interconnect fabrication process. This study presents a gap-filling treatment and BARC optimal process for BEOL dual damascene process. To improve systematic defects and provide better planarity for regions; and to provide good adhesion for the photo-resist layer thus reducing pattern collapse were included in present investigation. Acknowledgment

The author gratefully acknowledges the support and assistance of NSC 96- 2221-E - 426–007. References

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defect root cause analysis of Cu CMP shorts using dual beam FIB,”ASMC Adv. Manuf. Conf. Proc., p 53-55, 2008. KS846.01_RSM2_p14_p13 0.000 0.020 0.040 0.060 0.080 7 8 9 ₁0 wafer_ID Wafer ID Wafer ID R s (o hm ) #1 #2 #3 #4

Present technique _{Existing original process}

KS846.01_RSM2_p14_p13 0.000 0.020 0.040 0.060 0.080 7 8 9 ₁0 wafer_ID Wafer ID Wafer ID R s (o hm ) #1 #2 #3 #4

Present technique _{Existing original process}

KS846.01_IBRM2_p14_p13 1.0E-14 1.0E-12 1.0E-10 1.0E-08 1.0E-06 7 8 9 1 0 Wafer ID

Existing original process

Present technique B ri dg e C ur re nt (A ) #1 #2 #3 #4 KS846.01_IBRM2_p14_p13 1.0E-14 1.0E-12 1.0E-10 1.0E-08 1.0E-06 7 8 9 1 0 Wafer ID

Existing original process

Present technique B ri dg e C ur re nt (A ) #1 #2 #3 #4