National Aeronautics and Space Administration
BOK─Pr
inted
E
lectron
ics
Reza
Ghaffar
ian
,
Ph
.D
.
Je
t
Propu
ls
ion
Labora
tory
Pasadena
,
Ca
l
iforn
ia
Je
t
Propu
ls
ion
Labora
tory
Ca
l
iforn
ia
Ins
t
i
tu
te
of
Techno
logy
Pasadena
,
Ca
l
iforn
ia
JPL
Pub
l
ica
t
ion
13-17
12
/13
National Aeronautics and Space Administration
BOK─Pr
inted
E
lectron
ics
NASA
E
lec
tron
ic
Par
ts
and
Packag
ing
(NEPP)
Program
Off
ice
of
Safe
ty
and
M
iss
ion
Assurance
Reza
Ghaffar
ian
,
Ph
.D
.
Je
t
Propu
lsion
Labora
tory
Pasadena
,
Ca
l
iforn
ia
NASA
WBS
:
724297
.40
.43
JPL
Pro
jec
t
Number
:
104593
Task
Number
:
40
.49
.02
.18
Je
t
Propu
ls
ion
Labora
tory
4800
Oak
Grove
Dr
ive
Pasadena
,
CA
91109
h
t
tp
:
/
/nepp
.nasa
.gov
This research was carried out atthe Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program.
Reference hereinto any specific commercial product, process, or service bytrade name,trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government orthe Jet Propulsion Laboratory, California Institute of Technology.
Copyright 2014. California Institute of Technology. Government sponsorship acknowledged.
Acknowledgments
The author wouldliketo acknowledge many people fromindustry andthe Jet Propulsion Laboratory (JPL) who were criticaltothe progress ofthis activity. Specialthanksto Dr. Witold Sokolowski for hisinputs on additive manufacturing. The author extends his appreciation to program managers of the National Aeronautics and Space Administration Electronics Parts and Packaging (NEPP) Program, including Michael Sampson, Ken LaBel, Dr. Charles Barnes, and Dr. Douglas Sheldon, for their continuous support and encouragement.
Object
ives
and
Products
The use of printed electronics technologies (PETs), 2D or 3D printing approaches either by conventional electronicfabrication or by rapid graphic printing of organic or nonorganic electronic devices on varioussmall or large rigid orflexible substrates, is projected to grow exponentially in commercialindustry. This has provided an opportunityto determine whether or not PETs could be applicable for low volumeand high-reliability applications.
Thisreport presents asummary ofliteraturesurveyed and provides a body of knowledge(BOK) gathered on the currentstatus of organic and printed electronicstechnologies. Itreviews three key industry roadmaps- on this subject—OE-A, ITRS, and iNEMI—each with a different name identification forthisemergingtechnology. Thisfollowed by a briefreview of the status of the industry onstandard developmentforthistechnology, includingIEEEandIPCspecifications. The report concludes with key technologiesand applications and provides a technology hierarchy similar tothose of conventional microelectronics forelectronics packaging. Understanding keytechnology roadmaps, parameters, and applications is important when judiciallyselecting and narrowingthe follow-up of new and emerging applicabletechnologiesfor evaluation, as well asthe lowrisk insertion of organic,large area, and printed electronics.
Tab
le
of
Contents
1.
Pr
inted
E
lectron
ics
Techno
logy
Trends
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
2
.
PET
Roadmaps
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4
2
.1
PET
Roadmap
Organ
iza
t
ions
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4
2
.2
OE-A
Roadmap
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4
2
.3
Pr
in
ted
RFID
Roadmap
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
5
2
.4
ITRS
PET
Roadmap
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
7
2
.5
iNEMI
PET
Roadmap
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
9
3
.
Spec
if
icat
ions
for
PET
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
12
3
.1
Key
Spec
if
ica
t
ions
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
12
3
.2
IEEE
Spec
if
ica
t
ions
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
12
3
.3
IPC
Spec
if
ica
t
ions
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
13
4
.
Techno
log
ies
and
H
ierarchy
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
15
4
.1
Surface
Moun
t
Techno
logy
H
ierarchy
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
15
4
.2
Pr
in
ted
E
lec
tron
ics
Techno
logy
H
ierarchy
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
17
4
.3
Pr
in
ted
E
lec
tron
ics
Techno
logy
Performance
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
18
5
.
Add
it
ive
Manufactur
ing
/3D
Pr
int
ing
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
20
5
.1
In
troduc
t
ion
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
20
5
.2
Key
AM
for
Me
ta
l
l
ic
Ma
ter
ia
ls
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
20
5
.3
AM
Ma
ter
ia
ls
and
Cha
l
lenges
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
21
6
.
Summary
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
22
7
.
Acronyms
and
Abbrev
iat
ions
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
23
1
. Pr
inted
E
lectron
ics
Techno
logy
Trends
Printed electronics technologies (PETs) are emerging technologies that addsignificant advantages compared tothe use of costly andinflexibleconventional electronic systems. PETs can also be edible, biocompatible, and conformable/stretchable. For example, NASArecently (May 2013) awarded a contractto a company to makefood “on-demand” fromingredients [1]—allowing for storage of ingredients instead of perishable preparedfood—meetingthe demandforfood on long distance travel, such as humans going to Mars by 2030. Other projects pursued by NASA include nanotechnologyink andidentifying ways PET can be effectivelyimplementedinto various aspects of spacecraft. Onerecentconcept funded by NASA[2] utilizes thecommercialtechnology of printed electronics to design and fabricate an entire end-to-end functional spacecraft—a significant technical challenge. The novel concept of applyingPET in a multi-functional platform drives the current state of the art for functionality,as well as introducingdesign and manufacturing compatibility challenges amongthe functional subsystems. Currentindustry growth and commercialinvestmentis expectedto advancethefunctionality of available basic building blocks and componentssynergistically with NASA’s needs.
PET is complementary to silicon chip technology, which industry continues to find special applications for, withsignificant cost per area andthroughput benefits. PET’s keyadvantagesand disadvantagesrelativeto conventional microelectronics aresummarized in Figure 1. Eventhough PETs have significant drawbacks on speed due to longer switch timeand device density,advantages include largeareaapplications, use offlexiblesubstrate,ease offabrication,and muchlowercost (which provides incentive for industry to continuously seek new applications). In summary, conventional electronics have continuously reduced cost per function (Moore’s Law); whereas PET reduces cost per area. Cost per function is still cheaper for silicontechnology because of the significant miniaturization of integratedcircuits(ICs) since their inception. Inaddition, to date,the performance of PETsinterms of actualfunction andreliabilityislessthanthat of conventional electronics.
Forecasters have gone as far as to predict that the market for PET will eventually outpace the silicon chip market; which itself grew from nothing to 200 billion dollars in about thirty years. The beginning of PET’s exponential growth starts now. For low-volume and high-precision applications, sheet-based techniques such as inkjet and screen printing, rather than roll-to-roll (R2R) printing, are best. For high-volume productions,such assolar cells, gravure, offset, andflexographic, printing methodologies are more common.
In addition to printability, other technology and process improvements are critical for the implementation of PET. These include optimization approaches for electrical functionality, functionalityadjustment,and mechanicalflexibility. Forexample, Figure 2summarizes details of keytechnology challenges from performanceimprovementto killer application.
Figure 1. Comparison of key characteristics of conventional and printed electronics as complementarytechnologies.
Figure 2. Areas oftechnology challengesfor printed electronicsfrom performanceimprovementto finding a killer(large volume) application.
Irrespective of definition, the progress of PET has lead to a multitude of possibilities in conception, design, fabrication, packaging,andapplication of devicesandcircuits. Afew keyaspects of PET discussedinthis report are summarizedin Figure 4. The report first focuses on roadmapsto provide a general survey ofthetechnology,with emphasis on ultralow volume applications. Detailed roadmaps
of current status andfuture growthtrends fromthree keyroadmapindustrysocieties—the organic electronics association (OE-A) [3], the international technology research society(ITRS)[4],and the international manufacturing initiative (iNEMI)[5] are presented.Then, specification-related activities by IEEE on generating specification for organic devices, by IPC addressing key design and assembly, and by other societies are discussed.
Finally, technology levels (hierarchy) are presented side-by-side, both for surface mount technology (SMT) and PET, in order to link the well-known established levels, e.g., device/package/system, in microelectronics with those potentiallevels for organic or printed electronics. This directcomparison better defines technology opportunitiesthat are in-line with the author’s experience,especially at the packaginglevel.
2
. PET
Roadmaps
2
.1 PET
Roadmap
O
rgan
iza
t
ions
Industry roadmap organizations have been created to addresstechnologytrends andtoanswers simple questions,such as what fields oftechnology do printed electronics encompass? Some examples are an interactive business card with a flexible display or a board game with a printed battery and flashing OLEDs.As shown,the scope and fields of applications for PET are highly diverse.A few years ago, anindustry organization was createdin Europeto categorize this diversity and to providesome guidance. One ofthese wasthe OE-A, whosefocus was creating communications and developing interfaces forthe various fields of research. The OE-A, with over 180 members worldwide,represents the entire value chain of organic electronics, fromthe materials,equipment,and product manufacturer to the end user and all applications. While many OE-A-generated concepts are still in the development phase, a series of applications are already in production. The OE-A recently published thefourth edition of theroadmap on organic and printed electronics.
The ITRS is the key industry roadmap provider for the conventional microelectronics field,and it is sponsored bythe world’s fiveleadingchip manufacturers. The objective oftheITRSisto ensure cost-effective advancementsinthe performance oftheintegrated circuit andthe productsthat employ such devices; thereby supporting the healthandsuccess ofthisindustry. Recently, in 2013,ITRS team members gathered to discuss trends in printed electronics and associated technology developments.
iNEMI, aconsortium of approximately 100leading electronics manufacturers, suppliers, associations, government agencies and universities, isanother industry roadmap provider. iNEMI roadmapscover the future technology requirements of the global electronics industry by identifying and prioritizing gapsin technologyandinfrastructure. With the support of participant companies, iNEMI generates timely,high-impact deployment projectsto address or eliminatethose gaps.On thePET roadmap,the 2013 iNEMI roadmap has a chapter on Large Area, Flexible Electronics that provides a comprehensive update to its first edition, released in 2011, and is based on a number of announcement made byindustry.The roadmaps for printed electronics provided by OE-A, ITRS, and iNEMi are further discussedinthe following sections.
2
.2 OE-
A
Roadmap
The OE-A, a working group within VDMA, was organized a few years ago to create a communication and developmentinterface for various fields of research. It representsthe entire value chain of organic electronics,fromthe materialssupplier and equipment and product manufacturer through to the user. The OE-A's goal is to issue roadmaps that serve as a guide to the multitude of technical developments and help to define possible applications. While many of the developments of OE-A members are stillinthetest phaseinthelab, a whole series of practical applications are already in use. The OE-A has published four roadmaps. An adapted summary version of the 4th map, which projects near-termtolong-term growthandapplications, isschematicallyshownin Figure 3. Here, thetechnology relatedtolighting and display are bundletogether rather shown separately.
Figure 3.Adapted OE-A roadmap showing near-, mid-, and long-term keytechnology projections for printed electronics.
Thethree key areas defined are:
1. Electronics and components covering radio frequencyidentification, batteries, printed memory for games, andtransparent conductors
2. Integrated smart systems includingphysical and chemical sensors, sensor arrays, and integrated displays
3. Organic photovoltaic (OPV), organiclight emitting diode (OLED), and flexible displays, which encompass a large number of applicationsin consumer electronics,lighting, and flexible/smart cards.
Because of the diversity of technology in this report, only the first two categories will be discussed further as potential applications for microelectronics systems inlow-volume applications. Inthe first category(electronics and components), printed RFID, memories, andflexible batteries haveshown significant progress with new applications. Other application areas added recently within this category are printed conductors and passive components, printed antennas, printed circuits, and transparent conductive films. The second category (integrated smart systems) brings together multi -function devices to perform complex automated tasks without the need for external electronic hardware. Suchsystem applications become more challenging, especially as technology progresses for organic and printed electronics. Atypical printed electronic system may have a powersector (batteries, miniaturizedfuel cells),input devices (physical,chemicaland biological sensors), and output devices (displays, visual, audible or hapticinterfaces and wireless communications)—all sections areintegratedtogether using sophisticatedlogic and memory.
2
.3 P
r
in
ted
RF
ID
Roadmap
RFIDs enablesthe electroniclabelingand wirelessidentification of objects usingradiofrequency communications. Because oflow-cost fabrication and ease of remoteidentification, RFIDtechnology is rapidly growing andis currently beingused for various applications. An RFID system consists of a tagreader(alsocalledtheinterrogator)andatag. Allcommunication betweenthetagandreader occurs completelythrough a wirelesslinkthatis sometimes called an airinterface. Through a
sequence of commands sent and received between both devices (calledtheinventory round), an RFID reader can identify the electronic product code (EPC) of an RFID tag. Figure 4 shows a basic block diagram of the tag/reader system. For passive tags, the basic idea is that the interrogator initiates an interrogationround witha querycommand. The querycommandessentially“wakes up”thetag, which responds withthe appropriateinformation.
Figure 4.Block diagram of atypical RFIDtag/reader system.
Printed RFID with limited functionality is a major solution for meeting the growing market demand for low cost and high-volume (see Figure 5).Thelogic circuit withthe memoryis printed onthe basis of either organic or printed electronics platform technology. The antenna can be either standard,like today(e.g., etched copper or aluminum), be printed with conductiveinks, or by other additive processes. Besidesthelow cost of printedtagsthey also have advantages duetotheir smaller thickness, flexibility, and better ecological properties compared to standard tags. Increases in frequency of datarateand memory are expectedto become maturein afew yearsforfull printed UHF RFID (at 800to 900MHZ). Communicationis another aspectthat iscontinually improving.
Figure 5.Roadmapfor printed RFID projection (OE-A, fourthedition[3]).
2
.4 ITR
S
PET
Roadmap
For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in its products-based miniaturization level. This is usually expressed as Moore’s Law, but is alsosometime calledscaling. The mostsignificanttrendisthe decreasing cost-per-function, which hasledto substantial improvementsin economic productivity and overall quality oflife through proliferation of computers, communication, and otherindustrial and consumer electronics. To help guide these R&D programs in scaling, the Semiconductor Industry Association (SIA) met with correspondingindustry associationsin Europe,Japan, Korea, and Taiwanto participatein a 1998 update of itsroadmap andto begin worktowardthefirstITRS, publishedin 1999. Sincethen,the ITRS has been updated in even years and fully revised in between years. The latest 2012 update is available onthe ITRS website[4]. Figure 6 showstheITRSroadmapfor printed CMOS Moore’s Law,and beyond whichis latercalled “Morethan Moore” orits abbreviation,MtM.
Figure 6. ITRS Roadmapfor printed CMOS Moore’s Law and beyond, MtM.
The ITRS projects that by 2020–2025, many physical dimensions are expected to be crossing the 10 nmthreshold.Itis expectedthat as dimensions approachthe 5–7 nmrangeit will be difficultto operate anytransistor structurethatis utilizing CMOS physics as itsbasic principle of operation. Itis also expectedthat new devices,likethe very promisingtunneltransistors, will allow a smooth transition from traditional CMOS to this new class of devices to reach these new levels of miniaturization. However,itis becoming clearthat fundamental geometricallimits will be reachedin the above timeframe. By fully utilizing the vertical dimension, it will be possible to stack layers of transistors on top of each other. This 3D approach will continue to increase the number of components per mm2 even when horizontal physical dimensions will no longer be amenable to any further reduction.
ITRS recognized the limitations of Moore’s law (i.e., linear scaling) and proposed a methodology to identifythose MtMtechnologiesfor which aroadmapping effortisfeasible and desirable. The semiconductor community needsto departfromthetraditional scaling “technology push” approach andinvolve new constituenciesinits activities. ITRS materialized this new approachin 2011, whenit added a MEMS chaptertothe roadmap, and also alignedit with iNEMI roadmap.The MEMS chapter aligns its efforttowards those MEMStechnologies associated with “mobileinternet devices,” a driving application broad enoughtoincorporate many existing and emerging MEMS technologies. Even thoughthereis noinformationinthe current ITRS roadmap on printed electronics, a few ITRS team members recently met twice in conjunction with the IEEE Advanced Packaging Materials Symposium (IEEE APM, March 2013) to discuss keytrends, current status,and potential applications for nanomaterials technology and display. Draft documents ofthetrendinthesetechnologies were generated and distributed to participant team members; these are yet to be released. Key discussion topics on printed electronics included conductors, semiconductors, and opaque technologies. Trends in semiconductors presentedinthe following areintended for discussion purpose only.
Sem
iconductors
1
. 1D
/2D
Carbon
(Carbon
nano
tubes
,
graphene)
Cos
t
Low-cos
t
s
ing
le
wa
l
l
CNTs
Pur
i
ty
Ch
ira
l
i
ty
con
tro
l
in
produc
t
ion
or
pur
if
ica
t
ion
a
t
low
cos
t
In
terconnec
t
of
Trans
is
tors
Ohm
ic
con
tac
ts
to
nano
tubes
for
power
de
l
ivery
Durab
i
l
i
ty
of
Dop
ing
Long-term
spa
t
ia
l
d
is
tr
ibu
t
ion
s
tab
i
l
i
ty
of
dopan
ts
2
. Po
lymers
H
igh
res
is
tance
=>
S
low
Trans
is
tors
Low
process
ing
temp
.
Temp
.
dependence
,
pho
ton
ic
,
degrada
t
ion
……
.
durab
i
l
i
ty
3
. 1D
/2D
S
i
a
. Too
ear
ly
for
us
to
forecas
t
:
We
don’
t
know
enough
today
2
.5 iNEM
I
PET
Roadmap
The 2013iNEMI’s Large Area, Flexible Electronics Roadmap Chapteris building uponthe 2011 first edition [5]. Itadded a comprehensive update based on a number of announcements made byindustry since theprevious publication.In addition, the iNEMI team identified paradigm shifts, enablers,and showstoppers (see Figure 7). One key paradigm is the transitionfromthe beginning ofthe 21st century visionfor completely printed electronic productsto‘hybrid’ products, wheretraditional electronic components are usedin combination with printed components. Other paradigm shifts include cost per area offunctionality versus cost perfunction forsiliconchipandintegration of electronicsin non-traditional objectsandlocations – ubiquitous electronics. Afew gaps andshow stoppers are alsoidentified and presented. For example,itstatesthatrate of commercialization of materials and manufacturing/processing equipment is occurring too slowly to meet the cost/performance/utility demandsto enable near-term productlaunches Additionally, the rate of development ofsystems must accelerate—otherwise a window of opportunity may be lost for a disruptorto commercialize a new competitive product.
Figure 7.iNEMI 2013roadmapidentification of paradigm shifts and enablers.
Seven areas of opportunity wereidentified by anindustrysurvey performed bytheiNEMIteam. Those surveyed further predicted that the near-term commercialization opportunities will continue to belighting, power(battery), and sensors(biological, chemical, andtouch)followedlater bythe introduction of RF devices (anti-tampering and authentication), photovoltaics, and displays. As with silicon-based component/subsystem technologies, it is envisioned that the technology and applications will mature over time, offering additional opportunitiesforintegrationinto product emulators. As an example, asthesetechnologies become morerobust,itis possiblethat memory products may be developedforthe Aerospace and Defenseindustries. Table 1 identifies potential opportunities forintegration as performanceimproves overthe next 10 years.
Table 1. iNEMI 2013 product emulators and potential application opportunities.
Near-term opportunities are classified as either 1) non-hybrid—an applicationthatis comprised of onlythe emergingtechnology or 2) hybrid—an applicationthatis manufactured usingtraditional electronics and devices, circuits, or components based on the new technology,e.g.,a product with a printed display module and asiliconIC RFfront-end. For non-hybrid application, onetechnical
barrier concernsthe development ofin-line manufacturing quality control equipment. To benefit from theeconomies ofscalethat R2Rand printing offers,systems must be developedand qualifiedfor testingofthe fabricated devices, circuits, and components.
Conversely, hybridflexibleelectronicssystemscomprised of printed electronics-based components (sensors, power,indicators, signage)integrated withtraditional electronics (surface mounttechnology for passive devices and silicon based ICs) continue to receive greater attention for near-term commercialization opportunities.In orderto achievefurther commercialization, a dedicated, hybrid manufacturing platform must be developed.iNEMI envisions that an R2R manufacturing platform combining several printingtechnologies (e.g.,flexography, gravure,and micro dispensing)is required to enable realization ofthe market potential.
3
. Spec
if
icat
ions
for
PET
3
.1 Key
Spec
i
f
ica
t
ions
IEEE wasamongthefirsttorecognize the importance of generatingstandards for PE devices and new emergingtechnologies, such as nanotechnology materials [6]. Recently, IPC-JPCA (IPC— Association Connecting Electronics Industries® and JPCA—Japan Electronics Packaging and Circuits Association) released ajointspecification, thefirst operational-levelstandard on printed electronics [7]. Other industry societies are joining this trend; representatives are listed in Figure 8. This Figureincludesthe IEEE P1620™ for nanomaterials, an element of PEtechnology.
Figure 8.Key specificationsfor printed electronicstechnology byindustry societies.
3
.2 IEEE
Spec
i
f
ica
t
ions
Itisinterestingto notethat during development of nanotechnology specification,theterm “anticipator standards” was used because thetechnology was not yet mature. The definition and benefits of the IEEE anticipator standards are:
1. Creation of standardsin anticipation ofthe manufacturing of value added products,
2. Provide an approachto help drive early commercializationin emerging fields andto promote acceptance among producers, users andthe public, and
3. Creation of a standing group, which provides a forumto consider new standards projects. The anticipator standards also guidethe development of white papersinto standards and revise existing standards, e.g.,the IEEE 802™ committee, which deals with both wired and wireless networking standards. This committee decided to startwith the family of anticipatory nanotechnology standards, IEEE P1650™ in particular. to focus first on material characterization methods and
equipment. Then, standards followed that concern device and componentfabrication andtesting, followed by systems architecture andinteroperability.
IEEE 1620-2008—Standardfor Test Methods forthe Characterization of Organic Transistorsand Materials. Thisstandardrecommends methods andstandardizedreporting practicesfor electrical characterization of printed and organic transistors. Due to the nature of printed and organic electronics, significant measurement errors can beintroducedifthe electrical characterization des ign-of-experimentis not properly addressed. It describesthe most common sources of measurement error, particularlyfor the high-impedance electrical measurements commonlyrequiredfor printed and organic transistors. It also suggests recommended practices in order to minimize and/or characterize theeffect of measurementartifactsand othersources oferrorencountered while measuring printed and organictransistors.
3
.3 IP
C
Spec
i
f
ica
t
ions
A few years ago, IPC stakeholders began to identify printed electronics as a potential game changer and suggested that the field should be closely monitored. The exploratory standards working group meeting held in late 2010 become the foundation for the present IPC Printed Electronics Standards Portfolio development effort(see Figure 9). A dynamicstrategy wasadopted by theIPC Printed Electronics Standards Committee(D60)torespond quickly based onindustrytrends and market dynamics with the formation of subcommittees(D61-D64)to effectively generatespecifications on PE. The status ofthese specifications are as follows.
Figure 9.IPC committee and subcommitteefor printed electronictechnology specification development and current specificationsidentification.
IPC-2291:Design Guidelines for Printed Electronics provides an overview ofthe design process flow for printed electronics based devices, modules and units, and final products. Theintent ofthis generic specification is to establish a design process flow that will facilitate and improve the practice of PE design. It is “generic” because it specifies only information that forms the basis for further specific declarations. Itisthereforeintendedto be usedin conjunction with other documents,as needed. IPC-4921, released June 2012: Requirements for Printed Electronics Based Materials, a key structural materialforthefield of PE coveringfivesubstrate categories. These categories capturethe broad families of substrate materials. As new substrate materials areintroducedintothe field of PEthey will be added to the list appearing in IPC-4921. The IPC-4921 document has been referred to as
fundamental for the field of printed electronics. Moreover, it is considered by many to beone of the most critical drivers of manufacturing innovation. The paradigm shift that flexible substrates offers fortransitioningfrom batchtoroll-fedandroll-to-roll manufacturingisconsidered paramountfor realization of vibrant new areas of manufacturing growth. Inits release announcement, IPC statesthat “IPC/JPCA-4921 provides a starting pointforIPC’s Printed ElectronicsInitiativeto establish a criticalsegment oftheinfrastructurethat will helptheindustry expand more quickly”. The IPC committee startedto work on Revision A ofthis specificationinlate 2013.
IPC/JCA 4591, released Dec. 2012: Requirement for Printed Electronics Functional Conductive Materials provides data to help users more easily determine material performance, capabilities,and compatibility of functional conductive materials for the manufacture of printed electronics. It includes: 1) classification schemes based on composition, conductor type, and post-processing structure; 2) functional conductive material specification sheets to present properties for the different conductive materialtypes; and 3) the mostcurrentclassificationsystem, qualificationand quality conformance requirements,includingthose raw material properties of particularinteresttothe printed electronics designer, fabricator, or other user. The IPC committee started to work on Revision A of thisspecificationinlate 2013. The word“Conductive” was dropped from the title to accommodate new printed materials.
IPC 6901, yetto bereleased: Performance Requirementsfor Printed Electronics Assemblies. Final Assembly Subcommittee metin 2012 and draftedthetable of contents forthis specification as stated intheIPC updated document. Thesubcommitteeidentified documentsfromISO defining RFID structures and ASTM defining membrane switches as possible reference documents.
4
. Techno
logies
and
H
ierarchy
4
.1 Su
r
face
Moun
t
Techno
logy
H
ie
ra
rchy
For Surface Mount Technology(SMT), packaging hierarchy has been expandedto define different manufacturing and system levels. A similar adoption byindustry for printed electronics elements and systemlevel definitions(e.g., defininginterconnects between systemlevels) allows value chain participantsto capture value and enableinnovation. Furthermore,the acceptance of definitions allows value chain members to develop materials and technologies optimized for use within specific system levels. TheJISSO International Council(JIC),comprised of Asian, Europeanand North American members, isaimed at promoting astrategic partnership among organizationsinterestedinthetotal solutionfor electronicsinterconnecting, assembling, packaging, mounting, andintegratingsystem design. Figure 10 shows a recent proposal by JISSO for expanding packaging hierarchy [8].
Figure 10.SMT packaging hierarchy presented by JISSO [8].
The definition ofinterconnection hierarchy includesthe following[5,8,9].
Level 0 - Electronic Element: The intellectual property of an item pertains to the idea or intelligence imported or described in a formal document (protocol, standards and/or specifications), design entity or patent disclosure. The information may be in hard or soft copy and can include computer code or data format as a part ofthe descriptive analysis. The characteristics are described astotheir physical, chemical, electrical, mechanical, electromechanical, environmental, and/or hazardous properties. Level 1 - Electronic Element: Uncased bare die or discrete components(e.g.,resistor, capacitor, diode,transistor,inductor, fuse), with metallization ortermination ready for mounting. This can be an IC or a discrete electrical, optical,or MEMS element. Individual elements cannot be further reduced without destroyingtheir stated function.
Level 2 - Electronic Package: A containerfor an individual electronic element or elements that protectsthe contents and providesterminalsfor making connectionstotherest ofthe circuit. The package outlineis generally standardized or meets guideline standards. The package may function as electronic, optoelectronic, or MEMS, or System in Package (SiP),and may in the future include bio -electronic sensors.
Level 3 - Electronic Module: A electronic sub-assembly with functional blocks, which is comprised of individual electronic elements and/or component packages. Anindividual module having an application-specific purpose including electronic (including SiP), optoelectronic, or mechanical (MEMS). The module generally provides protection of its elements and packages, depending on the
applicationto assurethe requiredlevel of reliability. The module may be a company standard (catalog item) orcustom (OEM-specific). Note:there willlikely be some subdivisions of Level 2 and Level 3 descriptionstoincreasethe granularity and clarityrelativeto whatisincluded within each ofthese levels.
Level 4 - Electronic Unit: Any group of functional blocksthat have been designedto provide a single or complexfunction needed by asystemin orderforthesystemtoserve aspecific purpose. The electronic unit may be comprised of electronic elements, component packages and/or application -specific modules. The function of the electronic unit may be electronic, optoelectronic, electromechanical, or mechanical or any combinationthereof. The function mayinthe futureinclude bio-electronic applications.
Level 5 - Electronic System: A completed, market ready unit dedicated to combining and interconnecting functional blocks. The functional blocks are generally comprised of electronic units, but may also include electronic modules, electronic packages, or electronic elements. The electronic system productcanincludethecabinetry,a backplane or motherboardinto whichthe assemblies, modules, packages, or elements areinserted andthe cabling(electrical, optical, or mechanical) needed to interconnect the total functional block(s) into a configured system. The electronic system can varyin complexity from very simpleto highly complex.
The interconnect hierarchy has evolved since the introduction of the transistor in 1960[9].Figure 11 compares the traditional view of the hierarchy (lower left) to the emerging microelectronic technologies with growing ambiguityininterconnectionlevel definition. In the early days,the divisions oflevels forthe varioustasksinvolvedinthecreation ofanelectronic system were well defined. The semiconductor manufacturer createdtheintegrated circuits(IC);the IC chips were packaged for protection;a printedcircuitfacility build asubstrate accordingtoa design. Next, the package was assembled onto board using soldering process and used as “daughter card” for thenext assembly of motherboard. The completed assembly wouldthen be packagedin asuitable format, whether a computer,telephoneswitch, internetrouter, or any other product. Now,there are new interconnections, such as a wafer-level packages and 3D stacks; some lack a clear category or definition. The blue areainthe Figure shows added newinterconnections withlack of clear category; therefore, there is a need to find a way to embrace the emerging technologies that are already being deployedto create next generation products.
Figure 11.Expansion of SMT packaging hierarchy withinclusion of new developments in packaging, includingwaferlevels and 3D stacks[9].
4
.2 P
r
in
ted
E
lec
t
ron
ics
Techno
logy
H
ie
ra
rchy
Forthe purpose of comparisonto printed electronictechnology, keysystemlevels of SMT can be simply defined asfollows: a) Level 0 - siliconIC, b) Level 1- IC packaging,c) Level 2 - printed wiring board(PWB) manufacturing and board assembly, d) Level 3 - interconnections between different PWB’s, e) Level 4 - assembly ofthe PWBinto racks, housings of product, etc., and f) Level 5 - connection of severalindividual products or systems.
For printed electronicstechnology,levels of hierarchy can be definedsimilarto those of silicon, drivingthe SMT hierarchy as shownin Figure 12.
Figure 12.Comparison of SMT and PET device/package/system hierarchy.
The PET hierarchy can be simply defined as follows [10]:
• Level 0, basic material elements for PET system operations such as organic andinorganic functionalinks.Functionalinks haveintrinsic properties such as – emittinglightin OLEDs devices, energy harvestingin OPV cells, piezo/ pyro effectsin sensors, and conductivityin traces and antennas.
• Level 1, packaginglevel or functionallayers for PET. Thefunctional layers can be fabricated on a coated paper, plastic or metal foil. It can be a singlelayer such asin the case of a
conductor (e.g.,an antenna),printed electronics,orit can be combination of multiplelayers. For sensors,three or more (structured)layers can be used, while for OLEDs and OPVsthe number oflayers can be much higher.
• Level 2,the system-in-foillevel,is defined asthe combining of stacks of functionallayers, e.g.,theintegration of a first stack having an antenna with a second stack havinglogic. Another exampleisthe front and back planesthat form a display. The stacks may be based on differenttechnologies and couldinclude embedded or mounted ICs or SMT components
(resistors, capacitors,inductors, etc.). Also, stacksthat form Level 2 can beindividually tested.
• Level 3,the smart-systemlevel, representsthe hierarchicallevel where multiple system-in -foils areintegrated or linkedtogether. Theindividual system-in-foils are pretested and sorted to ensure high yield ofthe smartsystem. Typical examplesinclude batteries and displays connected with other system-in-foilsto provide power and visual contentto an existing printed system design.
• Level 4,the systemintegrationlevel, definesthelevel at which smart systems areintegrated into or mounted onto a structural housing, frame, package, etc. Thislevelis enabled dueto the novel feature provided bythistechnology– flexible design forintegration,e.g.laminate, attach.
• Level 5,the ambientintelligencelevel,isthe highestlevel andis characterized whenthe system has a “touch-point”tothe rest ofthe world - hierarchylevel whenthe functional productisintegrated withits surroundings. As an example,thisisthelevel at which OPV or OLED systems are connectedtothe power grid orlightinginfrastructure. A variety of connection methods can be used,such as RF or optical hardware.
Figure 13 summarizes the hierarchy for large area smart systems.The range encompasses large area smart systems, withlevel 0 asthin film electronics build by multi-organic/inorganic functionalink to level 5,which covers connectivitythatenables an objectto become “smart”.
Figure 13.Hierarchy device/packaging/systemslevelsforlarge area printed electronic sensors.
4
.3 Pr
in
ted
E
lec
t
ron
ics
Techno
logy
Pe
r
fo
rmance
The technology performance parameters discussed in this section are more “fundamental” and describe fundamental material, device or process properties rather than specific requirement for each application. Here, only asmall number ofthe keytechnology parametersidentifiedforthe various applications arelisted, emphasizingthosethat are relevantto a number of applications[9].
• Mobility/electrical performance (threshold voltage, on/off current):the performance
(operating frequency, current driving capacity) ofthe circuits depends onthe carrier mobility ofthe semiconductor,the conductivity ofthe conductor andthe dielectrical behavior ofthe dielectric materials.
• Resolution/registration:the performance (operating frequency, current driving capacity) and reliability ofthe circuits depends onthelateral distance ofthe electrodes (resolution) within the devices (e.g.transistors) andthe overlay accuracy (registration) between different patternedlayers.
• Barrier properties/environmental stability:thelifetime depends on a combination ofthe sensitivity ofthe materials and devicesto oxygen and moisture, as well asthe barrier properties of protectivelayers, substrates and sealants against oxygen and moisture. The necessary barrier properties vary forthe different applications over several orders of magnitude.
• Flexibility/bending radius:thin form factors and flexibility ofthe devices are key advantages of organic and printed electronics. In orderto achieve reliable flexibility and even rollable devices materials, design and process haveto be chosen carefully.
• Fit of process parameters (speed,temperature, solvents, ambient conditions, vacuum,inert gas atmosphere):in orderto have a sufficient working system,itisimportantto adjustthe parameters ofthe different materials and devices usedto build organic and printed electronics.
• Yield:low cost electronicsin high volumes are only possible whenthe processes allow production at high yields. Thisincludes safe processes, adjusted materials and circuit designs as well as anin-line quality control.
5
. Add
it
ive
Manufactur
ing/3D
Pr
int
ing
5
.1 In
t
roduc
t
ion
Additive manufacturing (AM) or 3D printing is a process for building up a three-dimensional solid object, layer-by-layer, from a 3D digital model.Itis an additive process, contrary to traditional machining, which is a subtractive process. Innovation in AM technology is critical for wider applications. On May 9, 2013, the US government announced a competitionto createthree new manufacturinginnovationinstitutes acrossfive agencies. NASA has beenfully engaged withthe partnersin the National Additive Manufacturing Innovation Institute (NAMII, a.k.a, America Makes); itrecognizesthat on Earth and potentiallyin space, additive manufacturing can be game-changing for new mission opportunities. Theadditive manufacturing technologiesexpected to significantly reduce production time and cost by'printing' tools, engine parts or even entire spacecraft. The 3-D printing manufacturing offers opportunitiesto optimizethefit,form, and deliverysystems of materialsthat will enable space missions while directly benefiting American businesses here on Earth.
5
.2 Key
AM
fo
r
Me
ta
l
l
ic
Ma
te
r
ia
ls
Applying additive manufacturing to aerospace has been emphasized by the development of h igh-value materials such as Ti-based alloys and Ni-based superalloys [12-15 ]. Ti-based alloys, specifically Ti-6Al-4V, are commonly usedinspace applications⎯thereare over 1000 Ti-6Al-4V partsin onespacecraftincluding parts with complex geometry. This category of parts is expensive andtime consumingtofabricate using conventional manufacturing becausetitaniumis generally difficult to process and to machine. These challenges make Ti-6Al-4V parts an ideal target for using additive processes.
The most common AM approaches forthe manufacturing of metal parts are:(1) the powder bed fusion processessuchas electron beam melting(EBM),(2) selectivelaser melting(SLM),and (3) direct energy deposition such as laser engineered near shaping (LENS). Presently, the EBM appears to bethe most mature methodologyfor building upfabrication of Ti-6Al-4V partssincethere also exists some materials property database;a number of aerospace parts are already fabricated.A large number of aerospace companies have developed, produced, characterized and approved some EBM-processed Ti-6Al-4V parts.
The AM version of Ti-6Al-4V can compete with its wrought version. In a recent study [12], it was shown that the static and dynamic mechanical properties of Ti-6Al-4V, which was electron beam melted plus hotisostatic pressed(HIP), become comparable to or exceed their classical wrought annealed properties. The author recommendedto acceleratetheinfusion of 3Dprinting for spaceflight applications by developing the statistical property database for effectively using the additive manufacturing technologies.
Key advantages and disadvantages of using AM materials are:. Advantages of additive manufacturing:
• Reductionin cost of manufacturing (e.g., about 50%less for Ti-6Al-4V) • Production of parts issignificantly faster (e.g., twiceas fastr for Ti-6Al-4V)
• Manufacturing of complex geometries and designs are possible, which cannot be done by traditional processes
• A higher manufacturing flexibility. Parts can be quickly replacedif needed
• A greener manufacturing process since it produces muchlower waste scrapcompared with subtractive material process with significant scraps (e.g., morethan75%less scrap for Ti-6A l-4V)
• The development of gradient alloy is possible[12] • Improvementin properties of some material is possible • Reductionin cost/timein building prototypes
• Multipleiterations of a prototype can be easily made
• Reductionintimefor design reviews and manufacturing steps
• Detection of discrepanciesin designs andfast revision duringthe early stages ofthe project Disadvantages of additive manufacturing:
• Better suited for production of smaller runs only. AMtechniquestendto be more expensive forlarge production runs
• Better suited for production of smaller part sizes only.Presently,low build speeds and technicallimitationstendtolimit AMtoshapes where relatively smaller parts (such as one cubic foot) are needed.
• Lack of database for materials properties. Currently,publically available dataisinadequate for designing of flight-quality AM parts.
5
.3 AM
Ma
te
r
ia
ls
and
Cha
l
lenges
Additive manufacturing offersanideal platformfor developing new productsandapplications.It createsthe material(i.e.the metallurgy)locallyinthelaser or electron beamfocus duringthe production of the part. This gives unprecedented possibilities to create new, tailored materials and/or material gradients,including materials that cannot be manufactured by other means. Duetothe additive build-up ofthe parts,itis also possibleto varythe geometry andtheinternal structure ofthe material by numerous methods, which offers possibilities for designing and optimizing part properties and behavior by geometrical layering,inadditiontochemical bonding. Theresultisanexpanded range of possibilities for designing partsto be produced by AM inthe future.
Recently, the additive manufacturing industry has grown significantly with markets including prototyping,tooling, direct part manufacturing, and maintenance andrepair. Theintroduction of aerospace materialsfor AM has beensuccessfulinincreasing acceptance,and hasalreadyledto many requests for additional materials. Since a very broad range of metal materials can be processed bythistechnique,itisto be expectedthatthe number andrange of aerospace and commercially available materials will continueto grow.
Additive manufacturing was the subject of the NASA administrator’s message when he was summarizing the development of technology for the future [16]. Briefly stating a number of innovations, it cited the joint effort with Aerojet Rocketdyne that hot-fire tested a “3D printed rocket engineinjector”,enabling a first stepin using AM to supportwider space applications.The citation is a referenceto a previous official announcement [17]that two rocket engineinjectors made with a 3D printer performed as well astraditionally constructed parts duringthe hot-firetests, whichexposed themtotemperatures approaching 6,000°F (3,316°C) and extreme pressures.
Despite significant progress in the AM field,a number oftechnicalchallengesrelatedto materials, equipment, and applicationsremain.Issuessuch as material characterization and development of statistical property database, material development, process control, process understanding in modeling, machine qualification and modularity among others have beenidentified byindustry as areasforimprovement. Though manyissues are being examined by researcherteams inacademia, industry,and government, itis perceivedthatcoherenteffortsamongthese teams with appropriate funding willenable resolutions oftechnical challenges andfasterimplementation ofthe additive manufacturingtechnology.
6
. Summary
Printed electronics takes over where silicon chips cannot cope. For example, PE can provide simple electronic circuits at one tenth of the cost of those in a simple silicon chip,but it can also be edible, stretchable, conformal(fitting over unevensurfaces), eventransparent,though not simultaneously. NASArecently funded JPL and industry partners for usingthistechnology to addressits effective implementation into variousaspects ofspacecraft. The conceptis “to apply printed electronicsin multi-functional platform byimplementingeverysubsystemthataspacecraft might needfromthe scientific sensorthroughthe data downlink and haveit survive and functionin a space environment.” If toinclude otheraspects ofthistechnology such as nanotechnology and additive manufacturing, then, NASAis heavilyinvolved in advancingtheprinted electronics and 3D technologiesforward. While a “killer application”for printed electronicstechnology has yetto beidentified allowing industry to focus on the development of key technologies and supply chains; nevertheless, there are numerous unique applications emergingthat will changethe direction of electronics. Afew key points on PET discussed inthis reportare summarized below:
• Itis forecastedthatthe PET market will outpace silicon chip electronics because ofits ubiquity.
• For ultralow volume and precision applications, sheet basedtechniques such as inkjet and screen printing withink or other materials are more suitable.
• Itis advisableto continuously reviewingroadmaps generated from keyindustryincluding OE-A, ITRS, andiNEMIto definethe pulse of development and potential areas for application and furtherinvestigation.
• Review and adoptor adapt applicability ofindustry specifications,includingthose by IEEE and IPC.
• To meetthe current needs of microelectronics applications, a hybrid approach combiningthe advantages of both silicon chip and printed electronics may be considered.
• Understanding thehierarchy of device/package/systems enables usersto better define key implementation and reliability challenges for effectiveuse of PETs.
• Briefly discussed keytechnology performance parameters for various applications. These included electrical performance, resolution, environmental stability,level of flexibility, process parameters, and yield.
• Briefly discussed additive manufacturing, a.k.a,three-dimensional (3D) printing, approaches; theiradvantages and disadvantages for use of high value metallic materials such as Ti-6A l-4V. Also, briefly discussed future needs andtechnical challenges for effective
implementation oftheAMtechnology.
Understanding key technology development and the characteristics of printed electronics technologies and additive manufacturing—advantages and disadvantages—are important in judiciallyselecting and narrowingthe follow-up applicable technology,and quality assurance and reliability test methodsin preparationforlow-riskinsertion into electronic or non-electronics systems for NASA use.
