Specifications GAL22V10

(1)

Specifications

GAL22V10

• HIGH PERFORMANCE E2_CMOS®_TECHNOLOGY — 4 ns Maximum Propagation Delay

— Fmax = 250 MHz

— 3.5 ns Maximum from Clock Input to Data Output — UltraMOS®_{Advanced CMOS Technology}

• ACTIVE PULL-UPS ON ALL PINS

• COMPATIBLE WITH STANDARD 22V10 DEVICES — Fully Function/Fuse-Map/Parametric Compatible

with Bipolar and UVCMOS 22V10 Devices

• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR — 90mA Typical Icc on Low Power Device

— 45mA Typical Icc on Quarter Power Device • E2_{CELL TECHNOLOGY}

— Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms) — 20 Year Data Retention

• TEN OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs • PRELOAD AND POWER-ON RESET OF REGISTERS

— 100% Functional Testability • APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing — Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

DESCRIPTION

The GAL22V10, at 4ns maximum propagation delay time, com-bines a high performance CMOS process with Electrically Eras-able (E2_{) floating gate technology to provide the highest} perform-ance available of any 22V10 device on the market. CMOS cir-cuitry allows the GAL22V10 to consume much less power when compared to bipolar 22V10 devices. E2_{technology offers high} speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.

The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL22V10 is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V10 devices. Unique test circuitry and reprogrammable cells allow complete

FUNCTIONAL BLOCK DIAGRAM FEATURES

PIN CONFIGURATION

GAL22V10

High Performance E

2

_{CMOS PLD}

Generic Array Logic™

PROGRAMMABLE

AND-ARRAY

(132X44)

I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I/CLK I I I I I I I I I I RESET PRESET 8 10 12 14 16 16 14 12 10 8 OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC

GAL22V10

Top View

PLCC

1 24 I/CLK I I I I I I I I Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q 6 18

GAL

22V10

2 28 NC I/CLK I I I I I I I I NC NC I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Vcc I/O/Q I/O/Q 4 26 25 19 18 21 23 16 14 12 11 9 7 5

DIP

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Specifications

GAL22V10

) s n ( d p T Tsu(ns) Tco(ns) Icc(mA) Ordering# Package 4 2.5 3.5 140 GAL22V10D-4LJ 28-LeadPLCC 5 3 4 150 GAL22V10C-5LJ 28-LeadPLCC 5 . 7 5 4.5 140 GAL22V10C-7LP 24-PinPlasticDIP 5 . 4 4.5 140 GAL22V10C-7LJ 28-LeadPLCC 5 . 6 5 140 GAL22V10B-7LP 24-PinPlasticDIP 0 4 1 GAL22V10B-7LJ 28-LeadPLCC 0 1 7 7 55 GAL22V10D-10QP 24-PinPlasticDIP 5 5 GAL22V10D-10QJ 28-LeadPLCC 0 3 1 GAL22V10D-10LP,GAL22V10C-10LPorGAL22V10B-10LP 24-PinPlasticDIP 0 3 1 GAL22V10D-10LJ,GAL22V10C-10LJorGAL22V10B-10LJ 28-LeadPLCC 5 1 10 8 55 GAL22V10D-15QPorGAL22V10B-15QP 24-PinPlasticDIP 5 5 GAL22V10D-15QJorGAL22V10B-15QJ 28-LeadPLCC 0 3 1 GAL22V10D-15LPorGAL22V10B-15LP 24-PinPlasticDIP 0 3 1 GAL22V10D-15LJorGAL22V10B-15LJ 28-LeadPLCC 5 2 15 15 55 GAL22V10D-25QPorGAL22V10B-25QP 24-PinPlasticDIP 5 5 GAL22V10D-25QJorGAL22V10B-25QJ 28-LeadPLCC 0 9 GAL22V10D-25LPorGAL22V10B-25LP 24-PinPlasticDip 0 9 GAL22V10D-25LJorGAL22V10B-25LJ 28-PinPLCC ) s n ( d p T Tsu(ns) Tco(ns) Icc(mA) Ordering# Package 5 . 7 5 4.5 160 GAL22V10C-7LPI 24-PinPlasticDIP 5 . 4 4.5 160 GAL22V10C-7LJI 28-LeadPLCC 0 1 7 7 160 GAL22V10C-10LPI 24-PinPlasticDIP 0 6 1 GAL22V10C-10LJI 28-LeadPLCC 5 1 10 8 150 GAL22V10D-15LPIorGAL22V10B-15LPI 24-PinPlasticDIP 0 5 1 GAL22V10D-15LJIorGAL22V10B-15LJI 28-LeadPLCC 0 2 14 10 150 GAL22V10D-20LPIorGAL22V10B-20LPI 24-PinPlasticDIP 0 5 1 GAL22V10D-20LJIorGAL22V10B-20LJI 28-LeadPLCC 5 2 15 15 150 GAL22V10D-25LPIorGAL22V10B-25LPI 24-PinPlasticDIP 0 5 1 GAL22V10D-25LJIorGAL22V10B-25LJI 28-LeadPLCC

GAL22V10 ORDERING INFORMATION

Commercial Grade Specifications

PART NUMBER DESCRIPTION

Industrial Grade Specifications

Blank = Commercial

I = Industrial

Grade

Speed (ns)

XXXXXXXX

XX

X

X X

Device Name

_

GAL22V10D

GAL22V10C

GAL22V10B

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Specifications

GAL22V10

OUTPUT LOGIC MACROCELL (OLMC)

OUTPUT LOGIC MACROCELL CONFIGURATIONS

GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)

Each of the Macrocells of the GAL22V10 has two primary func-tional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are nor-mally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page.

REGISTERED

In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by

NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins.

COMBINATORIAL I/O

In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term The GAL22V10 has a variable number of product terms per

OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 14 and 23, DIP pinout), two have ten product terms (pins 15 and 22), two have twelve product terms (pins 16 and 21), two have fourteen product terms (pins 17 and 20), and two OLMCs have sixteen product terms (pins 18 and 19). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low.

The GAL22V10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asyn-chronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all reg-isters to a logic one on the rising edge of the next clock pulse after this product term is asserted.

NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen.

A R S P D Q Q C L K 4 T O 1 M U X 2 T O 1 M U X

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Specifications

GAL22V10

REGISTERED MODE

ACTIVE HIGH ACTIVE LOW

COMBINATORIAL MODE

ACTIVE HIGH ACTIVE LOW S₀ = 1 S₁ = 1 S₀ = 0 S₁ = 1 S₀ = 0 S₁ = 0 S₀ = 1 S₁ = 0 A R S P D Q Q C L K A R S P D Q Q C L K

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Specifications

GAL22V10

GAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP

DIP (PLCC) Package Pinouts

1 (2) 22 (26) OLMC S0 5810 S1 5811 0440 . . . . 0880 2 (3) ASYNCHRONOUS RESET (TO ALL REGISTERS) 0 4 8 12 16 20 24 28 32 36 40 10 (12) 0000 0044 . . . 0396 ₅₈₀₈S0 23 (27) S1 5809 21 (25) OLMC S0 5812 S1 5813 0924 . . . . . 1452 3 (4) 4 (5) 5 (6) 20 (24) OLMC S0 5814 S1 5815 1496 . . . . . . 2112 19 (23) OLMC S0 5816 S1 5817 2156 . . . . . . . 2860 18 (21) OLMC S0 5818 S1 5819 2904 . . . . . . . 3608 17 (20) OLMC S0 5820 S1 5821 3652 . . . . . . 4268 OLMC S0 5822 S1 5823 4312 . . . . . 4840 8 (10) 16 (19) 15 (18) OLMC S0 5824 S1 5825 4884 . . . . 5324 9 (11) 5368 . . . 5720 14 (17) OLMC S0 5826 S1 5827 7 (9) 6 (7) 8 10 14 16 12 12 16 14 10 8 _OLMC

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Specifications

GAL22V10

ABSOLUTE MAXIMUM RATINGS

(1)

Supply voltage V

_CC

...

-

0.5 to +7V

Input voltage applied ... -2.5 to V

_CC

+1.0V

Off-state output voltage applied... -2.5 to V

_CC

+1.0V

Storage Temperature ... -65 to 150

°

C

Ambient Temperature with

Power Applied ... -55 to 125

°

C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).

RECOMMENDED OPERATING COND.

Commercial Devices:

Ambient Temperature (T

_A

) ... 0 to +75

°

C

Supply voltage (V

_CC

)

with Respect to Ground ... +4.75 to +5.25V

Industrial Devices:

Ambient Temperature (T

_A

) ... -40 to 85

°

C

Supply voltage (V

_CC

)

with Respect to Ground ... +4.50 to +5.50V

Specifications

GAL22V10D

COMMERCIAL

I

CC Operating Power VIL = 0.5V VIH = 3.0V L-4 — 90 140 mA

Supply Current ftoggle = 15MHz Outputs Open L-15 — 90 130 mA

L-25 — 75 90 mA

Q-10/-15/-25 — 45 55 mA

V

IL Input Low Voltage Vss – 0.5 — 0.8 V

V

IH Input High Voltage 2.0 — Vcc+1 V

I

IL1 _{Input or I/O Low Leakage Current} _0V≤_V

IN≤ VIL (MAX.) — — –100 µA

I

IH Input or I/O High Leakage Current 3.5V ≤ VIN≤ VCC — — 10 µA

V

OL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V

V

OH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

I

OL Low Level Output Current — — 16 mA

I

OH High Level Output Current — — –3.2 mA

I

OS2 _{Output Short Circuit Current} _V

CC = 5V VOUT = 0.5V T_A = 25°C –30 — –130 mA

DC ELECTRICAL CHARACTERISTICS

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.3 _MAX. _UNITS

INDUSTRIAL

I

CC Operating Power VIL = 0.5V VIH = 3.0V L-15/-20/-25 — 75 150 mA

Supply Current ftoggle = 15MHz Outputs Open

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested.

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Specifications

GAL22V10

-4 MIN. MAX.

t

pd A Input or I/O to Comb. Output 1 4 1 10 3 15 3 20 3 25 ns

t

co A Clock to Output Delay 1 3.5 1 7 2 8 2 10 2 15 ns

t

cf2 _— _{Clock to Feedback Delay} _— _2.5 _— _2.5 _— _2.5 _— ₈ _— ₁₃ _ns

t

su — Setup Time, Input or Fdbk before Clk↑ 2.5 — 7 — 10 — 14 — 15 — ns

t

h — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — ns

A Maximum Clock Frequency with 167 — 71.4 — 55.5 — 41.6 — 33.3 — MHz

External Feedback, 1/(tsu + tco)

f

max3 _A _{Maximum Clock Frequency with} ₂₀₀ _— ₁₀₅ _— ₈₀ _— _45.4 _— _35.7 _— _MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 250 — 105 — 83.3 — 50 — 38.5 — MHz

No Feedback

t

wh — Clock Pulse Duration, High 2 — 4 — 6 — 10 — 13 — ns

t

wl — Clock Pulse Duration, Low 2 — 4 — 6 — 10 — 13 — ns

t

en B Input or I/O to Output Enabled 1 5 1 10 3 15 3 20 3 25 ns

t

dis C Input or I/O to Output Disabled 1 5 1 9 3 15 3 20 3 25 ns

t

ar A Input or I/O to Asynch. Reset of Reg. 1 4.5 1 13 3 20 3 25 3 25 ns

t

arw — Asynch. Reset Pulse Duration 4.5 — 8 — 15 — 20 — 25 — ns

t

arr — Asynch. Reset to Clk↑ Recovery Time 3 — 8 — 10 — 20 — 25 — ns

t

spr — Synch. Preset to Clk↑ Recovery Time 3 — 10 — 10 — 14 — 15 — ns

Specifications

GAL22V10D

-10 MIN. MAX. -25 MIN. MAX. -20 MIN. MAX. -15 MIN. MAX.

AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

UNITS

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C_I Input Capacitance 8 pF V_CC = 5.0V, V_I = 2.0V

C_I/O I/O Capacitance 8 pF V_CC = 5.0V, V_I/O = 2.0V

*Characterized but not 100% tested.

CAPACITANCE (T

_A

= 25

°

C, f = 1.0 MHz)

PARAM. _COND.TEST1 DESCRIPTION

COM / IND IND COM / IND

COM COM

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Specifications

GAL22V10

Specifications

GAL22V10C

ABSOLUTE MAXIMUM RATINGS

(1)

Supply voltage V

_CC

...

-

0.5 to +7V

Input voltage applied ... -2.5 to V

_CC

+1.0V

Off-state output voltage applied ... -2.5 to V

_CC

+1.0V

Storage Temperature ... -65 to 150

°

C

Ambient Temperature with

Power Applied ... -55 to 125

°

C

COMMERCIAL

I

CC Operating Power Supply Current VIL = 0.5V VIH = 3.0V L-5 — 90 150 mA

ftoggle = 15MHz Outputs Open L-7 — 90 140 mA

L-10 — 90 130 mA

V

I

IL1 _{Input or I/O Low Leakage Current} _0V≤_V_IN≤_V_IL_(MAX.) _— _— _–100 µ_A

I

V

I

OS2 _{Output Short Circuit Current} _V_CC_{= 5V} _V_OUT_{= 0.5V T}

A = 25°C –30 — –130 mA

RECOMMENDED OPERATING COND.

Commercial Devices:

Ambient Temperature (T

_A

) ... 0 to +75

°

C

Supply voltage (V

_CC

)

with Respect to Ground ... +4.75 to +5.25V

Industrial Devices:

Ambient Temperature (T

_A

) ... -40 to 85

°

C

Supply voltage (V

_CC

)

with Respect to Ground ... +4.50 to +5.50V

DC ELECTRICAL CHARACTERISTICS

INDUSTRIAL

I

CC Operating Power Supply Current VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA

ftoggle = 15MHz Outputs Open

(9)

Specifications

GAL22V10

t

pd A Input or I/O to Combinatorial Output 1 5 1 7.5 1 7.5 3 10 1 10 ns

t

co A Clock to Output Delay 1 4 1 4.5 1 4.5 2 7 1 7 ns

t

cf2 _— _{Clock to Feedback Delay} _— ₃ _— ₃ _— ₃ _— _2.5 _— _2.5 _ns

t

su — Setup Time, Input or Fdbk before Clk↑ 3 — 4.5 — 5 — 7 — 7 — ns

t

A Maximum Clock Frequency with 142.8 — 111 — 105 — 71.4 — 71.4 — MHz

f

max3 _A _{Maximum Clock Frequency with} ₁₆₆ _— ₁₃₃ _— ₁₂₅ _— ₁₀₅ _— ₁₀₅ _— _MHz

A Maximum Clock Frequency with 200 — 166 — 142.8 — 105 — 105 — MHz

No Feedback

t

wh — Clock Pulse Duration, High 2.5 — 3 — 3.5 — 4 — 4 — ns

t

wl — Clock Pulse Duration, Low 2.5 — 3 — 3.5 — 4 — 4 — ns

t

en B Input or I/O to Output Enabled 1 6 1 7.5 1 7.5 3 10 1 10 ns

t

dis C Input or I/O to Output Disabled 1 6 1 7.5 1 7.5 3 9 1 9 ns

t

ar A Input or I/O to Asynch. Reset of Reg. 1 5.5 1 9 1 9 3 13 1 13 ns

t

arw — Asynch. Reset Pulse Duration 5.5 — 7 — 7 — 8 — 8 — ns

t

Specifications

GAL22V10C

AC SWITCHING CHARACTERISTICS

UNITS

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these parameters.

PARAM TEST

COND.1 DESCRIPTION

CAPACITANCE (T

_A

= 25

°

C, f = 1.0 MHz)

-5 MIN. MAX. COM/IND COM -7 (PLCC) MIN. MAX. -10 MIN. MAX. -7 (PDIP) MIN. MAX. COM COM/IND -10 MIN. MAX. IND

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Specifications

GAL22V10

Specifications

GAL22V10B

ABSOLUTE MAXIMUM RATINGS

(1)

Supply voltage V

_CC

...

-

0.5 to +7V

Input voltage applied ... -2.5 to V

_CC

+1.0V

Off-state output voltage applied ... -2.5 to V

_CC

+1.0V

Storage Temperature ... -65 to 150

°

C

Ambient Temperature with

Power Applied ... -55 to 125

°

C

RECOMMENDED OPERATING COND.

Commercial Devices:

Ambient Temperature (T

_A

) ... 0 to +75

°

C

Supply voltage (V

_CC

)

with Respect to Ground ... +4.75 to +5.25V

Industrial Devices:

Ambient Temperature (T

_A

) ... -40 to 85

°

C

Supply voltage (V

_CC

)

with Respect to Ground ... +4.50 to +5.50V

DC ELECTRICAL CHARACTERISTICS

V

I

IL1 _{Input or I/O Low Leakage Current} _0V≤_V_IN≤_V_IL_(MAX.) _— _— _–100 µ_A

I

V

I

OS2 _{Output Short Circuit Current} _V_CC_{= 5V} _V_OUT_{= 0.5V T}

A = 25°C –30 — –130 mA

COMMERCIAL

I

CC Operating Power VIL = 0.5V VIH = 3.0V L-7 — 90 140 mA

Supply Current ftoggle = 15MHz Outputs Open L-10/-15 — 90 130 mA

L-25 — 75 90 mA

Q-15/-25 — 45 55 mA

INDUSTRIAL

I

CC Operating Power VIL = 0.5V VIH = 3.0V L-15/-20/-25 — 90 150 mA

Supply Current ftoggle = 15MHz Outputs Open

(11)

Specifications

GAL22V10

Specifications

GAL22V10B

-10 MIN. MAX. -25 MIN. MAX. -20 MIN. MAX. -15 MIN. MAX. -7 MIN. MAX.

AC SWITCHING CHARACTERISTICS

t

pd A Input or I/O to Comb. Output 3 7.5 3 10 3 15 3 20 3 25 ns

t

co A Clock to Output Delay 2 5 2 7 2 8 2 10 2 15 ns

t

cf2 _— _{Clock to Feedback Delay} _— _2.5 _— _2.5 _— _2.5 _— ₈ _— ₁₃ _ns

t

su₁ — Setup Time, Input or Fdbk before Clk↑ 6.5 — 7 — 10 — 14 — 15 — ns

t

su₂ — Setup Time, SP before Clock↑ 10 — 10 — 10 — 14 — 15 — ns

t

A Maximum Clock Frequency with 87 — 71.4 — 55.5 — 41.6 — 33.3 — MHz

f

max3 _A _{Maximum Clock Frequency with} ₁₁₁ _— ₁₀₅ _— ₈₀ _— _45.4 _— _35.7 _— _MHz

A Maximum Clock Frequency with 111 — 105 — 83.3 — 50 — 38.5 — MHz

No Feedback

t

wh — Clock Pulse Duration, High 4 — 4 — 6 — 10 — 13 — ns

t

wl — Clock Pulse Duration, Low 4 — 4 — 6 — 10 — 13 — ns

t

en B Input or I/O to Output Enabled 3 8 3 10 3 15 3 20 3 25 ns

t

dis C Input or I/O to Output Disabled 3 8 3 9 3 15 3 20 3 25 ns

t

ar A Input or I/O to Asynch. Reset of Reg. 3 13 3 13 3 20 3 25 3 25 ns

t

arw — Asynch. Reset Pulse Duration 8 — 8 — 15 — 20 — 25 — ns

t

UNITS

2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.

CAPACITANCE (T

_A

= 25

°

C, f = 1.0 MHz)

PARAM. TEST

COND.1 DESCRIPTION

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Specifications

GAL22V10

SWITCHING WAVEFORMS

Input or I/O to Output Enable/Disable

Registered Output Combinatorial Output VALID INPUT INPUT or I/O FEEDBACK

t

pd COMBINATORIAL OUTPUT INPUT or I/O FEEDBACK REGISTERED OUTPUT CLK VALID INPUT

t

su

t

co

t

h (external fdbk) 1/

f

max

t

en

t

dis INPUT or I/O FEEDBACK OUTPUT CLK (w/o fdbk) tw h tw l 1 / fm a x Clock Width REGISTERED OUTPUT CLK INPUT or I/O FEEDBACK DRIVING SP

t

su

t

h

t

co

t

spr R E G I S T ER E D O U T P U T CLK

t

arw

t

ar

t

arr INPU T or

I/O F EED B ACK DRIVI NG AR

f

max with Feedback CLK

REGISTERED FEEDBACK

tcf

t

su

(13)

Specifications

GAL22V10

f

max with Internal Feedback 1/(

t

su+

t

cf) Note: fmax with external feedback is

cal-culated from measured tsu and tco.

f

max with External Feedback 1/(

t

su+

t

co)

Note: tcf is a calculated value, derived by sub-tracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combi-natorial output is equal to tcf + tpd.

f

max with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.

R E G I S T E R L O G I C A R R A Y tc o ts u C L K

fmax DESCRIPTIONS

REGISTER LOGIC ARRAY CLK tsu + th CLK REGISTER LOGIC ARRAY tcf tpd

(14)

Specifications

GAL22V10

GAL22V10D-4 Output Load Conditions (see figure below)

Test Condition R1 CL A 50Ω 50pF B Active High 50Ω 50pF Active Low 50Ω 50pF C Active High 50Ω 50pF Active Low 50Ω 50pF

Input Pulse Levels GND to 3.0V

Input Rise and D-4, C-5 1.5ns 10% – 90% Fall Times D-10/-15/-20/-25 2.0ns 10% – 90%

B & C-7/-10

B-15/-20/-25 3ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V

Output Load See Figure

3-state levels are measured 0.5V from steady-state active level.

SWITCHING TEST CONDITIONS

TEST POINT

C *L

FROM OUTPUT (O/Q) UNDER TEST

+5V

*C INCLUDES TEST FIXTURE AND PROBE CAPACITANCEL

R2

R1

Output Load Conditions (except D-4) (see figure below)

Test Condition R1 R2 CL A 300Ω 390Ω 50pF B Active High ∞ 390Ω 50pF Active Low 300Ω 390Ω 50pF C Active High ∞ 390Ω 5pF Active Low 300Ω 390Ω 5pF TEST POINT Z0 = 50Ω, CL*

FROM OUTPUT (O/Q) UNDER TEST

+1.45V

(15)

Specifications

GAL22V10

ELECTRONIC SIGNATURE

An electronic signature (ES) is provided in every GAL22V10 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the se-curity cell.

The electronic signature is an additional feature not present in other manufacturers' 22V10 devices. To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor 22V10 device type when com-piling a set of logic equations. In addition, many device program-mers have two separate selections for the device, typically a GAL22V10 and a GAL22V10-UES (UES = User Electronic Sig-nature) or GAL22V10-ES. This allows users to maintain compat-ibility with existing 22V10 designs, while still having the option to use the GAL device's extra feature.

The JEDEC map for the GAL22V10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. However, the GAL22V10 device can still be programmed with a standard 22V10 JEDEC map (5828 fuses) with any qualified device pro-grammer.

OUTPUT REGISTER PRELOAD

When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state condi-tions.

The GAL22V10 device includes circuitry that allows each regis-tered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically.

INPUT BUFFERS

GAL22V10 devices are designed with TTL level compatible in-put buffers. These buffers have a characteristically high imped-ance, and present a much lighter load to the driving logic than bi-polar TTL devices.

The input and I/O pins also have built-in active pull-ups. As a re-sult, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schemat-ics on the following page.)

Typical Input Current

SECURITY CELL

A security cell is provided in every GAL22V10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always avail-able to the user, regardless of the state of this control cell.

LATCH-UP PROTECTION

GAL22V10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any pos-sibility of SCR induced latching.

GAL devices are programmed using a Lattice Semiconductor-approved Logic Programmer, available from a number of manu-facturers (see the the GAL Development Tools section). Com-plete programming of the device takes only a few seconds.

Eras-1 . 0 2 . 0 3 . 0 4 . 0 5 . 0 - 6 0 0 - 2 0 - 4 0 0 In p u t V o lt ag e ( V o lt s) Input C u rr e nt ( u A )

DEVICE PROGRAMMING

(16)

Specifications

GAL22V10

POWER-UP RESET

(Vref Typical = 3.2V)

(Vref Typical = 3.2V) Circuitry within the GAL22V10 provides a reset signal to all

reg-isters during power-up. All internal regreg-isters will have their Q out-puts set low after a specified time (tpr, 1µs MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the

asyn-chronous nature of system power-up, some conditions must be met to guarantee a valid power-up reset of the GAL22V10. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in nor-mal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.

Vcc PIN Vcc Vref Active Pull-up Circuit ESD Protection Circuit ESD Protection Circuit Vcc PIN

INPUT/OUTPUT EQUIVALENT SCHEMATICS

Vcc (min.) tpr Internal Register Reset to Logic "0" Device Pin Reset to Logic "1" twl tsu Device Pin Reset to Logic "0" V c c C L K INTERNAL REGISTER Q - OUTPUT ACTIVE LOW OUTPUT REGISTER ACTIVE HIGH OUTPUT REGISTER Vcc PIN Vref Tri-State Control Active Pull-up Circuit PIN Feedback Data Output

(17)

Specifications

GAL22V10

GAL22V10D-4: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Delta Tpd vs # of Outputs Switching -0.3 -0.2 -0.1 0 1 2 3 4 5 6 7 8 9 1 0 Number of Outputs Switching

Delta T

pd (

ns)

RISE FALL

Delta Tco vs # of Outputs Switching -0.4 -0.3 -0.2 -0.1 0 1 2 3 4 5 6 7 8 9 1 0 Number of Outputs Switching

Delta T co ( ns) co ( ns) RISE FALL

Delta Tpd vs Output Loading

pd (

ns)

RISE FALL

Delta Tco vs Output Loading

RISE FALL Normalized Tpd vs Vcc Normalized T p d Normalized T p d RISE FALL Normalized Tco vs Vcc RISE FALL Normalized Tsu vs Vcc Supply Voltage (V) Supply Voltage (V) Supply Voltage (V) RISE FALL

Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp

125 100 75 50 25 0 -25 -55 125 100 75 50 25 0 -25 -55

Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)

125 100 75 50 25 0 -25 -55 RISE FALL RISE FALL RISE FALL 5.5 5.25 5 4.75 4.5 0.9 1.3 1.2 1.1 1 0.9 0.8 12 8 4 12 8 4 1.3 1.2 1.1 1 0.9 0.8 0.9 1 1.1 1.2 0.95 1 1.05 1.1 Normalized T c o Normalized T c o 0.9 0.95 1 1.05 1.1 Normalized T Normalized T s u 0.9 0.95 1 1.05 1.1 5.5 5.25 5 4.75 4.5 4.5 4.75 5 5.25 5.5

(18)

Specifications

GAL22V10

GAL22V10D-4: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol 0 0.2 0.4 0.6 0 5 10 15 20 25 30 35 40 Iol (mA) Vol ( V ) Voh vs Ioh 0 1 2 3 4 0 5 10 1 5 2 0 2 5 3 0 3 5 4 0 4 5 50 55 60 Ioh(mA) Voh ( V ) Voh vs Ioh 3.15 3.25 3.35 3.45 3.55 3.65 3.75 3.85 3.95 0.00 1.00 2.00 3.00 4.00 5.00 Ioh(mA) Voh ( V ) Normalized Icc vs Vcc 0.8 0.9 1 1.1 1.2 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized I c c

Normalized Icc vs Temp

0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 2 5 5 0 8 8 100 125 Temperature (deg. C) Normalized I c c

Normalized Icc vs Freq

0.95 1 1.05 1.1 1.15 1.2 1 15 25 50 75 1 00 Frequency (MHz) Normalized I c c

Input Clamp (Vik)

Vik (V)

Iik (

mA)

Delta Icc vs Vin (1 input)

6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -3 100 80 60 40 20 0 -2.5 -2 -1.5 -1 -0.5 1 Vin (V) Delta I cc ( mA)

(19)

Specifications

GAL22V10

GAL22V10D-10 AND SLOWER: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Normalized Tpd vs Vcc 0.9 0.95 1 1.05 1.1 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized T p d RISE FALL Normalized Tco vs Vcc 0.9 0.95 1 1.05 1.1 1.15 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized T c o RISE_FALL Normalized Tsu vs Vcc 0.8 0.9 1 1.1 1.2 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized T s u RISE_FALL Normalized Tpd vs Temp 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized T p d RISE FALL

Normalized Tsu vs Temp

0.75 0.85 0.95 1.05 1.15 1.25 1.35 1.45 -55 -25 0 25 50 75 100 1 25 Temperature (deg. C) Normalized T s u RISE FALL

Normalized Tco vs Temp

0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 1 25 Temperature (deg. C) Normalized T c o RISE FALL Delta Tpd vs # of Outputs Switching -1.2 -0.8 -0.4 0 1 2 3 4 5 6 7 8 9 1 0 Number of Outputs Switching

Delta T

pd (

ns)

RISE FALL

Delta Tco vs # of Outputs Switching -1.2 -0.8 -0.4 0 1 2 3 4 5 6 7 8 9 1 0 Number of Outputs Switching

Delta T

co (

ns)

RISE FALL

8 1 2 1 6 2 0 pd ( ns) RISE FALL

8 12 16 20 co ( ns) RISE FALL

(20)

Specifications

GAL22V10

GAL22V10D-10 AND SLOWER: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol 0 0.2 0.4 0.6 0 5 10 15 20 25 30 35 4 0 Iol (mA) Vol ( V ) Voh vs Ioh 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 20 40 6 0 Ioh (mA) Voh ( V ) Voh vs Ioh 2.5 3 3.5 4 4.5 0.00 1.00 2.00 3.00 4.00 5.00 Ioh (mA) Voh ( V ) Normalized Icc vs Vcc 0.8 0.9 1 1.1 1.2 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized I c c

0.75 0.85 0.95 1.05 1.15 1.25 1.35 -55 -25 0 25 50 88 100 1 25 Temperature (deg. C) Normalized I c c

Normalized Icc vs Freq

0.9 1 1.1 1.2 1.3 1.4 1 15 25 50 75 1 00 Frequency (MHz) Normalized I c c

0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 -2.5 -2 -1.5 -1 -0.5 0 Vik (V) Iik ( m A)

0 1 2 3 4 5 6 7 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Vin (V) Delta I cc ( m A)

(21)

Specifications

GAL22V10

GAL22V10C-5/-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Normalized Tpd vs Vcc Supply Voltage (V) Normalized Tpd 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 PT H->L PT L->H Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 RISE FALL Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 PT H->L PT L->H Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 PT H->L PT L->H

Temperature (deg. C) Normalized Tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 RISE FALL

Temperature (deg. C) Normalized Tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 PT H->L PT L->H Delta Tpd vs # of Outputs Switching

Number of Outputs Switching

Delta Tpd (ns) -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 1 2 3 4 5 6 7 8 9 10 RISE FALL

Delta Tco vs # of Outputs Switching

Delta Tco (ns) -1 -0.75 -0.5 -0.25 0 1 2 3 4 5 6 7 8 9 10 RISE FALL

6 8 10 12 RISE FALL

(22)

Specifications

GAL22V10

GAL22V10C-5/-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol Iol (mA) Vol (V) 0 0.5 1 1.5 2 2.5 3 0.00 20.00 40.00 60.00 80.00 100.00 Voh vs Ioh Ioh(mA) Voh (V) 0 1 2 3 4 5 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Voh vs Ioh Ioh(mA) Voh (V) 3 3.25 3.5 3.75 4 0.00 1.00 2.00 3.00 4.00 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50

Temperature (deg. C) Normalized Icc 0.8 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125

Normalized Icc vs Freq.

Frequency (MHz) Normalized Icc 0.90 1.00 1.10 1.20 1.30 0 25 50 75 100

Vin (V)

Delta Icc (mA)

0 2 4 6 8 10 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vik (V) Iik (mA) 0 10 20 30 40 50 60 70 -2.50 -2.00 -1.50 -1.00 -0.50 0.00

(23)

Specifications

GAL22V10

GAL22V10B-7/-10/-15/-25L: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Normalized Tpd vs Vcc Supply Voltage (V) Normalized Tpd 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 PT H->L PT L->H Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 RISE FALL Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 PT H->L PT L->H Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 ₁₀₀ ₁₂₅ PT H->L PT L->H

Temperature (deg. C) Normalized Tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 RISE FALL

Temperature (deg. C) Normalized Tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 ₁₀₀ ₁₂₅ PT H->L PT L->H Delta Tpd vs # of Outputs Switching

Delta Tpd (ns) -2 -1.5 -1 -0.5 0 1 2 3 4 5 6 7 8 9 10 RISE FALL

Delta Tco (ns) -2 -1.5 -1 -0.5 0 1 2 3 4 5 6 7 8 9 10 RISE FALL

6 8 10 12 RISE FALL

(24)

Specifications

GAL22V10

GAL22V10B-7/-10/-15/-25L: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol Iol (mA) Vol (V) 0 0.5 1 1.5 2 2.5 3 0.00 20.00 40.00 60.00 80.00 100.00 Voh vs Ioh Ioh(mA) Voh (V) 0 1 2 3 4 5 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Voh vs Ioh Ioh(mA) Voh (V) 3.5 3.75 4 4.25 4.5 0.00 1.00 2.00 3.00 4.00 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50

Temperature (deg. C) Normalized Icc 0.8 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125

Frequency (MHz) Normalized Icc 0.80 0.90 1.00 1.10 1.20 0 25 50 75 100

Vin (V)

Delta Icc (mA)

0 2 4 6 8 10 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vik (V) Iik (mA) 0 10 20 30 40 50 60 70 80 90 100 -2.00 -1.50 -1.00 -0.50 0.00

(25)

Specifications

GAL22V10

GAL22V10B-15/-25Q: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Normalized Tpd vs Vcc Supply Voltage (V) Normalized Tpd 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125

Temperature (deg. C) Normalized Tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125

Temperature (deg. C) Normalized Tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 Delta Tpd vs # of Outputs Switching

Delta Tpd (ns) -1 -0.75 -0.5 -0.25 0 1 2 3 4 5 6 7 8 9 10

Delta Tco (ns) -2 -1.5 -1 -0.5 0 1 2 3 4 5 6 7 8 9 10

6 8 10 12 RISE FALL

6 8 10 12 14 RISE FALL

(26)

Specifications

GAL22V10

GAL22V10B-15/-25Q: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol Iol (mA) Vol (V) 0 0.2 0.4 0.6 0.8 1 0.00 20.00 40.00 Voh vs Ioh Ioh(mA) Voh (V) 0 1 2 3 4 5 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 Voh vs Ioh Ioh(mA) Voh (V) 3 3.25 3.5 3.75 4 0.00 1.00 2.00 3.00 4.00 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50

Temperature (deg. C) Normalized Icc 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 75 100 125

Frequency (MHz) Normalized Icc 0.80 1.00 1.20 1.40 1.60 1.80 2.00 0 25 50 75 100

Vin (V)

Delta Icc (mA)

0 2 4 6 8 10 0.20 0.70 1.20 1.70 2.20 2.70 3.20 3.70

Vik (V) Iik (mA) 0 10 20 30 40 50 60 70 80 90 -2.00 -1.50 -1.00 -0.50 0.00

(27)

E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispDS, ispDS+, ispGDS, ispGDX, ispHDL, ispJTAG, ispStarter, ispSTREAM, ispTEST, ispTURBO, ispVECTOR, ispVerilog, ispVHDL, Latch-Lock, LHDL, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders.

Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296 US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US, 5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US, 5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US, 0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not represent that products described herein are free from patent infringement or from any third-party right.

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