Design for Assembly
Design for Assembly
by Tom Hausherr, CID+, CIT by Tom Hausherr, CID+, CIT
CEO, PCB Libraries, Inc. CEO, PCB Libraries, Inc.
Every PCB layout must go through the
Every PCB layout must go through the component assembly process and there are several things tcomponent assembly process and there are several things t hat a PCBhat a PCB designer can do to make t
designer can do to make the assembly process easier.he assembly process easier.
IPC Classes 1, 2 & 3 for defect reject / accept cr IPC Classes 1, 2 & 3 for defect reject / accept criteriaiteria
A PCB designer needs to design every layout to meet one of the IPC Product Classes so that the manufacturer A PCB designer needs to design every layout to meet one of the IPC Product Classes so that the manufacturer knows the category classification of the end e
knows the category classification of the end e lectronic product being designed. A PCB lectronic product being designed. A PCB designer can find these 3designer can find these 3 Product Classes in almost every IPC
Product Classes in almost every IPC standard publication.standard publication. CLASS 1
CLASS 1
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General Electronic Products General Electronic ProductsIncludes products suitable for applications where the major
Includes products suitable for applications where the major requirement is function of the completed assembly.requirement is function of the completed assembly. CLASS 2
CLASS 2
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Dedicated Service Electronic Products Dedicated Service Electronic ProductsIncludes products where continued performance and extended
Includes products where continued performance and extended life is required, and for which uninterruptedlife is required, and for which uninterrupted service is desired but not critical. Typically the e
service is desired but not critical. Typically the e nd-use environment would not cause failures.nd-use environment would not cause failures. CLASS 3
CLASS 3
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High High Performance/Harsh EnvironmPerformance/Harsh Environment Electronic ent Electronic ProductsProducts Includes products where continued high performance or perIncludes products where continued high performance or per formance-on-demand is critical, equipmentformance-on-demand is critical, equipment downtime cannot be tolerated, end-use environment may be
downtime cannot be tolerated, end-use environment may be uncommonly harsh, and the equipment mustuncommonly harsh, and the equipment must function when required, such as medical life support, military battlefield or ot
function when required, such as medical life support, military battlefield or ot her critical systems.her critical systems.
The IPC-7351B for land pattern
The IPC-7351B for land pattern standard uses a 3-Tier PCB library system for standard uses a 3-Tier PCB library system for various electronic devicevarious electronic device applications. These include Most, Nominal and Least dimensional criteria. See
applications. These include Most, Nominal and Least dimensional criteria. See Figure 1 Figure 1 for the 3-Tier footprintfor the 3-Tier footprint density levels.
density levels.
Figure 1 Figure 1
These 3-Tiers are not directly related to the three IPC Classes, but picking the most appropriate land pattern might help the manufacturer achieve a higher yield for a specific IPC Product Class. It is widely assumed that if a design needs to meetIPC Product Class 3 that a “Most – Level A” land pattern must be used. This is not true. Any of the
IPC-7351B 3-tierenvironments can be used to build a Class 3 board assembly. It’s just that a Density Level A (Most Environment) land pattern will make it easier for manufacturing to achieve a higher yield. However, an IPC -7351B Nominal Environment land pattern can be used to create a Class 3 electronic product. And the Least environment might also be used to create a Class 3 product but the manufacturing price will go up as the yield goes down.
Silkscreen under components / Useful silkscreen outlines
Silkscreen outlines add cost to PCB fabrication and in most cases is not necessary.
However, if you use silkscreen outlines, here are my guidelines for creating PCB library parts.
1. Silkscreen Outlines should never be located under t he component because they are covered up during assembly and do not provide any useful function to the assembly process
2. J-STD-001E Assembly Requirements Section 9.2 – Silkscreen Polarity Marking, Reference Designators, Revision Level and Serial Numbers Shall be visible after assembly as shown in Figure 2
3. Silkscreen outlines should be mapped to the m aximum component body outline
4. Your company’s “Pad to Silkscreen” drafting rule should override maximum component body mapping 5. Silkscreen outlines are used for assembly placement registration accuracy and post assembly inspection 6. The silkscreen line width and pad to line gap are normally the same value
7. Silkscreen outlines should always be located inside the Placement C ourtyard. Otherwise the silkscreen outlines can get confused with other components or overlap with other silkscreen outlines.
8. Only one line width should be used throughout the entire P CB library
Silkscreen to pad clearance & Silkscreen on pads
IPC-7351C (to be released) will introduce guidelines for 3-Tier silkscreen lines widths as shown inFigure 3. Some PCB designers allow silkscreen on pads and they ex pect the fabrication shop to trim the silkscreen away from the
pad. But what if the fabrication shop doesn’t do that? Silkscreen ink on a solder pad becomes a solderability issue. The assembly shop will be scrapping the silkscreen ink off the pads prior to applying the solder paste via stencil if fabrication shop does not. But assembly will be dealing with soldering issues from the pad contamination!
Figure 3
Polarity Marking & Sometimes No Marking is Polarity
Components that can be inverted (like Resistors) during assembly do have polarity marking. All parts that have to be inserted in a particular rotation re quire a silkscreen marker to indicate polarity or Pin 1 . My recommendation for silkscreen polarity is to extend the silkscreen line the full length of the Pin 1 pad as shown inFigure 4.
For bottom-termination components, the placement courtyard hugs the package body or the pads. In this case,
the “absence of silkscreen” is the best polarity marker as shown in Figure 5 for a QFN package.
Figure 5
Assembly Outlines and Polarity Marking
The assembly drawing component outlines should be a simple closed polygon and the polarity marker should be a simple chamfer to locate Pin 1 as shown inFigure 6.
Courtyard Excess
Courtyard Excess as shown inFigure 7 is used as a guideline for part placement. Every assembly shop has their unique tolerances and if the guidelines place the components too close the assembly shop has a manufacturing allowance which will be the necessary gap betwee n courtyards.
Figure 7
If the assembly shop does not require a “manufacturing allowance” the PCB designer can place the courtyards so
they touch, but not overlap as shown in Figure 8. Crowding & overlapping courtyards can lead to solder bridging during assembly.
Figure 8
Part Placement & Alignment
In the 1980’s assembly shops preferred all polarized parts should be pointed in the same direction. With today’s
technology that is no longer necessary however, aligning parts in nice neat rows will add aesthetic v alue to the
final PC board. And if you’re selling boards on the open market, consumers will naturally choose the pretty board. Also, nicely ordered parts are better for signal routing and use of space.
Footprint Origins
Components come packaged in Tape & Reel, Tubes & Trays. The pick & place machines pick up the component at the center of gravity. When PCB designers put the origin of the PCB library part in the center, they are aiding the assembly shop. However, some component packages have irregular shapes and the center is difficult to
and making Pin 1 the origin optimizes signal routing. A c entric origin marker helps the PCB designer identify the location of the footprint origin. However, some CAD tools auto-generate an origin marker in the software and in that case there is no need to add an additional origin marker in the PCB library part.
Figure 9
Assembly Rails or Frames
The assembly shop needs the board edge to clamp onto while the board travels through the pick & place
machines and the solder reflow oven. If the PCB designer places components close to the board edge due to high density part placement, then a breakaway panel must be added to aid the assembly line. The breakaway tab could also contain the Global Fiducials and Tooling Holes as shown in Figure 10.
When the board is completely assembled the breakaway t abs must be removed. There are two methods o f separating the breakaway tabs. The first and most popular m ethod is Routing and Mouse Bites as shown in Figure 11. The trace routing must be at least 1 mm away from the finished board edge and the mouse bites. And
components should be located at least 2 mm away from the Routed Edge and Mouse Bite holes as shown in Figure 12.
Figure 11
Figure 12
Figure 13
Some PCB designers like to insure that the breakaway tabs are secure and won’t breakaway during handling. In this case the PCB designer will add a frame around the entire PCB design and use mouse bites and routing channels. Adding a frame reduces the number of boards you can get on a panel but it does add rigidity to the individual board to insure the breakaway tabs do not prematurely break away during assembly handling.
Global and Local Fiducials
Global Fiducials are a must for the Pick & Place machine to optically bombsite the fiducial locations to register the board for machine placement accuracy as shown in Figure 14.
Local Fiducials are used for Fine Pitc h QFP components when the pin pitch is less than 0.625 mm and BGA components when the pin pitch is less than 0.8 mm and shown inFigure 15.With today’s modern equipment,
many assembly shops do not require local fiducials however; they might come in handy for repair/replacement.
Figure 15
Surface Mount Solder Joints
These 7 factors are used to calculate the optimum Land Size per IPC-7351 1. Component Body Tolerance
2. Component Terminal Tolerance
3. Fabrication Tolerance – ± 2 Mil (0.05 mm) 4. Placement Tolerance – ± 1 Mil (0.025 mm) 5. Land Size Round-off
6. Land Spacing Round-off
7. Solder Joint Goals for Toe, Heel and Side – SeeFigure 16
Gull Wing Lead Pitch > 0.625 Least Level C Nominal Level B Most Level A Toe 0.15 0.35 0.55 Heel 0.25 0.35 0.45 Side 0.01 0.03 0.05
Round-off Factor Round-off to the Nearest 0.01 or 0.05 Courtyard Excess 0.10 0.25 0.50
Figure 16
The heel fillet in a gull-wing lead component is very important. Lots of reliability studies establish that 60-80% of gull-wing solder strength is in the heel. L and position or length that precludes forming the minimum heel fillet is a failure mechanism.
Plated Through-hole (PTH) Hole and Pad Size Calculations
Before you calculate the pad size, you must first calculate the hole-size perFigure 17.
Figure 17
Once you figure out the hole-size, the annular ring can be calculated by adding a m inimum annular ring value of 2 mil (0.05 mm) plus a minimum fabrication allowance of 16 mil (0.4 mm) to t he hole-size. The nominal fabrication allowance is 20 mil (0.5 mm) and the maximum fabrication allowance is 24 mil (0.6 mm).
You can also use the PCB Libraries, Inc. Proportional Padstack Chart to auto-generate a good known annular ring. The Proportional Padstack starts out using the least annular ring for small holes and nominal annular ring for average hole sizes and most annular ring for large hole sizes. Download the Proportional Padstack Chart and many other important library construction documents here -
Manufacturer Recommended Footprint Patterns
IPC-7351B has standard mathematical formulas for calculating “Standard Component Families”. Over 50% of all component packages in the electronics industry today are “Non-standard Packages”. These non-standard packages require the component manufacturer to provide a recommended footprint pattern. Typically the component manufacturer will create test patterns and run them through the assembly process to se lect which pattern has the best solder joints.
Minimum Pad to Pad Clearance
The minimum pad to pad clearance is defined by the assembly shop. Before you create your PCB library parts, discuss this issue with your assembly shop engineer. The IPC-7351 c alculator default minimum pad to pad clearance is set to 6 mil (0.15 mm) but some assembly shops require 8 mil (0.2 mm) pad to pad clearance to optimize their assembly process and reduce scrap and increase yield.
Pad Trimming Under Components
Pad trimming is used exclusively for Gull Wing component leads for low profile component packages that have no space under the component (between the PCB and the component bottom). However, IPC says that regardless of the component stand-off value, a PCB designer should not trim the pads under low profile components. See Figure 18.
Figure 18
Zero Component Orientation
Zero component orientation indicates the location of pin 1 and the rotation the PCB library was built to. This is important for automating the pick & place assembly line. When an assembly shop starts a project, they have to insure the rotation of every part o n the PCB layout to insure that every component is attached with the cor rect rotation. This currently is a manual time consuming process. IPC-7351C will introduce two acceptable rotations, seeFigure 19 Part 1. Level A is pin 1 in the upper left corner and Level B is pin 1 in the lower left corner. If a PCB designer creates the entire PCB library with a known rotation, they can indicate that in the assembly drawing to provide the assembly shop with a known starting point. When every PC B designer in the electronics industry organizes their entire PCB library using either Level A or Level B (not both) then the assembly shop can start the process of automation however, the assembly shops will continue to ver ify zero component orientations until they have consistency in the X/Y pick & place data.
Figure 19 Part 1
Figure 19 Part 2 illustrates IPC-7351C Level B zero component orientation rotated counterclockwise by 90°.
X / Y Coordinate File
The PCB designer creates a pick & place file normally in M/S Excel format. The spreadsheet contains the reference designator of every component in the PCB layout and its associated X & Y location from the PC Board Origin and the rotation of each component per the Zero Component Orientation of the PCB library pa rt. If the PCB designer does not provide an X/Y coordinate file, the assembly shop will take hours to calculate the center of each
component to program the pick & place assembly line.
Thermal Pad Paste Mask Reduction
These component families have Thermal Tabs – QFN, PQFN, SON, PSON, SOP and QFP
The paste mask stencil must be reduced by a value between 40 – 65% and evenly dispersed in a checker board pattern so when the PCB goes through the reflow oven, the thermal pad paste mask spreads out evenly. See Figure 20 for an example of a QFN with a thermal pad and its associated paste mask stencil reduced by 50%.
Figure 20
Rounded Rectangle Pad Shape
Surface mount pad shapes have been at the center of controversy since the 1980’s. IPC has always recommended
either a full radius or corner radius pad shape while the component manufacturers recommend a rectangular pad shape. The goal is to aid the assembly process t o make it more efficient. The number one issue with the industry not adopting the Rounded Rectangle Pad S hape is that many CAD tools did not support it until re cently. In my opinion, the rounded rectangle pad shape should be used for every surface mount component package. It is the universal pad shape that improves fabrication and assembly and meets IPC standards. The only goal now is to get the component manufacturers to adopt it in their datasheet drawings. SeeFigure 21 for the optimal sizing.
If you look at an assembled PC board you will notice that most of the solder pulls away from the corners of the pad (land). SeeFigure 22. The rounded rectangle pad shape also opens up additional routing channels for dense layouts.
Via-in-pad Technology
Via-in-pad technology is just starting to take off because of new component packages like Land G rid Array (LGA) where there is no room for a typical dog bone via fanout. SeeFigure 23.
Also, finepitch BGA’s need to use the via-in-pad technique and sometimes not locating the via in the center of the pad is necessary to open routing channels on inner layers. SeeFigure 24 for an example of a routing solution for a 0.6 mm pitch BGA.
Figure 24
The main assembly problem with using via-in-pad technology is the fabrication process must insure that the via is plated,plugged, capped and surface finish with a flat surface. It’s the “Flat Surface” that is the most important
issue. If there is a slight dimple in the pad, the paste mask will trap air that will get super heated in the reflow oven and blow a hole into the component lead and create a void. See Figure 25 for an example of a BGA void.
Non-Solder Mask Defined Pads
Either the PCB designer or the fabrication shop must swell the solder mask to preve nt solder mask from
encroaching on the solder pad (land). Depending on the solder mask fabrication process, there is a manufacturing tolerance. If you are using multiple fabrication facilities, it is best not to swell the solder mask in the PCB library or in the Gerber data that is provided to fabrication. Let the fabrication shop swell the solder mask to a value that is compatible with their solder mask registration tolerances to insure that no solder mask will end up on an exposed pad.Most BGA’s have collapsing balls that needs to collapse around the edge of the pad. If the solder mask is not swelled, the BGA ball cannot collapse around the pad edge and this will compromise the BGA solder joint
connection. InFigure 26, the image on the left is a non-solder mask swell and no Ball collapse around the pad. The image on the right has a solder mask swell and the BGA ball collapsed around the pad.
Figure 26
Note: J-STD-001E and IPC-A-610E have looser criter ia for solder mask than bare board fabrication. Solder mask has a purpose during assembly – keep solder from wetting in specific areas. But during the assembly process high
temp cycles and mechanical actions may degrade the mask material. At that point it probably doesn’t matter.
However, it would become an issue if the solder mask darkened so much that silkscreen markings required to be discernible were not.
Solder Mask Defined Pads
Solder mask defined pads are only used in two applications that I know of. When designing library parts for
Flexible Circuits it is best to solder mask define the Toe and the Heel to assist in holding the pad down to the PCB during flexing.
The other reason is solder mask defining BGA pads in hand held devices such as cell phones. The BGA pin pitch in an average cell phone is 0.4mm or less and the ball and pad sizes are very small. During drop testing, it has been proven that the BGA solder joint holds up better than the pad to pre greg adhesion. The pad will break away from the PCB before the ball breaks away from the pad. So solder mask defining BGAvery fine pitch BGA’s helps to hold the pad to the PCB which decreases failure in dropping the device. SeeFigure 27.
Figure 27
Paste Mask Stencil for Micro-miniature Components
The average paste mask stencil thickness is 0.125 - 0.15 mm (5 – 6 mils) thick. The stencil manufacturer must thin out the stencil areas around all chip components less than 0402.Figure 28 is an example of a real 1:1 scale 0201 chip resistor that has a 0.033 mm thickness and placed on 0.15 mm paste mask. You can easily see that the solder volume is way too much for this miniature component. So t he paste mask stencil must be thinned out to reduce the solder volume.
Mounting Hardware
Every PCB layout has mounting holes to attach the PCB to an enclosure. It is important for the PCB Designer to add keep-outs to allow for the hardware manufacturing to lerance to prevent short circuiting the hardware t o a trace, via, copper pour or component pad. SeeFigure 29.
Figure 29
For non-plated (unsupported) mounting holes I highly recommend a pad so t hat the metal hardware (screw head, washer or nut) contact a pad rather than the bare board. For m any years I created unsupported mounting holes with no pad annular ring, but I never saw the damage that metal hardware does whe n it comes in contact with the bare board FR4 material. The solder mask and woven glass get roughed up when torque is applied to tighten the screw and when too much torque is applied, the FR4 material cr ushes. I also recommend that the pad be constructed using a Donut Pad with the inside diameter of the pad to be pulled away from the hole by 5 mil (0.12 mm) so that the drill bit goes straight through FR4 material and does not hit any me tal. See Figure 30 for non-plated mounting-hole construction.
Figure 30
Written By: Tom Hausherr CID+, CIT Founder & CEO of PCB Libraries, Inc. [email protected] www.PCBLibraries.com
