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WWW.TESTBENCH.IN

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SystemVerilog Verilog OpenVera Miscellanious

Basic Constructs Interface OOPS Randomization Functional Coverage Assertion DPI VMM Ethernet Example ... Verification Concepts UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM Easy Labs : AVM

Verification Concepts Switch Example Basic Constructs ... ... ... ... ... ... Constructs Switch Example RVM Switch Example RVM Ethernet Sample ... ... ... ... ... Articles Specman E Tutorial Interview Questions ... ... ... ... ... ...

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>Table of Contents

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WWW.TESTBENCH.IN - SystemVerilog Constructs http://testbench.in/SV_00_INDEX.html[9/26/2012 1:55:53 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ...DATA TYPES

... Signed And Unsigned

... Void

...LITERALS

... Integer And Logic Literals

... Time Literals

... Array Literals

... Structure Literals

...STRINGS

... String Methods

... String Pattren Match

... String Operators ... Equality ... Inequality. ... Comparison. ... Concatenation. ... Replication. ... Indexing. ...USERDEFINED DATATYPES ...ENUMARATIONS ... Enumarated Methods

... Enum Numerical Expressions

...STRUCTURES AND UNIOUNS ... Structure

... Assignments To Struct Members

... Union

... Packed Structures

...TYPEDEF

... Advantages Of Using Typedef

...ARRAYS

... Fixed Arrays

... Operations On Arrays

... Accessing Individual Elements Of Multidimensional Arrays

...ARRAY METHODS ... Array Methods

... Array Querying Functions

... Array Locator Methods

... Array Ordering Methods

... Array Reduction Methods

... Iterator Index Querying

...DYNAMIC ARRAYS

... Declaration Of Dynmic Array

... Allocating Elements

... Initializing Dynamic Arrays

... Resizing Dynamic Arrays

Index Introduction Data Types Literals Strings Userdefined Datatypes Enumarations

Structures And Uniouns Typedef Arrays Array Methods Dynamic Arrays Associative Arrays Queues Comparison Of Arrays Linked List Casting Data Declaration Reg And Logic Operators 1 Operators 2 Operator Precedency Events Control Statements Program Block Procedural Blocks Fork Join Fork Control Subroutines Semaphore Mailbox

Fine Grain Process Control

Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

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WWW.TESTBENCH.IN - SystemVerilog Constructs

http://testbench.in/SV_00_INDEX.html[9/26/2012 1:55:53 PM]

... Copying Elements

...ASSOCIATIVE ARRAYS

... Associative Array Methods

...QUEUES

... Queue Operators

... Queue Methods

... Dynamic Array Of Queues Queues Of Queues

...COMPARISON OF ARRAYS ... Static Array ... Associative Array ... Dynamic Array ... Queues ...LINKED LIST ... List Definitions

... Procedure To Create And Use List

... List_iterator Methods ... List Methods ...CASTING ... Static Casting ... Dynamic Casting ... Cast Errors ...DATA DECLARATION ... Scope And Lifetime

... Global

... Local

... Alias

... Data Types On Ports

... Parameterized Data Types

... Declaration And Initialization

...REG AND LOGIC ...OPERATORS 1 ... Operators In Systemverilog ... Assignment Operators ... Assignments In Expression ... Concatenation ... Arithmetic ... Relational ... Equality ...OPERATORS 2 ... Logical ... Bitwise ... Reduction ... Shift

... Increment And Decrement

... Set

... Streaming Operator

... Re-Ordering Of The Generic Stream

... Packing Using Streaming Operator

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WWW.TESTBENCH.IN - SystemVerilog Constructs

http://testbench.in/SV_00_INDEX.html[9/26/2012 1:55:53 PM]

... Streaming Dynamically Sized Data

...OPERATOR PRECEDENCY ...EVENTS

... Triggered

... Wait()

... Race Condition

... Nonblocking Event Trigger

... Merging Events ... Null Events ... Wait Sequence ... Events Comparison ...CONTROL STATEMENTS ... Sequential Control

... Enhanced For Loop

... Unique ... Priority ...PROGRAM BLOCK ...PROCEDURAL BLOCKS ... Final ... Jump Statements ... Event Control ... Always ...FORK JOIN

... Fork Join None

... Fork Join Any

... For Join All

...FORK CONTROL

... Wait Fork Statement

... Disable Fork Statement

...SUBROUTINES ... Begin End

... Tasks

... Return In Tasks

... Functions

... Return Values And Void Functions:

... Pass By Reference

... Default Values To Arguments

... Argument Binding By Name

... Optional Argument List

...SEMAPHORE ...MAILBOX

...FINE GRAIN PROCESS CONTROL

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WWW.TESTBENCH.IN - Systemverilog Interface http://testbench.in/IF_00_INDEX.html[9/26/2012 1:56:01 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTERFACE

... Advantages Of Using Inteface

...PORTS

... Interface Ports

... Modports

... Modport Selection Duing Module Definition.

... Modport Selection Duing Module Instance.

...INTERFACE METHODS ... Methods In Interfaces ...CLOCKING BLOCK ... Clocking Blocks ... Skew ... Cycle Delay ...VIRTUAL INTERFACE ... Virtual Interfaces

... Advantages Of Virtual Interface

... Multi Bus Interface

...SVTB N VERILOG DUT

... Working With Verilog Dut

... Connecting In Top

... Connecting Using A Wrapper

Index Interface Ports Interface Methods Clocking Block Virtual Interface Svtb N Verilog Dut Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

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WWW.TESTBENCH.IN - Systemverilog Interface

http://testbench.in/IF_00_INDEX.html[9/26/2012 1:56:01 PM]

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WWW.TESTBENCH.IN - Systemverilog OOPS http://testbench.in/CL_00_INDEX.html[9/26/2012 1:56:09 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION

... Brief Introduction To Oop

... Class ... Object ... Methods ... Inheritance ... Abstraction ... Encapsulation ... Polymorphism ...CLASS ... Class Properties ...OBJECT ... Creating Objects ... Declaration ... Instantiating A Class ... Initializing An Object ... Constructor ...THIS

... Using The This Keyword

...INHERITANCE

... What You Can Do In A Subclass

... Overriding ... Super ... Is Only Method ... Is First Method ... Is Also Method ... Overriding Constraints. ... Overriding Datamembers ...ENCAPSULATION ... Access Specifiers ...POLYMORPHISM ...ABSTRACT CLASSES ...PARAMETERISED CLASS

... Type Parameterised Class

... Value Parameterised Class

... Generic Parameterised Class

... Extending Parameterised Class

...NESTED CLASSES

... Why Use Nested Classes

...CONSTANT

... Constant Class

... Global Constant

... Instance Constants

...STATIC

... Static Class Properties

Index Introduction Class Object This Inheritance Encapsulation Polymorphism Abstract Classes Parameterised Class Nested Classes Constant Static Casting Copy Scope Resolution Operator Null External Declaration Classes And Structures Typedef Class

Pure

Other Oops Features Misc

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WWW.TESTBENCH.IN - Systemverilog OOPS

http://testbench.in/CL_00_INDEX.html[9/26/2012 1:56:09 PM]

... Static Methods

... Static Lifetime Method.

...CASTING ...COPY

... Shallow Copy

... Deep Copy

... Clone

...SCOPE RESOLUTION OPERATOR ...NULL

...EXTERNAL DECLARATION ...CLASSES AND STRUCTURES ...TYPEDEF CLASS

... Forward Reference

... Circular Dependency

...PURE

...OTHER OOPS FEATURES ... Multiple Inheritence

... Method Overloading

...MISC

... Always Block In Classes

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WWW.TESTBENCH.IN - Systemverilog Randomization http://testbench.in/CR_00_INDEX.html[9/26/2012 1:56:18 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...CONSTRAINED RANDOM VERIFICATION ... Introduction

...VERILOG CRV

... Constrained Random Stimulus Generation In Verilog

...SYSTEMVERILOG CRV

... Systemverilog Constraint Random Stmulus Generaion

... Random Number Generator System Functions

... $Urandom_range

... Scope Randomize Function

... Randomizing Objects

... Random Unpacked Structs

... Rand Case

... Rand Sequence

...RANDOMIZING OBJECTS

... Generating Random Stimulus Within Class

...RANDOM VARIABLES

... Random Varible Declaration

... Rand Modifier

... Randc Modifier

...RANDOMIZATION METHODS

... Randomization Built-In Methods

... Randomize()

... Pre_randomize And Post_randomize

... Disabling Random Variable

... Random Static Variable

... Randomizing Nonrand Varible

...CHECKER ...CONSTRAINT BLOCK ... Inheritance ... Overrighting Constraints ...INLINE CONSTRAINT ...GLOBAL CONSTRAINT ...CONSTRAINT MODE

... Disabling Constraint Block

...EXTERNAL CONSTRAINTS ... Constraint Hiding ...RANDOMIZATION CONTROLABILITY ... Controlability ...STATIC CONSTRAINT ...CONSTRAINT EXPRESSION ... Set Membership ... Weighted Distribution Index Constrained Random Verification Verilog Crv Systemverilog Crv Randomizing Objects Random Variables Randomization Methods Checker Constraint Block Inline Constraint Global Constraint Constraint Mode External Constraints Randomization Controlability Static Constraint Constraint Expression Variable Ordering Constraint Solver Speed Randcase Randsequence Random Stability Array Randomization Constraint Guards Titbits

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WWW.TESTBENCH.IN - Systemverilog Randomization http://testbench.in/CR_00_INDEX.html[9/26/2012 1:56:18 PM] ... Implication ... If..Else ...VARIABLE ORDERING ... Functions ... Iterative Constraints

...CONSTRAINT SOLVER SPEED ...RANDCASE

...RANDSEQUENCE

... Random Productions

... Random Production Weights

... If..Else

... Case

... Repeat Production Statements

... Rand Join

... Break

... Return

... Value Passing Between Productions

...RANDOM STABILITY ... Srandom

...ARRAY RANDOMIZATION ...CONSTRAINT GUARDS ...TITBITS

... Constraining Non Integral Data Types

... Saving Memory

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WWW.TESTBENCH.IN - SystemVerilog Functional Coverage http://testbench.in/CO_00_INDEX.html[9/26/2012 1:56:27 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION

... Systemverilog Functional Coverage Features

...COVER GROUP ...SAMPLE ...COVER POINTS

... Commands To Simulate And Get The Coverage Report

...COVERPOINT EXPRESSION ... Coverpoint Expression

... Coverage Filter

...GENERIC COVERAGE GROUPS ...COVERAGE BINS

... Implicit Bins

...EXPLICIT BIN CREATION ... Array Of Bins

... Default Bin

...TRANSITION BINS

... Single Value Transition

... Sequence Of Transitions

... Set Of Transitions

... Consecutive Repetitions

... Range Of Repetition

... Goto Repetition

... Non Consecutive Repetition

...WILDCARD BINS ...IGNORE BINS ...ILLEGAL BINS ...CROSS COVERAGE

... User-Defined Cross Bins

...COVERAGE OPTIONS ... Weight ... Goal ... Name ... Comment ... At_least ... Detect_overlap ... Auto_bin_max ... Cross_num_print_missing ... Per_instance ... Get_inst_coverage ...COVERAGE METHODS ...SYSTEM TASKS Index Introduction Cover Group Sample Cover Points Coverpoint Expression Generic Coverage Groups Coverage Bins

Explicit Bin Creation Transition Bins Wildcard Bins Ignore Bins Illegal Bins Cross Coverage Coverage Options Coverage Methods System Tasks Cover Property

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WWW.TESTBENCH.IN - SystemVerilog Functional Coverage

http://testbench.in/CO_00_INDEX.html[9/26/2012 1:56:27 PM]

...COVER PROPERTY

... Cover Property Results

... Cover Sequence Results

... Comparison Of Cover Property And Cover Group.

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WWW.TESTBENCH.IN - System Verilog Assertion - SVA http://testbench.in/AS_00_INDEX.html[9/26/2012 1:56:34 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ... Advantages Of Assertion

... What Assertions Can Verify

...EVENT SIMULATION ...ASSERTION TYPES ...ASSERTION SYSTEM TASKS

... Assertion Control System Tasks

... Boolean System Function

...CONCURRENT ASSERTION LAYERS ... Boolean Expressions

...SEQUENCES

... Fixed Delay

... Zero Delay

... Constant Range Delay

... Unbounded Delay Range

... Repetation Operators ... Consecutive Repetition ... Goto Repetition ... Nonconsecutive Repetition ... Sequence And ... Sequence Or ... Sequence Intersect ... Sequence Within ... Sequence First_match ... Sequence Throughout ... Sequence Ended

... Operator Precedence Associativy

...PROPERTIES

... Overlap Implication

... Non Overlapping Implication

...VERIFICATION DIRECTIVE ... Assert ... Assume ... Cover Statement ... Expect Statement ... Binding Index Introduction Event Simulation Assertion Types Assertion System Tasks Concurrent Assertion Layers

Sequences Properties

Verification Directive Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

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WWW.TESTBENCH.IN - System Verilog Assertion - SVA

http://testbench.in/AS_00_INDEX.html[9/26/2012 1:56:34 PM]

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WWW.TESTBENCH.IN - Systemverilog DPI http://testbench.in/DP_00_INDEX.html[9/26/2012 1:56:42 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTIONS ... What Is Dpi-C ? ...LAYERS

... Two Layers Of Dpi-C

... Dpi-C Systemverilog Layer

... Dpi-C Foreign Language Layer

...IMPORT

... Import Methods

... Steps To Write Import Metyhods

... Standard C Functions

...NAMING

... Global Name

... Local Name

... Sv Keyword As Linkage Name

...EXPORT

... Export Methods

... Steps To Write Export Methods

... Blocking Export Dpi Task

...PURE AND CONTEXT ... Pure Function

... Context Function

...DATA TYPES

... Passing Logic Datatype

...ARRAYS

... Open Arrays

... Packed Arrays

... Linearized And Normalized

... Array Querying Functions

...PASSING STRUCTS AND UNIONS ... Passing Structure Example

... Passing Openarray Structs

... Passing Union Example

...ARGUMENTS TYPE

... What You Specify Is What You Get

... Pass By Ref

... Pass By Value

... Passing String

... Example Passing String From Sv To C

... Example Passing String From C To Sv

...DISABLIE

... Disable Dpi-C Tasks And Functions

... Include Files Index Introductions Layers Import Naming Export

Pure And Context Data Types Arrays

Passing Structs And Unions

Arguments Type Disablie

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WWW.TESTBENCH.IN - Systemverilog DPI

http://testbench.in/DP_00_INDEX.html[9/26/2012 1:56:42 PM]

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WWW.TESTBENCH.IN http://testbench.in/ethernet_vmm.html[9/26/2012 1:56:49 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

VMM Ethernet

This testbench is developed in VMM (Systemverilog) for the Ethernet core available from opencores.org. My intension here is to explore the VMM methodology but not to verify the Ethernet core, as a result there are many bugs in the environment. I dont remember the versions of VMM but I developed these in the third quarter of 2007. To simulate this testbench some dependencies on libraries has to be removed from RTL files. It takes bit time for these changes in RTL.

Feauters:

Full support of automatic random, constrained random, and directed testcase creation. Supports injuction of random errored packets.

Supports 1G Fullduplex modeled both in RX and TX paths. Protocol Checker/Monitor for self checking.

Built in function coverage support for packets.

Developed in Systemverilog using Synopsys VMM base classes. NOTE: All trademarks are the property of their respective owners. Download vmm.tar

Browse the code in vmm_eth.tar

BLOCK DIAGRAM OF ETHERNET VERIFICATION ENVIRONMENT

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WWW.TESTBENCH.IN

http://testbench.in/ethernet_vmm.html[9/26/2012 1:56:49 PM]

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WWW.TESTBENCH.IN - Systemverilog for Verification http://testbench.in/TS_00_INDEX.html[9/26/2012 1:56:57 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...ASIC DESIGN ... Mrd ... Architecture Specification ... Design Specification ... Verification Plan ... Rtl Design ... Functional Verification ... Synthesis ... Physical Design ... Timing Analysis ... Tapeout

...BOTTLE NECK IN ASIC FLOW ...FUNCTIONAL VERIFICATION NEED ...TESTBENCH

...LINEAR TESTBENCH

...LINEAR RANDOM TESTBENCH ...HOW TO CHECK THE RESULTS ...SELF CHECKING TESTBENCHS

...HOW TO GET SCENARIOS WHICH WE NEVER THOUGHT

...HOW TO CHECK WHETHER THE TESTBENCH HAS SATISFACTORILY EXERCISED THE DESIGN

...TYPES OF CODE COVERAGE ...STATEMENT COVERAGE ...BLOCK COVERAGE ...CONDITIONAL COVERAGE ...BRANCH COVERAGE ...PATH COVERAGE ...TOGGLE COVERAGE ...FSM COVERAGE ... State Coverage ... Transition Coverage

...MAKE YOUR GOAL 100 PERCENT CODE COVERAGE NOTHING LESS ... Dont Be Fooled By The Code Coverage Report

... When To Stop Testing?

...FUNCTIONAL COVERAGE

... Introduction To Functional Coverage

... Item

Index Asic Design

Bottle Neck In Asic Flow Functional Verification Need Testbench Linear Testbench Linear Random Testbench

How To Check The Results

Self Checking Testbenchs How To Get Scenarios Which We Never Thought How To Check Whether The Testbench Has Satisfactorily Exercised The Design

Types Of Code Coverage Statement Coverage Block Coverage Conditional Coverage Branch Coverage Path Coverage Toggle Coverage Fsm Coverage Make Your Goal 100 Percent Code Coverage Nothing Less Functional Coverage Coverage Driven Constraint Random Verification Architecture Phases Of Verification Ones Counter Example Verification Plan

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WWW.TESTBENCH.IN - Systemverilog for Verification

http://testbench.in/TS_00_INDEX.html[9/26/2012 1:56:57 PM]

... Cross

... Transitional

... Assertion Coverage

...COVERAGE DRIVEN CONSTRAINT RANDOM VERIFICATION ARCHITECTURE ... Verification Components Required For Cdcrv

... Stimulus

... Stimulus Generator

... Transactor

... Driver

... Monitor

... Assertion Based Monitor

... Data Checker ... Scoreboard ... Coverage ... Utilities ... Environment ... Tests ...PHASES OF VERIFICATION ... Verification Plan ... Building Testbench ... Writing Tests

... Integrating Code Coverage

... Analyze Coverage

...ONES COUNTER EXAMPLE ... Specification

... Test Plan

... Block Diagram

... Verification Environment Hierarchy

... Testbench Components ... Stimulus ... Driver ... Monitor ... Assertion Coverage ... Scoreboard ... Environment ... Top ... Tests ...VERIFICATION PLAN

... Verification Plan Contains The Following

... Overview

... Feature Extraction

... Resources, Budget And Schedule

... Verification Environment

... System Verilog Verification Flow

... Stimulus Generation Plan

... Checker Plan

... Coverage Plan

... Details Of Reusable Components

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WWW.TESTBENCH.IN - Systemverilog for Verification

http://testbench.in/TS_00_INDEX.html[9/26/2012 1:56:57 PM]

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WWW.TESTBENCH.IN - UVM Tutorial http://testbench.in/UT_00_INDEX.html[9/26/2012 1:57:04 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION

... Installing Uvm Library

...UVM TESTBENCH ... Uvm_env

... Verification Components

... About Uvm_component Class

... Uvm_test ... Top Module ...UVM REPORTING ... Reporting Methods ... Actions ... Configuration ...UVM TRANSACTION ... Core Utilities

... User Defined Implementations

... Shorthand Macros

...UVM CONFIGURATION ... Set_config_* Methods

... Automatic Configuration

... Manual Configurations

... Configuration Setting Members

...UVM FACTORY ... Registration ... Construction ... Overriding ...UVM SEQUENCE 1 ... Introduction

... Sequence And Driver Communication

... Simple Example

... Sequence Item

... Sequence

... Sequencer

... Driver

... Driver And Sequencer Connectivity

... Testcase

...UVM SEQUENCE 2

... Pre Defined Sequences

... Sequence Action Macro

... Example Of Pre_do,Mid_do And Post_do

... List Of Sequence Action Macros

... Examples With Sequence Action Macros

...UVM SEQUENCE 3 ... Body Callbacks ... Hierarchical Sequences ... Sequential Sequences ... Parallel Sequences ...UVM SEQUENCE 4 Index Introduction Uvm Testbench Uvm Reporting Uvm Transaction Uvm Configuration Uvm Factory Uvm Sequence 1 Uvm Sequence 2 Uvm Sequence 3 Uvm Sequence 4 Uvm Sequence 5 Uvm Sequence 6 Uvm Tlm 1 Uvm Tlm 2 Uvm Callback

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WWW.TESTBENCH.IN - UVM Tutorial

http://testbench.in/UT_00_INDEX.html[9/26/2012 1:57:04 PM]

... Sequencer Arbitration

... Setting The Sequence Priority

...UVM SEQUENCE 5

... Sequencer Registration Macros

... Setting Sequence Members

...UVM SEQUENCE 6 ... Exclusive Access

... Lock-Unlock

... Grab-Ungrab

...UVM TLM 1

... Port Based Data Transfer

... Task Based Data Transfer

... Operation Supported By Tlm Interface

... Methods

... Tlm Terminology

... Tlm Interface Compilation Models

... Interfaces

... Direction

... All Interfaces In Uvm

...UVM TLM 2 ... Analysis

... Tlm Fifo

... Example

...UVM CALLBACK

... Driver And Driver Callback Class Source Code

... Testcase Source Code

... Testcase 2 Source Code

... Methods

... Macros

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WWW.TESTBENCH.IN - VMM Tutorial http://testbench.in/VM_00_INDEX.html[9/26/2012 1:57:13 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ...VMM LOG ... Vmm Message Type ... Message Severity ... Vmm Log Macros ... Message Handling

... Counting Number Of Messages Based Of Message Severity

...VMM ENV ...VMM DATA

... Complete Packet Class

... Vmm_data Methods ...VMM CHANNEL ... Complete Example ... Vmm Channel Methods. ...VMM ATOMIC GENERATOR ... Completed Example ...VMM XACTOR

... Complete Vmm_xactor Example

... Vmm_xactor Members

...VMM CALLBACK

... Complete Source Code

...VMM TEST

... Writing A Testcase

... Example Of Using Vmm_test

...VMM CHANNEL RECORD AND PLAYBACK ... Recording ... Playing Back ...VMM SCENARIO GENERATOR ... Example ... Scenario Code ... Testcase ...VMM OPTS Index Introduction Vmm Log Vmm Env Vmm Data Vmm Channel Vmm Atomic Generator Vmm Xactor Vmm Callback Vmm Test Vmm Channel Record And Playback Vmm Scenario Generator Vmm Opts

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WWW.TESTBENCH.IN - VMM Tutorial

http://testbench.in/VM_00_INDEX.html[9/26/2012 1:57:13 PM]

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WWW.TESTBENCH.IN - OVM Tutorial http://testbench.in/OT_00_INDEX.html[9/26/2012 1:57:21 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ...OVM TESTBENCH ... Ovm_env ... Verification Components

... About Ovm_component Class

... Ovm_test ... Top Module ...OVM REPORTING ... Reporting Methods ... Actions ... Configuration ...OVM TRANSACTION ... Core Utilities

... User Defined Implementations

... Shorthand Macros ...OVM FACTORY ... Registration ... Construction ... Overriding ...OVM SEQUENCE 1 ... Introduction

... Sequence And Driver Communication

... Simple Example

... Sequence Item

... Sequence

... Sequencer

... Driver

... Driver And Sequencer Connectivity

... Testcase

...OVM SEQUENCE 2

... Pre Defined Sequences

... Sequence Action Macro

... Example Of Pre_do,Mid_do And Post_do

... List Of Sequence Action Macros

... Examples With Sequence Action Macros

...OVM SEQUENCE 3 ... Body Callbacks ... Hierarchical Sequences ... Sequential Sequences ... Parallel Sequences ...OVM SEQUENCE 4 ... Sequencer Arbitration

... Setting The Sequence Priority

...OVM SEQUENCE 5

... Sequencer Registration Macros

... Setting Sequence Members

Index Introduction Ovm Testbench Ovm Reporting Ovm Transaction Ovm Factory Ovm Sequence 1 Ovm Sequence 2 Ovm Sequence 3 Ovm Sequence 4 Ovm Sequence 5 Ovm Sequence 6 Ovm Configuration Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

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WWW.TESTBENCH.IN - OVM Tutorial http://testbench.in/OT_00_INDEX.html[9/26/2012 1:57:21 PM] ...OVM SEQUENCE 6 ... Exclusive Access ... Lock-Unlock ... Grab-Ungrab ...OVM CONFIGURATION ... Set_config_* Methods ... Automatic Configuration ... Manual Configurations

... Configuration Setting Members

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WWW.TESTBENCH.IN - Easy Labs : SV http://testbench.in/SL_00_INDEX.html[9/26/2012 1:57:28 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ...SPECIFICATION ... Switch Specification ... Packet Format ... Packet Header ... Configuration ... Interface Specification ... Memory Interface ... Input Port ... Output Port ...VERIFICATION PLAN ... Overview ... Feature Extraction

... Coverage Plan ... Verification Environment ...PHASE 1 TOP ... Interfaces ... Testcase ... Top Module

... Top Module Source Code

...PHASE 2 ENVIRONMENT ... Environment Class

... Run

... Environment Class Source Code

...PHASE 3 RESET ...PHASE 4 PACKET

... Packet Class Source Code

... Program Block Source Code

...PHASE 5 DRIVER

... Driver Class Source Code

...PHASE 6 RECEIVER

... Receiver Class Source Code

...PHASE 7 SCOREBOARD

... Scoreboard Class Source Code

... Source Code Of The Environment Class

...PHASE 8 COVERAGE

... Source Code Of Coverage Class

... Source Code Of The Scoreboard Class

...PHASE 9 TESTCASE

... Source Code Of Constraint Testcase

Index Introduction Specification Verification Plan Phase 1 Top Phase 2 Environment Phase 3 Reset Phase 4 Packet Phase 5 Driver Phase 6 Receiver Phase 7 Scoreboard Phase 8 Coverage Phase 9 Testcase Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

(29)

WWW.TESTBENCH.IN - Easy Labs : SV

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(30)

WWW.TESTBENCH.IN - Easy Labs : UVM http://testbench.in/UL_00_INDEX.html[9/26/2012 1:57:36 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION

... Installing Uvm Library

...SPECIFICATION ... Switch Specification ... Packet Format ... Configuration ... Interface Specification ...VERIFICATION PLAN ... Overview ... Feature Extraction

... Verification Environment ...PHASE 1 TOP ... Interface ... Top Module ...PHASE 2 CONFIGURATION ... Configuration

... Updates To Top Module

...PHASE 3 ENVIRONMENT N TESTCASE ... Environment

... Testcase

...PHASE 4 PACKET ... Packet

... Test The Transaction Implementation

...PHASE 5 SEQUENCER N SEQUENCE ... Sequencer ... Sequence ...PHASE 6 DRIVER ... Driver ... Environment Updates ... Testcase Updates ...PHASE 7 RECEIVER ... Receiver

... Environment Class Updates

...PHASE 8 SCOREBOARD ... Scoreboard

Index Introduction Specification Verification Plan Phase 1 Top Phase 2 Configuration Phase 3 Environment N Testcase Phase 4 Packet Phase 5 Sequencer N Sequence Phase 6 Driver Phase 7 Receiver Phase 8 Scoreboard Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

(31)

WWW.TESTBENCH.IN - Easy Labs : UVM

http://testbench.in/UL_00_INDEX.html[9/26/2012 1:57:36 PM]

(32)

WWW.TESTBENCH.IN - Easy Labs : OVM http://testbench.in/CM_00_INDEX.html[9/26/2012 1:57:46 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ...SPECIFICATION ... Switch Specification ... Packet Format ... Configuration ... Interface Specification ...VERIFICATION PLAN ... Overview ... Feature Extraction

... Verification Environment ...PHASE 1 TOP ... Interface ... Top Module ...PHASE 2 CONFIGURATION ... Configuration

... Updates To Top Module

...PHASE 3 ENVIRONMENT N TESTCASE ... Environment

... Testcase

...PHASE 4 PACKET ... Packet

... Test The Transaction Implementation

...PHASE 5 SEQUENCER N SEQUENCE ... Sequencer ... Sequence ...PHASE 6 DRIVER ... Driver ... Environment Updates ... Testcase Updates ...PHASE 7 RECEIVER ... Receiver

...PHASE 8 SCOREBOARD ... Scoreboard

Index Introduction Specification Verification Plan Phase 1 Top Phase 2 Configuration Phase 3 Environment N Testcase Phase 4 Packet Phase 5 Sequencer N Sequence Phase 6 Driver Phase 7 Receiver Phase 8 Scoreboard Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

(33)

WWW.TESTBENCH.IN - Easy Labs : OVM

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(34)

WWW.TESTBENCH.IN - Easy Labs : VMM http://testbench.in/VL_00_INDEX.html[9/26/2012 1:57:53 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ...SPECIFICATION ... Switch Specification ... Packet Format ... Configuration ... Interface Specification ...VERIFICATION PLAN ... Overview ... Feature Extraction

... Coverage Plan ... Verification Environment ...PHASE 1 TOP ... Interfaces ... Testcase ... Top Module

... Top Module Source Code

...PHASE 2 ENVIRONMENT ... Environment Class

... Run

...PHASE 3 RESET ...PHASE 4 PACKET

... Packet Class Source Code

... Program Block Source Code

...PHASE 5 GENERATOR

...PHASE 6 DRIVER

... Driver Class Source Code

...PHASE 7 RECEIVER

... Receiver Class Source Code

...PHASE 8 SCOREBOARD

... Scoreboard Class Source Code

... Source Code Of The Environment Class

...PHASE 9 COVERAGE

... Source Code Of Coverage Class

Index Introduction Specification Verification Plan Phase 1 Top Phase 2 Environment Phase 3 Reset Phase 4 Packet Phase 5 Generator Phase 6 Driver Phase 7 Receiver Phase 8 Scoreboard Phase 9 Coverage Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

(35)

WWW.TESTBENCH.IN - Easy Labs : VMM

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(36)

WWW.TESTBENCH.IN - AVM Switch TB http://testbench.in/AV_00_INDEX.html[9/26/2012 1:58:01 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...AVM INTRODUCTION ... Tlm ... Building Blocks ... Avm_transactors ... Avm_env ... Avm_messaging ...DUT SPECIFICATION ... Configuration ... Interface Specification ... Memory Interface ... Input Interface ... Output Interface ...RTL ...TOP ... Verilog Top ...INTERFACE ...ENVIRONMENT ...PACKET ...PACKET GENERATOR ...CONFIGURATION ...DRIVER ...RECIEVER ...SCOREBOARD Index Avm Introduction Dut Specification Rtl Top Interface Environment Packet Packet Generator Configuration Driver Reciever Scoreboard

(37)

WWW.TESTBENCH.IN - AVM Switch TB

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(38)

WWW.TESTBENCH.IN - Verilog for Verification http://testbench.in/TB_00_INDEX.html[9/26/2012 1:58:09 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION

... Test Bench Overview

...LINEAR TB

... Linear Testbench

...FILE IO TB

... File I/O Based Testbench

...STATE MACHINE BASED TB ...TASK BASED TB

... Task And Function Based Tb

...SELF CHECKING TESTBENCH ... Stimulus Generator

... Bus Functional Models

... Driver ... Reciver ... Protocol Monitor ... Scoreboard ... Checker ... Coverage ... Code Coverage ... Functional Coverage ...VERIFICATION FLOW ... Planning ... Feature Extraction

... Verification Environment Architecture Plan

...CLOCK GENERATOR

... Timescale And Precision Enlightment

...SIMULATION ... Simulation Steps ... Macro Preprocessing ... Compilation (Analyzer) ... Elaboration ... Optimization ... Initialization ... Execution ... Simulation Process ...INCREMENTAL COMPILATION ...STORE AND RESTORE ...EVENT CYCLE SIMULATION ... Event Based Simulation

... Cycle Based Simulation

...TIME SCALE AND PRECISION

... Time Scale And Time Precision

... $Time Vs $Realtime

... System Task Printtimescale

Index Introduction Linear Tb File Io Tb

State Machine Based Tb Task Based Tb

Self Checking Testbench Verification Flow Clock Generator Simulation

Incremental Compilation Store And Restore Event Cycle Simulation Time Scale And Precision Stimulus Generation System Function Random A Myth

Race Condition Checker

Task And Function Process Control Disableing The Block Watchdog

Compilation N Simulation Switchs

Debugging

About Code Coverage Testing Stratigies File Handling Verilog Semaphore Finding Testsenarious Handling Testcase Files Terimination

Error Injuction Register Verification Parameterised Macros White Gray Black Box Regression

Tips

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WWW.TESTBENCH.IN - Verilog for Verification

http://testbench.in/TB_00_INDEX.html[9/26/2012 1:58:09 PM]

... System Task Timeformat

...STIMULUS GENERATION

...SYSTEM FUNCTION RANDOM A MYTH ...RACE CONDITION

... What Is Race Condition?

... Why Race Condition?

... When Race Is Visible?

... How To Prevent Race Condition?

... Types Of Race Condition

... Write-Write Race

... Read-Write Race

... More Race Example

... Event Terminology

... The Stratified Event Queue

... Determinism

... Nondeterminism

... Guideline To Avoid Race Condition

... Avoid Race Between Testbench And Dut

...CHECKER

... Protocol Checker

... Data_checker

... Modularization

...TASK AND FUNCTION ... Functions

... Task

... Task And Function Queries

... Constant Function

... Reentrant Tasks And Functions

...PROCESS CONTROL ... Nonblocking Task

... Fork/Join Recap

... Fork/Join None

... Fork/Join Any

...DISABLEING THE BLOCK ... Disable

... Goto

... Break

... Continue

...WATCHDOG

...COMPILATION N SIMULATION SWITCHS ... Compilation And Simulation Directives

... Example

...DEBUGGING

... Pass Or Fail

... Waveform Viewer

... Log File

... Message Control System

... Message Severity Levels

... Message Controlling Levels

... Passing Comments To Waveform Debugger

... $Display N $Strobe

... Who Should Do The Rtl Debugging?

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... Types Of Coverage

... Code Coverage

... Statement Coverage /Line Coverage

... Block/Segment Coverage

... Branch / Decision / Conditional Coverage

... Path Coverage

... Expression Coverage

... Toggle Coverage

... Variable Coverage

... Triggering / Event Coverage

... Parameter Coverage ... Functional Coverage ... Fsm Coverage ... State Coverage ... Transition Coverage ... Sequence Coverage ... Tool Support

... Limitation Of Code Coverage

...TESTING STRATIGIES ... Bottom-Up ... Unit Level ... Sub-Asic Level ... Asic Level ... System Level ... Flat ...FILE HANDLING

... Fopen And Fclose

... Fdisplay

... Fmonitor

... Fwrite

... Mcd

... Formating Data To String

...VERILOG SEMAPHORE ... Semaphore In Verilog ...FINDING TESTSENARIOUS ... Register Tests ... System Tests ... Interrupt Tests ... Interface Tests ... Functional Tests ... Error Tests ... Golden Tests ... Performance Tests

...HANDLING TESTCASE FILES ...TERIMINATION ...ERROR INJUCTION ... Value Errors ... Temporal Errors ... Interface Error ... Sequence Errors ...REGISTER VERIFICATION ... Register Verification ... Register Classification ... Features ...PARAMETERISED MACROS ...WHITE GRAY BLACK BOX ... Black Box Verification

... White Box Verification

... Gray Box Verification

...REGRESSION ...TIPS

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... Colourful Messages

... Debugging Macros

(42)

WWW.TESTBENCH.IN - Verilog Switch TestBench http://testbench.in/VS_00_INDEX.html[9/26/2012 1:58:17 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...DUT SPECIFICATION ... Configuration ... Interface Specification ... Memory Interface ... Input Interface ... Output Interface ...RTL ...TOP ... Verification Environment ... Top Module ...PACKET ...DRIVER ...RECIEVER ...SCOREBOARD ...ENV Index Dut Specification Rtl Top Packet Driver Reciever Scoreboard Env

(43)

WWW.TESTBENCH.IN - Verilog Switch TestBench

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(44)

WWW.TESTBENCH.IN - Verilog Basic Constructs http://testbench.in/VT_00_INDEX.html[9/26/2012 1:58:27 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ... Introduction ...SYNTAX ...DATA TYPES ... Value Set ... Net ... Variable Or Reg ... Vectors ... Memories ... Net Types ...OPERATORS

... Binary Arithmetic Operators

... Unary Arithmetic Operators

... Relational Operators

... Logical Operators

... Bitwise Operators

... Unary Reduction Operators

... Other Operators

... Operator Precedence

...ASSIGNMENTS

... Blocking Procedural Assignments

... The Nonblocking Procedural Assignment

... Procedural Continuous Assignments

... Assign And Deassign Procedural Statements

... Force And Release Procedural Statements

... Delays

... Inter Assignmnet Delay .

... Intra-Assignment Delay Control

...CONTROL CONSTRUCTS

... If And If Else Statements

... Case

... Forever

... Repeat

... While

... For

...PROCEDURAL TIMING CONTROLS ... Delay Control ... Event Control ... Named Events ...STRUCTURE ... Module ... Ports ... Signals ...BLOCK STATEMENTS ... Sequential Blocks ... Parallel Blocks ...STRUCTURED PROCEDURES Index Introduction Syntax Data Types Operators Assignments Control Constructs Procedural Timing Controls Structure Block Statements Structured Procedures Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

(45)

WWW.TESTBENCH.IN - Verilog Basic Constructs http://testbench.in/VT_00_INDEX.html[9/26/2012 1:58:27 PM] ... Initial ... Always ... Functions ... Task

(46)

WWW.TESTBENCH.IN - Vera Constructs http://testbench.in/OV_00_INDEX.html[9/26/2012 1:58:37 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ... Introduction ... Comments In Openvera ... Numbers In Openvera ...DATA TYPES

... Basic Data Types

... Integer ... Register ... String ... Event ... Enumerated Types ... Virtual Ports ... Arrays ... Fixed-Size Arrays ... Dynamic Arrays ... Associative Arrays ... Smart Queues ... Class ...LINKED LIST ... Linked List ... List Methods ...OPERATORS PART 1 ... Operators ... Concatenation ... Arithmetic ... Relational ... Equality ...OPERATORS PART 2 ... Logical ... Bitwise ... Reduction ...OPERATORS PART 3 ... Shift ... Bit-Reverse

... Increment And Decrement

... Conditional ... Set ... Replication ...OPERATOR PRECEDENCE ... Operator Precedence ...CONTROL STATEMENTS ... Sequential Statements

...PROCEDURES AND METHODS ... Procedures And Methods

... Pass By Value ... Pass By Reference ... Default Arguments ... Optional Arguments Index Introduction Data Types Linked List Operators Part 1 Operators Part 2 Operators Part 3 Operator Precedence Control Statements Procedures And Methods Interprocess

Fork Join

Shadow Variables Fork Join Control Wait Var Event Sync Event Trigger Semaphore Regions Mailbox Timeouts Oop Casting Randomization Randomization Methods Constraint Block Constraint Expression Variable Ordaring Aop Predefined Methods String Methods Queue Methods Dut Communication Functional Coverage Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!

(47)

WWW.TESTBENCH.IN - Vera Constructs

http://testbench.in/OV_00_INDEX.html[9/26/2012 1:58:37 PM]

...INTERPROCESS

... Interprocess Synchronization And Communication

...FORK JOIN ... Fork Join

...SHADOW VARIABLES ... Shadow Variables

...FORK JOIN CONTROL

... Fork And Join Control

... Wait_chiled() ... Terminate ... Suspend_thread ...WAIT VAR ... Wait_var ...EVENT SYNC ... Event Methods ...EVENT TRIGGER ... Event Trigger ... Event Variables ...SEMAPHORE ... Semaphore ...REGIONS ... Regions ...MAILBOX ... Mailbox ...TIMEOUTS ... Timeouts ...OOP

... Object Oriented Programming

... Properties ... This ... Class Extensions ... Polymorphism ... Super ... Abstract Class ...CASTING ...RANDOMIZATION

... Constrained Random Verification

... Random Varible Declaration

... Rand Modifier

... Randc Modifier

...RANDOMIZATION METHODS

... Randomization Built-In Methods

... Randomize()

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WWW.TESTBENCH.IN - Vera Constructs

http://testbench.in/OV_00_INDEX.html[9/26/2012 1:58:37 PM]

...CONSTRAINT BLOCK ... Constraint Block

... Inline Constraints

... Disabling Constraint Block

...CONSTRAINT EXPRESSION ... Constraint Expressions ... Set Membership ... Weighted Distribution ... Implication ... If..Else ... Iterative ...VARIABLE ORDARING ... Variable Ordaring ...AOP

... Aspect Oriented Extensions

...PREDEFINED METHODS ... Predefined Methods

... New()

... Finalize()

... Object_print

... Deep Object Compare

... Deep Object Copy

... Pack And Unpack

...STRING METHODS ...QUEUE METHODS ...DUT COMMUNICATION ... Connecting To Hdl

... Interface Declaration

... Direct Hdl Node Connection

... Blocking And Non-Blocking Drives

...FUNCTIONAL COVERAGE ... Functional Coverage ... Coverage Group ... Sample_event ... Coverage_point ... Cross Coverage

(49)

WWW.TESTBENCH.IN - Vera Switch TestBench http://testbench.in/OS_00_INDEX.html[9/26/2012 1:58:44 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...DUT SPECIFICATION ... Configuration ... Interface Specification ... Memory Interface ... Input Interface ... Output Interface ...RTL ...TOP ... Verification Environment ... Top Module ...INTERFACE ...PACKET ...PACKET GENERATOR ...CFG DRIVER ...DRIVER ...RECIEVER ...SCOREBOARD ...ENV Index Dut Specification Rtl Top Interface Packet Packet Generator Cfg Driver Driver Reciever Scoreboard Env

(50)

WWW.TESTBENCH.IN - Vera Switch TestBench

http://testbench.in/OS_00_INDEX.html[9/26/2012 1:58:44 PM]

(51)

WWW.TESTBENCH.IN - RVM Switch TB http://testbench.in/RV_00_INDEX.html[9/26/2012 1:58:52 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

INDEX

...INTRODUCTION ... Dut Specification ... Configuration ... Interface Specification ... Memory Interface ... Input Interface ... Output Interface ...RTL ...TOP ...INTERFACE ...PROGRAM BLOCK ... Testbench Program ...ENVIRONMENT ...PACKET ...CONFIGURATION ...DRIVER ...RECIEVER ...SCOREBOARD Index Introduction Rtl Top Interface Program Block Environment Packet Configuration Driver Reciever Scoreboard

(52)

WWW.TESTBENCH.IN - RVM Switch TB

http://testbench.in/RV_00_INDEX.html[9/26/2012 1:58:52 PM]

(53)

WWW.TESTBENCH.IN http://testbench.in/ethernet_rvm.html[9/26/2012 1:58:59 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : OVM Easy Labs : VMM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

RVM Ethernet

This testbench is developed in RVM (Vera) for the Ethernet core available from opencores.org. My intension here is to explore the RVM methodology but not to verify the Ethernet core, as a result there are many bugs in the environment. I dont remember the versions of RVM but I developed these in the third quarter of 2007. To simulate this testbench some dependencies on libraries has to be removed from RTL. It takes bit time for these changes in RTL.

Feauters:

Full support of automatic random, constrained random, and directed testcase creation. Supports injuction of random errored packets.

Supports 1G Fullduplex modeled both in RX and TX paths. Protocol Checker/Monitor for self checking.

Built in function coverage support for packets. Developed in Vera using Synopsys RVM base classes.

NOTE: All trademarks are the property of their respective owners. Download rvm.tar

Browse the code in rvm_eth.tar

BLOCK DIAGRAM OF ETHERNET VERIFICATION ENVIRONMENT

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WWW.TESTBENCH.IN

http://testbench.in/ethernet_rvm.html[9/26/2012 1:58:59 PM]

(55)

WWW.TESTBENCH.IN http://testbench.in/art.html[9/26/2012 1:59:07 PM] TUTORIALS SystemVerilog Verification Constructs Interface OOPS Randomization Functional Coverage Assertion DPI UVM Tutorial VMM Tutorial OVM Tutorial Easy Labs : SV Easy Labs : UVM Easy Labs : VMM Easy Labs : OVM AVM Switch TB VMM Ethernet sample Verilog Verification Verilog Switch TB Basic Constructs OpenVera Constructs Switch TB RVM Switch TB RVM Ethernet sample Specman E Interview Questions

UVM/OVM Killing Sequences on Sequencer Abruptly by Vishnu Prashant.

Sometimes you may need to drive input until you see come condition or some timer expires. Read ...

Do not rely on illegal_bins for checking purpose. by Ankit Gopani. If you rely on cover group where you have written illegal_bins, what happens when you turn off the coverage?? Read ...

PASS and FAIL Messages with Colors...! by Ankit Gopani.

How many among you know that you can actually display color messages using Verilog and SystemVerilog? Read ...

VMM 1.2 and VMM_sb_ds example by Ankit Shah.

This example contains VMM 1.2 based layered testbench architeracture. My intensation here is to demonstrate different component of testbench using different base class of VMM. Read ...

Whats new in Systemverilog 2009 ? by Ankit Shah.

The SystemVerilog working group worked hard in the past four years on improving the language and in 2009 Systemverilog LRM was released. There are 30+ noticeable new constructs and 25+ system task are introduced in SystemVerilog 2009. Read ...

Introduction To Ethernet Frames: Part 1 by Bhavani shankar.

The Ethernet protocol basically implements the bottom two layers of the Open Systems Interconnection (OSI) 7-layer model, i.e., the data link and physical sub 7-layers. Read ...

Introduction To Ethernet Frames: Part 2 by Bhavani shankar. we will see a simple testplan for 10G Ethernet Frames. Read ...

Introduction To PCI Express by Arjun Shetty.

We will start with a conceptual understanding of PCI Express. This will let us appreciate the importance of PCI Express. This will be followed by a brief study of the PCI Express protocol. Then we will look at the enhancements and improvements of the protocol in the newer 3.0 specs. Read ...

VCSMX Separate compilation example by Emmanuelle Chu.

When I started to use VCSMX along with system Verilog, one main problem came up: I had to generate one executable for each program. Read ...

Psychology of Verification Engineer by Gopi Krishna.

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WWW.TESTBENCH.IN

http://testbench.in/art.html[9/26/2012 1:59:07 PM]

Soft skills are extremely important for the people in Verification and this is something that is often found to be neglected by the upcoming Verification engineers. Read ...

Graphical TestBench Generation by Donna Mitchell.

Test Benches can be generated from language independent timing diagrams, which are a natural way to design and display the parallel activity that occurs in within test benches. Read ...

Verilog Basic Examples by Nithin Singani.

Verilog examples with output: and,or,not,halfadder,fulladder etc Read ...

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