5.1 a. How many 128 x 8 RAM chips are needed to provide a memory capacity of
2048 bytes?
b. How many lines of the address bus must be used to access 2048 bytes of
memory? How many of these lines will be common to all chips?
c. How many lines must be decoded for chip select? Specify the size of the
decoders.
5.2 A computer uses RAM chips of 1024 x 1 capacity.
a. How many chips are needed, and how should their address lines be connected to provide a memory capacity of 1024 bytes? b. How many chips are needed to provide a
memory capacity of 16K bytes? Explain in words how the chips are to be connected to the address bus.
5.3 A ROM chip of 1024 x 8 bits has four select inputs and operates from a 5-volt power supply. How many pins are needed for the IC package? Draw a block diagram and label all input and output terminals in the ROM.
5.4 A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer system needs 2K bytes of RAM, 4K bytes of ROM, and four interface units, each with four registers. A memory-mapped I/O configuration is used. The two highest-order bits of the address bus are assigned 00 for RAM, 01 for ROM, 10 for interface registers. a. How many RAM and ROM chips are
needed?
PROBLEM S
b. Draw a memory-address map for the system.
c. Give the address range in hexadecimal for RAM, ROM, and interface.
5.5 An 8-bit computer has a 16-bit address bus. The first 15 lines of the address are used to select a bank of 32K bytes of memory. The high-order bit of the address is used to select a register which receives the contents of the data bus. Explain how this configuration can be used to extend the memory capacity of the system to eight banks of 32K bytes each, for a total of 256K bytes of memory.
5.6 A magnetic disk system has the following parameters:
s
T = seek time; average time to position the magnetic head over a track
R= rotation speed of disk in revolutions per second
t
N = number of bits per track
s
N = number of bits per sector
Calculate the average time Ta that it will take
to read one sector.
5.7 Obtain the complement function for the match logic of one word in an associative memory. In other words, show that '
i
M is the sum of exclusive-OR functions. Draw the logic diagram for '
i
M and terminate it with an
inverter to obtain Mi .
5.8 Obtain the Boolean function for the match logic of one word in an associative memory taking into consideration a tag bit that indicates whether the word is active or inactive.
5.9 What additional logic is required to give a no-match result for a word in an associative memory when all key bits are zeros?
5.10 Describe in words and by means of a block diagram how multiple matched words can be read out from an associative memory.
5.11 Derive the logic of one cell and of an entire word for an associative memory that has an output indicator when the unmasked argument is greater than (but not equal to) the word in the associative memory.
5.12 Consider a 32-bit microprocessor that has an on-chip 16 Kbytes four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ADCDE8F8 mapped?
5.13 Given the following specifications for an external cache memory: four-way set associative: line size of two 16-bit words: able to accommodate a total of 4K 32-bit words from main memory: used with a 16-bit processor that issues 24-bit addresses. Design the cache structure with all pertinent information and show how it interprets the processor's addresses.
5.14 A set associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K x 32 bits. Design the cache
structure and show how the processor's addresses are interpreted.
5.1 Referring to the organization in Fig.5-4: (a)
The total memory capacity = 2048 = 11 2 bytes
The capacity of a one RAM chip = 128 = 7
2 bytes
Solutions For Selected Problems
The number of memory chips needed = 11 2 / 7 2 = 16 memory chips. (b) To access 2048 ( e.g 11
2 ) bytes, 11 bits for addressing are needed.
Each chip has capacity of 7
2 bytes 7 bits for addressing must be common to all chips.
(c)
We have 16 memory chip 4 selection bits are needed.
The 4 selection bits are decoded to 16 bit
an 4
×
16 decoder is needed.5.4 (a)
The total RAM capacity = 2K = 2048 = 11
2 bytes
The capacity of a one RAM chip = 256 = 8
2 bytes
The number of memory chips needed = 11
2 / 28= 8 memory chips.
The total ROM capacity = 4K = 4096 = 12 2 bytes
The capacity of a one RAM chip = 1024 = 10
The number of memory chips needed = 12
2 / 10
2 = 4 memory chips.
(b) The memory and I/O address map for the system is shown below:
Address Bus component Hexadecimal address 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RAM1 0000 – 00FF 0 0 0 0 0 0 X X X X X X X X RAM2 0100 – 01FF 0 0 0 0 0 1 X X X X X X X X RAM3 0200 – 02FF 0 0 0 0 1 0 X X X X X X X X RAM4 0300 – 03FF 0 0 0 0 1 1 X X X X X X X X RAM5 0400 – 04FF 0 0 0 1 0 0 X X X X X X X X RAM6 0500 – 05FF 0 0 0 1 0 1 X X X X X X X X RAM7 0600 – 06FF 0 0 0 1 1 0 X X X X X X X X RAM8 0700 – 07FF 0 0 0 1 1 1 X X X X X X X X ROM1 1000 – 13FF 0 1 0 0 X X X X X X X X X X ROM2 1400 – 17FF 0 1 0 1 X X X X X X X X X X ROM3 1800 – 1BFF 0 1 1 0 X X X X X X X X X X ROM4 1C00 – 1FFF 0 1 1 1 X X X X X X X X X X Interface1 2000 – 2003 1 0 0 0 0 0 0 0 0 0 0 0 X X Interface2 2004 – 2007 1 0 0 0 0 0 0 0 0 0 0 1 X X Interface3 2008 – 200B 1 0 0 0 0 0 0 0 0 0 1 0 X X Interface4 200C – 200F 1 0 0 0 0 0 0 0 0 0 1 1 X X (c)
The address ranges are shown in the table above.
5.7 Referring to section 5.4.2:
The match logic M for a word i:
) )...( )( )( ( 1 1' 2 2' 3 3' n n' i x K x K x K x K M = + + + + n n n n n n i K x K x K x K x K x K x K x K x K x K x K x K x M ... ) ...( ) ( ) ( ) ( ] ) )...( )( )( [( 3 3 2 2 1 1 ' ' 3 3 ' 2 2 ' 1 1 ' ' 3 3 ' 2 2 ' 1 1 + + + = + + + + + + + = + + + + = →
We have: ij j ij j ij j j ij j ij j j F A F A F A x F A F A x ⊕ = + = → + = ' ' ' '
We can say that:
∑
=⊕
=
n j j ij j iA
F
K
M
1)
(
M is the sum of exclusive-OR i'
functions.
The logic diagram can be easily drawn referring to Fig.5-9.
5.9 In the match logic described in Fig.5-9, when all key bits are zeros
M
i=
1
To give no-match result when all key bits are zeros, we can add the following logic:
∑
=⋅
=
n i i i inew
M
K
M
1)
(
5.13Number of lines per set = 4 Line size = 2 word (16-bit word)
Total cache capacity = 4K word (32-bit word)
= 4 * 2 = 8K word (16-bit word).K Number of lines in the cache
=cache capacity / Line size = 8K / 2 = 4K Lines
Total number of sets in the cache
= Number of lines in the cache / Number of lines per set
= 4K / 4 =
2
10 sets.As the processor has a 24-bit address: The cache address will be mapped as
f o l l o w s : 1-bit for selecting the word within a line.
10-bits for the Set addressing.
The remaining 13-bits will be reserved as tag bits
The arrangement will be as follows:
13-bit 10-bit 1-bit
1 A computer uses RAM chips of 1024 x 1 capacity.
a. How many chips are needed, and how should their address lines be connected to provide a memory capacity of 1024 bytes? b. How many chips are needed to provide a
memory capacity of 16K bytes? Explain in words how the chips are to be connected to the address bus.
2 A ROM chip of 1024 x 8 bits has four select inputs and operates from a 5-volt power supply. How many pins are needed for the IC package? Draw a block diagram and label all input and output terminals in the ROM.
3 Describe in words and by means of a block diagram how multiple matched words can be read out from an associative memory.
4 Consider a 32-bit microprocessor that has an on-chip 16 Kbytes four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ADCDE8F8 mapped? 5 A set associative cache has a block size of
four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K x 32 bits. Design the cache structure and show how the processor's addresses are interpreted.
