course230B2

P-N Junctions/Diodes

p

_n

p

_n

I

V

log I

log I

slope = 60 mV/decade

I

V

slope = 60 mV/decade

V

V

Static Properties

p

(a) c E E E_i E_f c E E E_i E_f q E_v n-type p-type E_v c E E (b) q bi E_v E_i E_f Ec E_v E_i E_f 0 dx dn q kT n q J_{n n E}

No net current

dx d = i E E E kT kT ( )/ ( )/ d E d x f ₀

No net current

flow at thermal

equilibrium:

n n e_i (E E kTf i)/ n e_i q( i f)/kT

Built-in Potential

• Fermi level E

_ff

is spatially constant (flat), causing a

built-in potential difference across the diode.

• Built-in potential:

p

0 0 2

ln

ln

ln

a d p n bi

n

n

kT

p

p

kT

N

N

kT

q

p

_p

= (majority) hole density on p-side N

_a

0

0 p

n

i

p

n

n

p

_n

= (minority) hole density on n-side

n

_n

= (majority) electron density on n-side N

_d

Abrupt Junctions: Depletion Approx.

Q uasi-neutral p-region Q uasi-neutral n-region D epletion region 2 0 xn x -x_p (x) qN d d dx qN i d si 2 2 d2 _i qN_a for 0 x x_n for -x x 0 0 n p E (x) a -qN E_m d i d n a p d qN x qN x dx2 _si for xp x 0 x E(x) -E_m -x_p 0 xn m x si si dx 0 2 2 ) ( _{n p m d} m m W x x E E m m p (x) - (-x ) i i W N N qN N d si a d m a d 2 ( ) 2 2 x m xn -x_p 0 m bi Vapp

One-Sided n

+

_{-p Diode}

_p

Q u asi-n eu tral n-region Q uasi-neutral p -region D epletion region (x) q N _d -x_n xp 0 x n a -q N

Charge neutrality: N

_d

x

_n

= N

_a

x

_p

, if N

_d

>> N

_a

x

_p

>> x

_n

,

i e depletion layer and voltage drop primarily appear

i.e., depletion layer and voltage drop primarily appear

on the lightly doped side.

One-Sided n

+

_{-p Diode}

_p

Built-in potential:

1.05 i a g bi n N kT E q ln 2 0.95 1.00 1.05 (V ) 0.85 0.90 in po te nt ia l 0.75 0.80 Bui lt-i

1E+14 1E+15 1E+16 1E+17 1E+18

0.70

Doping concentration (cm 3)

One-Sided n

+

_{-p Diode}

_p

Depletion-layer width: _{n p p} a app bi si d x x x qN V W 2 ( )

Depletion-layer capacitance: C_d dQ_d/dV_app = _si /W_d

10 10 /µm 2) ) 1 1 cita nc e (f F/ wid th (µ m ) Cd 0.1 0.1 -l ay er c apa c etio n-la ye r W_d

1E+14 1E+15 1E+16 1E+17 1E+18

0.01 0.01 Dep le tio n-De pl e W_d Doping concentration (cm )-3

Quasi-Fermi Potentials

_n

and

_p

n i i kT q n n ln i q n p i i kT q p n ln

Nonequilibrium near the

junction pn n_i2 pn n_i2_{exp (}q _{p n) /} kT junction, pn n_i . J qn d dx kT qn dn dx qn d dx n n i n n d kT dp d J qp d dx kT qp dp dx qp d dx p p i p p

Spatial Variations of

_n

and

_p

V_app = _{p n} at junction

boundaries.

Inside the space-charge

region: J_n is constant (neglect G-R currents) [n_{n n}d _n/dx]_xn = [n_{p n}d _n/dx] _xp [d _n/dx at x_n] << [d _n/dx at x_p]

n ~ constant inside space-charge region

Practically all spatial variation in _n occurs in p-region, Likewise, all spatial variation in _p occurs in n-region.

Currents in a p-n Junction

(x) Quasi-neutral n-region Quasi-neutral p-region Depletion region Generation-recombination currents in space-charge region are usually negligible

x xp

qN _d region are usually negligible.

Electron current leaving n-side = electron current

t i id 0 x -xn p a -qN entering p-side.

Hole current leaving p-side = hole current entering n side Ec Ev n+ p n-side. Need to consider minority carriers and

Ev

e h

minority carriers and currents only.

Total current in diode =

0 W

0 _{electron current + hole}

Excess Electrons in the p-Region

0 1 n n n _{R G} x J q t n dx dn kT dx dn qn kT dx d qn J_{n n n} n n n n n G R 0 q _n L D kT q n n n n n d n dx n n L p p p n 2 2 0 2 0, where is the

minority carrier diffusion length. Boundary conditions: Space-charge region Boundary conditions: at x=0, and

n_p n_p0 exp qV_app / kT _{Emitter Base}

at x=W (ohmic contact). n_p n_p0 x 0 n+ p W

Excess Electrons in the p-Region

d n dx n n L p p p n 2 2 0 2 0, Boundary conditions: t 0 n_p n_p0 exp qV_app / kT at x=0, and at x=W (ohmic contact). n_p n_p0 np np np qVapp kT W_{W L}x L n n 0 0 exp( / ) 1 sinh ( ) / sinh( / ) . 0.8 1 ron de ns ity a (o c co ac ) W/L = 0.2 0.4 0.6 exc es s el ec tr 0.5 1.0 _2.0 exp(-x/L) 0 0.2 N om al iz ed e 0 0.5 1 1.5 2 2.5 3 0 x/L N

Wide-Base and Narrow-Base Diodes

J x qD dn dx n n p x ( 0) 0 qD n qV kT L W L n p app n n 0 exp( / ) 1 tanh( / ) qD n qV kT p L W L n i app p n n 2 0 1 exp( / ) tanh( / ) Wide-base: W>>L_n Forward-bias: J_n(x = 0)= [qD_nn_i2_/N aLn]exp(qVapp/kT) C t i ti ll ith V t 60 V

Current increases exponentially with V_app, at 60 mV per

decade at RT.

Reverse-bias: J_n(x = 0)= [qD_nn_i2_/N

aLn]

Electrons on p side but within a diffusion length of the Electrons on p-side but within a diffusion length of the depletion-region boundary diffuse towards n-side.

N b W<<L Narrow-base: W<<L_n Forward-bias: J_n(x = 0)= [qD_nn_i2_/N aW]exp(qVapp/kT) Reverse-bias: J_n(x = 0)= [qD_nn_i2_/N aW]

Currents increase rapidly as W decreases! Currents increase rapidly as W decreases!

Turning Off a p-n Diode

Excess electrons in p-region

t < 0

n+ _p

V_{F R i(t)}

Q q nW( n dx)

Effective turn off starts only after most excess minority carriers have

V_R n+ _p R i(t) t > 0 Q_B q n( _p n dx_p ) 0 0

recombined or have drained off.

t ts i(t) I_F x 0 1E-4 s) Electrons Holes t -I_R 0 ( ) 1E-7 1E-6 1E-5 arrie r lif etim e (s t = 0 t > 0 t = t_s (n - n )p _p0 1E-10 1E-9 1E-8 Minor ity -c a s x 0

1E+170 1E+18 1E+19 1E+20

Diffusion Capacitance

Diffusion capacitance C_D is due to stored minority carriers

responding to applied voltage responding to applied voltage.

C_D due to electrons stored in p-type region:

C dQ /dV ( V /kT)

C_Dn = dQ_B/dV_app exp(qV_app/kT)

For a diode or bipolar transistor to switch fast, it must have minimal diffusion capacitance

minimal diffusion capacitance.

To minimize diffusion capacitance: increase doping

concentration and minimize charge-storage volume. concentration and minimize charge storage volume.

Modern high-speed bipolar transistors require very thin base.

MOS Device

Silicon dioxide Gate electrode (metal or polysilicon) tox Vacuum Vacuum Silicon substrate Vacuum level Vacuum level Ec = 4.10 eV 0.95 eV = 4.05 eV q q m q Ec Ev 8-9 eV q s Metal ( l i ) 1.12 eV Eg q B _EEi f E_f Ev v (aluminum) Silicon (p-type) f g E v Silicon dioxide s g B q 2

Flatband Condition

ox ox ms ox ox s m fb C Q C Q V ( ) C t ox ox ox Ec 0.95 eV Free electron level = 4 05 eV q q m 0.95 eV Free electron level = 4 05 eV q 4.05 eV E_f q s m E_f Ec 4.05 eV E_f q s q m E_f q( _{s m}) Ev Silicon (p-type) f Metal Ev Silicon (p-type) f Metal f (a) SiO2 v SiO2 (b)

Fig. 2.29. Band diagrams of an MOS system under (a) the flatband condition, and (b) zero gate-voltage condition.

Rules of Band Diagram

Rules of Band Diagram

1 I

i

i l E

d

i

1. In a given material, E

_g

and q are given.

They do not change spatially.

2. The free electron level is continuous at the

interface between two different materials.

3. The displacement (D =

E ) is continuous at

Example: Heterojunction

Example: Heterojunction

q ₁ q ₂ q ₁ q E_g2 q ₂ E_g1 g2 E_g1 E_g2 band discontinuity band discontinuity

Band alignment

Zero bias voltage

Bandgap Heaven in Color

450 G Sb AlSb 1550 1350 ₂₀₀ 500 250 InGaP AlAs InAs GaSb 770 GaAs 1420 InGaAs 760 InAlAs 1460 InP 1350 200 450 InGaP₁₉₀₀ InSb 220 AlAs 2170 360 200 170 150 550 170 200

assuming alloy compositions when grown on GaAs

assumes (I guess)

not clear if this is unstrained or g y p lattice-matched to InP g

( g )

growth on a strain-relaxed layer of GaSb, so the InAs and AlSb are both somewhat strained

includes effect of strain resulting from growth on relaxed GaSb

MOS: Gate Voltage Equation

s ox s s ox fb g C Q V V V Fi 2 30 E b d d t ti l V V_{g fb} V_ox s

Fig. 2.30. Energy band and potential diagrams of an MOS capacitor showing how the bands change under different gate bias conditions. The solid lines represent the flatband condition. The E_f

dashed lines represent the condition when a positive gate voltage is applied. Note that in the diagram the electron energy increases upward while the potential or voltage increases Silicon Metal SiO V V_{g fb} E_f f E_f s V _g V_fb p g downward. Silicon (p-type) Metal SiO₂ s si ox ox

E

E

Accumulation, Depletion, Inversion

(a) Ec (e) E E V = 0g Ec Ef Ef V = 0g p-type n-type flatband _ _ _ _ _ _ _ _ Assume _m= _s: Ev Ef E_f V 0g Ev f + + + + + + + + (b) Ec (f) Ev E_f Ef Ec Ev Ef E_f accumulation V < 0g V > 0g + + + + + + _ _ _ _ _ + + _ _ __ __{_}___ __{_}_ +++ + + + + + (c) (g) depletion Ec Ev E_f E V > 0g Ec Ev Ef E_f V < 0g + + + + + _ _ _ _ _ _ _ + + inversion Ev Ef Ef V < 0g + _ (d) Ec (h) Ev Ef E_f V > 0g Ec Ev E_f + + + + _ _ _ _ + + _ _ _ __ __{_} ____ _ __ + +₊ ++ + + ++ + +

Poisson’s Equation

Silicon surface _{2 ( ) ( ) ( ) ( )} 2 x N x N x n x p q dx d dx d a d i E Ec E Eg q ( )x dx dx _si q s (> 0) Ei Ev q B q ( ) E_f p x n e_i q kT n e_i q kT N e a q kT f i B ( ) ( )/ ( )/ /

Oxide p-type silicon

x p( ) _{i i a} n x n e n e n N e i q kT i q kT i a q kT i f B ( ) ( )/ ( )/ / 2 x 1 1 / 2 / 2 2 kT q a i kT q a si e N n e N q dx d

Solving Poisson’s Equation

1 1 2 ) ( / 2 2 / 2 kT q e N n kT q e kTN dx d x q kT a i kT q si a 2 E 2 / 1 2 / / 2 2 / _{1 1} 2 kT q e N n kT q e kTN Q q kT s a i s kT q a si s si s E s s

Depletion Approximation

(1 D Uniform Doping)

(1-D Uniform Doping)

qN

Q

d

= qN W

d

W

_d

x

qN

_a

Q

d

qN

a

W

d

E = qN

_a

(W

_d

- x)/

_si

E

E

= qN

_a

(W

_d

- x)

2

_/2

si

N W

2

_/2

x

W

_d s

= qN

a

W

d2

/2

si

W

2

si s

x

W

_d

W

d

qN

a

x

1

2 s d

W

1

Condition for Strong Inversion

g

Silicon surface a inv kT N ( ) 2 2 ln Ec E s B i inv q n ( ) 2 2 ln q s (> 0) Ei Ev Eg q B q ( )x E_f i.e., (n_i2_/N a2)exp(q s/kT) = 1. v

Oxide p-type silicon

And the electron concentration at the surface equals the hole

x

concentration in the bulk Si.

Max. Depletion Width in MOS

(1 D Uniform Doping)

(1-D Uniform Doping)

In contrast to p-n junctions, W_d 10

In contrast to p n junctions, W_d

reaches a maximum value W_dm

at the onset of strong inversion

when _ion Wid 1 th ( µ m )

k

4

l (

/ )

s = 2 B = 2(kT/q)ln(Na/ni): _0.1 M ax im um D ep let i

W

kT

N

n

q N

dm si a i a

4

2

ln(

/ )

1.0E+14 1.0E+15 1.0E+16 1.0E+17 1.0E+18 1.0E+19 0.01

Substrate Doping Concentration (cm )

M

-3

This defines the threshold condition of a MOSFET.

W_dm also plays a key role in the short-channel

scaling of a MOSFET namel L W

Strong Inversion

d dx kTN q kT n N e a si i a q kT 2 2 2 / 1E+19 1.2E+19 Na 1016 cm 3 x) (cm )

-3 Charge per area:

Q kTn N e i si i q _s kT 2 2 _/2 6E+18 8E+18 s 088. V trati on, n (x Electron conc. at surface: N_a 2E+18 4E+18 s 085. V tron conc en t _surface: n n N e i a q _s kT ( )₀ / 2 0 50 100 150 200 0

Distance from surface, x ( )Å

El ec t Inversion layer thickness: Q_i/qn(0) = 2 _sikT/qQ_i Q_i q ( ) _si qQ_i

Quantum Effect in MOS Inversion

In an MOS inversion layer, carriers are confined in the direction perpendicular to the surface and therefore need be treated

quantum mechanically (2 D)

Silicon surface

E

quantum mechanically (2-D).

Discrete energy levels:

q s Ec Ej Slope = Es E E hq m j j s x 3 4 2 3 4 2 3 E / Ev Ec E_f

Average distance of inversion layer from the surface:

Oxide p-type silicon

x E q j j s 2 3 E from the surface:

Self-Consistent QM Solution

de

ns

ity

Classical

Electron ground state is

El e ct ro n Quantum Depth

Electron ground state is at some finite energy above the bottom of the conduction band. Conduction band edge Ox id e p

Band bending must

exceed 2 _B to invert ene rg y Lowest subband surface.

The centroid of inversion layer is farther away

Electron

Bottom of the well

layer is farther away from the surface than in the classical case.

MOSFET Charge and Potential

1.2 1E-6 V ) ₎ t = 10 nm_ox N = 10 cm_a 17 -3 2 Oxide p-type silicon q s Ec Metal Vox 0.6 0.8 1 6E-7 8E-7 otent ial (V nsit y ( C /cm s s 2 Q_s Q_i B q s Ei Ev q B Vg 0 Deple-tion Neutral region Ef 0.2 0.4 2E-7 4E-7 Sur fa ce P o Ch ar ge De n Q_d Q_i tion region Inversion region region Ef 0 0.5 1 1.5 2 2.5 3 3.5 0 0E+0 Gate Voltage (V)V_g Q_M 0 x t W dm

Gate voltage equation (V_fb=0):

Q_d Qi Qs QM

x

tox Gate voltage equation (V_fb 0):

V V Q C g o x s s o x s Note C /t 1/2 Note: C_ox= _ox/t_ox and _oxEox= _siEs 2 / 1 / 2 2 / _{1 1} 2 kT q e N n kT q e kTN Q q kT s a i s kT q a si s si s E s s

Inversion Charge in Log Scale

1E 7 1E-5 1E-6

cm

)

cm

)

2 2 1E-9 1E-7 6E-7 8E-7

sity

(

C

/c

sit

y

(

C

/c

1E-13 1E-11 4E-7

rg

e D

en

s

rg

e D

en

s

Q

_i

Q

_i 1E-15 2E-7

Inv

. C

ha

Inv

. C

ha

Q

_i B 0 0.5 1 1.5 2 2.5 3 3.5 1E-17 0E+0

Gate Voltage (V)

_V

_g

t = 10 nm

_ox

N = 10 cm

_a 17 -3

MOS Capacitances

Gate Gate Vg Vg

d Q

(

)

Cox Cox Qs Qs

C

d Q

dV

s g

(

)

d Q

(

)

C C (inversion) C

C

d Q

d

si s s

(

)

Csi Ci (low freq.) C_d Qs Q d Qi

)

(

1

1

s s ox

d

Q

d

C

C

p-type substrate n+ channel p-type substrate s ox si ox

C

C

1

1

substrate channel substrate

Capacitance-Voltage Characteristics

In accumulation, Q_s exp(-q _s/2kT), so C _i=-dQ /d =(q/2kT)Q

1

1

1

2kT q

/

so C_si=-dQ_s/d _s=(q/2kT)Q_s =(q/2kT)C_ox|V_g- _s|.

1

C

C

_ox

_V

g s

Capacitance-Voltage Characteristics

At flatband voltage, q _s/kT<<1, 1 1 kT 1 L_D

therefore, Q_s= ( _siq2_N

Capacitance-Voltage Characteristics

In depletion, where d ox C C C 1 1 1 where C d Q d qN W d d s si a s si d ( ) 2 Note that V qN W C qN C g a d s si a s s 2 C C g ox s ox s

Capacitance-Voltage Characteristics

Inversion, high freq.: Inversion charge cannot respond, cannot respond, 1 1 4 2 C C kT N n q N ox a i si a min ln( / )

Inversion, low freq., or connected to a reservoir: where 1 1 1 C C_ox C_d C_i d Q( ) Q

is the inv. layer cap.

C d Q d Q kT q i i s i ( ) / 2 1 1 1 2 C C kT q V ox _{g s} / Like accumulation,

Effect of Gate Work Function

V

V

V

V

Q

C

t fb B ox fb B d ox

2

2

Q

Vacuum level Vacuum l l ox ox s m fb

C

Q

V

(

)

g

E

level level Ec = 4.10 eV 0.95 eV = 4.05 eV q q m q s s g B

q

2

Ec Ev 8-9 eV Metal (aluminum) Silicon 1.12 eV Eg q B _EEi f E_{f m}

(n

poly)

( id

)

E

_g Ev Silicon (p-type)

poly)

(p

E

_g m

(midgap)

2q

g m dioxide m

q

(p

p y)

Effect of Gate Work Function

Example: n+ _{polysilicon gate on p-type silicon}

ms g B a i E q kT q N n 2 0 56. ln q ms Vg V fb ms Vg 0 B _{q ms} Ec Ev Ei Ec Ev Ei E_{f E} f E_f E_f oxide p-type silicon n+ poly

n+ poly p-type silicon

oxide oxide

Poly-Si Gate Depletion Effect

p-type silicon Oxide

n+ poly

Q

Gate eq. becomes:

Ec E Vox s

V

V

Q

C

g fb s p s ox and, Ei Ev Ec Vg p E_f E_f

1

1

1

1

C

C

_ox

C

_si

C

_p Ei Ev p f 0.6 0.8 1

C

0 0.2 0.4

C

inv Typically, t_inv is 0.8-1.0 nm thicker than t -2 -1 0 1 2 0 thicker than t_ox.

Gated-Diode: MOS + p-n Junction

Zero-bias on the p-n junction (equilibrium):

The electron quasi-Fermi level in the MOS is the same as the Fermi level of the p-type Si

the Fermi level of the p-type Si.

Gated-Diode: Reverse Biased

(N

ilib i

)

MOS under Nonequilibrium

For a p-n junction reverse-biased at a voltage V

_R

,

the electron concentration on the p-side of the

p

junction is

, V

_R

<V

_R kT qV i

e

R

N

n

n

/' 2

If a gate voltage is applied to bend the p-type

bands by

_s

, the electron concentration at the

f

i

a

N

surface is

kT qV kT q a i

e

s

e

R

N

n

n

/ /' 2

As

_s

2

_B

, V

_R

V

_R

. For surface inversion to

occur, i.e., n = N

_a

, Need

inv

V

(

)

2

MOS under Nonequilibrium

V 2 ( 2 ) W V qN dm si R B a 2 ( 2 )