Siemens Simatic S 7 300 - 400 -Statement List for S7-300 and S7-400

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Preface, Contents

Product Overview

1

Structure and Components of

Instructions and Statements

2

Adressing

3

Accumulator Operations and

Address Register Instructions

4

Bit Logic Instructions

5

Timer Instructions

6

Counter Instructions

7

Load and Transfer Instructions

8

Integer Math Instructions

9

Floating-Point Math Instructions

10

Comparison Instructions

11

Conversion Instructions

12

Word Logic Instructions

13

Shift and Rotate Instructions

14

Data Block Instructions

15

Jump Instructions

16

17

Statement List (STL)

for S7-300 and S7-400

Programming

Reference manual

This reference manual is part of the documentation package with the order number

6ES7810-4CA04-8BR0

SIMATIC S7

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Note the following:

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WarningThis device and its components may only be used for the applications described in the catalog or the technical description, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens.

This product can only function correctly and safely if it is transported, stored, set up, and installed correctly, and operated and maintained as recommended.

SIMATIC, SIMATIC HMI and SIMATIC NET are registered trademarks of SIEMENS AG. Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners.

We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed.

 Siemens AG 1998

Technical data subject to change.

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Preface

This manual is your guide to creating user programs in the Statement List programming languageSTL.

The manual also includes a reference section that describes the syntax and functions of the language elements of STL.

This manual is intended for S7 programmers, operators, and

maintenance/service personnel. A working knowledge of automation procedures is essential.

This manual is valid for release 5.0 of the STEP 7 programming software package.

STL corresponds to the “Instruction List” language defined in the

International Electrotechnical Commission’s standard IEC 1131-3, although there are substantial differences with regard to the operations. For further details, refer to the table of standards in the STEP 7 file NORM_TBL.WRI.

Purpose Audience Scope of the Manual Compliance with Standards

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To use this Statement List manual effectively, you should already be familiar with the theory behind S7 programs which is documented in the online help for STEP 7. The language packages also use the STEP 7 standard software, so you should be familiar with handling this software and have read the accompanying documentation.

Documentation Purpose Order Number

STEP 7 Basic Information with

 Working with STEP 7 V5.0, Getting Started Manual

 Programming with STEP 7 V5.0

 Configuring Hardware and Communication Connections, STEP 7 V5.0

 From S5 to S7, Converter Manual

Basic information for technical per-sonnel describing the methods of im-plementing control tasks with STEP 7 and the S7-300/400 pro-grammable controllers.

6ES7810-4CA04-8BA0

STEP 7 Reference with

 Ladder Logic (LAD)/Function Block Dia-gram (FBD)/Statement List (STL) for S7-300/400 manuals

 Standard and System Functions for S7-300/400

Provides reference information and describes the programming langua-ges LAD, FBD and STL and stan-dard and system functions extending the scope of the STEP 7 basic infor-mation.

6ES7810-4CA04-8BR0

Online Helps Purpose Order Number

Help on STEP 7 Basic information on programming and configuraing hardware with STEP 7 in the form of an online help.

Part of the STEP 7 Stan-dard software.

Reference helps on STL/LAD/FBD Reference help on SFBs/SFCs Reference help on Organization Blocks

Context-sensitive reference informa-tion.

Part of the STEP 7 Stan-dard software.

You can display the online help in the following ways:

 Context-sensitive help about the selected object with the menu command

Help > Context-Sensitive Help, with the F1 function key, or by clicking

the question mark symbol in the toolbar.

 Help on STEP 7 via the menu command Help > Contents.

References to other documentation are indicated by reference numbers in slashes /.../. Using these numbers, you can check the exact title in the References section at the end of the manual.

Requirements

Accessing the Online Help

References

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The SIMATIC Customer Support team offers you substantial additional information about SIMATIC products via its online services:

 General current information can be obtained: – on the Internet under

http://www.ad.siemens.de/simatic/html_00/simatic

via the Fax-Polling number 08765-93 02 77 95 00

 Current product information leaflets and downloads which you may find useful are available:

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If you have other questions, please contact the Siemens representative in your area. The addresses are listed, for example, in catalogs and in Compuserve (go autforum).

Our SIMATIC Basic Hotline is also ready to help:  in Nuremberg, Germany

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The SIMATIC Premium Hotline is available round the clock worldwide with the SIMATIC card (telephone: +49 (911) 895-7777).

SIMATIC Customer Support Online Services Additional Assistance Preface

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To help us to provide the best possible documentation for you and future STEP 7 users, we need your support. If you have any comments or suggestions relating to this manual or the online help, please complete the questionnaire at the end of the manual and send it to the address shown. Please include your own personal rating of the documentation.

Questionnaires on the Manual and Online Help

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Contents

Preface . . . iii 1 Product Overview . . . 1-1 2 Structure and Components of Instructions and Statements . . . 2-1

2.1 Structure of a Statement . . . 2-2 2.2 Meaning of the CPU Register in Statements . . . 2-10

3 Addressing . . . 3-1

3.1 Immediate Addressing . . . 3-2 3.2 Direct Addressing . . . 3-2 3.3 Memory Indirect Addressing . . . 3-3 3.4 Address Registers . . . 3-6 3.5 Area-Internal Register Indirect Addressing . . . 3-7 3.6 Area-Crossing Register Indirect Addressing . . . 3-11

4 Accumulator Operations and Address Register Instructions. . . 4-1

4.1 Overview . . . 4-2 4.2 ENT and LEAVE . . . 4-3 4.3 Incrementing and Decrementing . . . 4-6 4.4 +AR1 und +AR2: Adding a Constant to Address Register 1

or Address Register 2 . . . 4-7

5 Bit Logic Instructions . . . 5-1

5.1 Boolean Bit Logic . . . 5-2 5.2 Bit Logic Instructions and Relay Coil Circuit. . . 5-6 5.3 Evaluating Conditions Using And, Or, and Exclusive Or . . . 5-10 5.4 Nesting Expressions and And before Or . . . 5-14

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6 Timer Instructions . . . 6-1

6.1 Overview . . . 6-2 6.2 Location of a Timer in Memory and Components of a Timer . . . 6-3 6.3 Loading, Starting, Resetting, and Enabling a Timer . . . 6-5 6.4 Timer Examples . . . 6-7 6.5 Address Locations and Ranges for Timer Instructions. . . 6-17 6.6 Choosing the Right Timer . . . 6-18

7 Counter Instructions. . . 7-1

7.1 Overview . . . 7-2 7.2 Setting, Resetting, and Enabling a Counter . . . 7-3 7.3 Couting Up and Counting Down. . . 7-5 7.4 Loading a Count Value as Integer . . . 7-6 7.5 Loading a Count Value in Binary Coded Decimal Format . . . 7-7 7.6 Counter Example . . . 7-8 7.7 Address Locations and Ranges for Counter Instructions. . . 7-10

8 Load and Transfer Instructions . . . 8-1

8.1 Overview . . . 8-2 8.2 Loading and Transferring . . . 8-3 8.3 Reading the Status Word or Transferring to the Status Word. . . 8-6 8.4 Loading Times and Counts as Integers . . . 8-7 8.5 Loading Times and Counts in Binary Coded Decimal Format . . . 8-9 8.6 Loading and Transferring between Address Registers . . . 8-11 8.7 Loading Data Block Information . . . 8-12

9 Integer Math Instructions . . . 9-1

9.1 Four-Function Math . . . 9-2 9.2 Adding an Integer to Accumulator 1 . . . 9-6

10 Floating-Point Math Instructions. . . 10-1

10.1 Four-Function Math . . . 10-2 10.2 Forming the Absolute Value of a Floating-Point Number. . . 10-6 10.3 Extended Math Instructions. . . 10-7 10.4 Forming the Square / Square Root of a Floating-Point Number. . . 10-9 10.5 Forming the Natural Logarithm of a Floating-Point Number . . . 10-11 10.6 Forming the Exponential Value of a Floating-Point Number . . . 10-12 10.7 Forming Trigonometric Functions on Angles Acting as

Floating-Point Numbers . . . 10-13 Contents

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11 Comparison Instructions. . . 11-1

11.1 Overview . . . 11-2 11.2 Comparing Two Integers . . . 11-3 11.3 Comparing Two Floating-Point Numbers . . . 11-5

12 Conversion Instructions . . . 12-1

12.1 Converting Binary Coded Decimal Numbers and Integers . . . 12-2 12.2 Converting 32-Bit Floating-Point Numbers to 32-Bit Integers . . . 12-8 12.3 Reversing the Order of Bytes within Accumulator 1 . . . 12-13 12.4 Forming Complements and Negating Floating-Point Numbers . . . 12-14

13 Word Logic Instructions . . . 13-1

13.1 Overview . . . 13-2 13.2 16-Bit Word Logic Instructions . . . 13-3 13.3 32-Bit Word Logic Instructions . . . 13-6

14 Shift and Rotate Instructions . . . 14-1

14.1 Shift Instructions . . . 14-2 14.2 Rotate Instructions . . . 14-6

15 Data Block Instructions . . . 15-1

15.1 Opening Data Blocks . . . 15-2 15.2 Swapping Data Block Registers. . . 15-2 15.3 Loading Data Block Lengths and Numbers . . . 15-3

16 Jump Instructions . . . 16-1

16.1 Overview . . . 16-2 16.2 Unconditional Jump Instructions . . . 16-3 16.3 Conditional Jump Instructions Founded on Result of Logic Operation . . . 16-4 16.4 Conditional Jump Instructions Founded on BR, OV, or OS Bits

of the Status Word . . . 16-5 16.5 Conditional Jump Instructions Based on Result in the CC 1 and

CC 0 Bits of the Status Word . . . 16-6 16.6 Loop Control . . . 16-8

17 Program Control Instructions . . . 17-1

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A Alphabetical Listing of Instructions . . . A-1

A.1 Listing with (German) SIMATIC and International Mnemonics . . . A-2 A.2 Alphabetical Listing with International Names . . . A-12

B Programming Examples . . . B-1

B.1 Overview . . . B-2 B.2 Bit Logic Instructions . . . B-3 B.3 Timer Instructions . . . B-7 B.4 Counter and Comparison Instructions. . . B-10 B.5 Integer Math Instructions. . . B-12 B.6 Word Logic Instructions . . . B-14

C Source Files - Examples and Reserved Keywords . . . C-1 D References. . . D-1 Glossary. . . Glossary-1 Index . . . Index-1

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Product Overview

Statement List (STL) is a textual programming language that can be used to create the code section of logic blocks. Its syntax for statements is similar to assembler language and consists of instructions followed by addresses on which the instructions act.

Of all the programming languages with which you can program S7

controllers, STL is the closest to the machine code MC7 of the S7 CPU. This means that by using it to program S7 controllers, you can optimize the run time and the use of memory.

The programming language STL has all the necessary elements for creating a complete user program. It contains a comprehensive range of instructions. A total of over 130 different basic instructions and a wide range of addresses are available. Functions and function blocks allow you to structure your STL program clearly.

The STL programming package is an integral part of the STEP 7 Standard Software. This means that following the installation of your STEP 7

software, all the editor functions, compiler functions and test/debug functions for STL are available to you.

Using STL, you can create your own user program as follows:

 With the Incremental Editor. The input of the local data structure is made easier with the help of table editors.

 With a source file in the Text Editor. Text input is made easier with the help of block templates.

There are three programming languages in the standard software, STL, FBD, and LAD. You can switch from one language to the other almost without restriction and choose the most suitable language for the particular block you are programming. What is Statement List? The Programming Language STL The Programming Package

1

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Structure and Components of

Instructions and Statements

Section Description Page

2.1 Structure of a Statement 2-2

2.2 Meaning of the CPU Register in Statements 2-10

Chapter Overview

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2.1

Structure of a Statement

With reference to structure, an instruction statement belongs to either one of the following two basic groups (see also Figure 2-1):

 A statement made up of an instruction alone (for example, NOT, see Section 5.9)

 A statement made up of an instruction and an address (see Tables 2-1 through 2-5, and Table 2-9)

Statement group 1

Instruction + address Instruction alone

Statement group 2

Figure 2-1 Basic Groups of Statements

The address of an instruction indicates a constant or the location where the instruction finds a value (data object) on which to perform an operation. The address can have a symbolic name or an absolute designation. The address can point to any of the following items (see also Tables 2-1 through 2-9):  A constant, the value of a timer or counter, or an ASCII character string

to be loaded into accumulator 1 (for example, L +27, see Table 2-1)  A bit in the status word of the programmable logic controller (for

example, A UO, see Table 2-2)

 A symbolic name (for example, A Motor.On, see Table 2-3)  A data block and a location within the data block area (for example,

L DB4.DBD10, see Table 2-4)

 A function (FC), function block (FB), integrated system function (SFC), or integrated system function block (SFB) and the number of the function or block (see Table 2-5)

 An address identifier and a location within the memory area that is indicated by the address identifier (for example, A I 1.0, or A I [AR1,P#4.3], see Table 2-9)

Tables 2-1 through 2-9 show various statements that each include an instruction with an address.

Components of a Statement

Address of an Instruction

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Table 2-1 shows how you can use a constant value as the address of an instruction.

Table 2-1 Addresses That Point to a Value or Character String

Statement

D i i Instruction Address Description

Constant

L +27 Load the integer 27 into accumulator 1.

L ’END’ Load the ASCII characters ’END’ into accumulator 1.

The address of a statement list instruction can refer to one or more bits in the status word of the programmable logic controller (see Section 2.2). The instruction checks and reacts to the signal state of a single bit in the status word (for example, A BR) or interprets the bit combination in two of the bits (for example, A UO).

Table 2-2 Addresses That Refer to a Bit in the Status Word

Statement

Instruction Address Description Bit in the Status

Word

A BR The 1 or 0 in bit 8 of the status word is included in a Boolean logic combination.

A UO The instruction interprets the bit combination that it finds in bits CC 1 and CC 0 of the status word to see if a certain condition has been fulfilled. For example, a combination of 1 and 1 indicates “unordered,” that is, one of the values in a floating-point operation was not a valid floating-point number.

Constant Values

Locations in the Status Word

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Table 2-3 shows how you use a symbolic name as the address of an instruction. You can only use symbolic names inSTL statements once you have declared them: shared symbolic names should be entered in the symbol table and local names in a block.

Table 2-3 Addresses That Point to a Symbolic Name

Statement

D i i Instruction Address Description

Symbol

A Motor.On Perform an And logic operation on the bit whose symbolic name is “Motor.On”. In this case, the symbolic name “Motor.On” can only represent a bit in the data block (D) area of memory or element of a structure “MOTOR” .

L SPEED Load the byte, word, or double word value, whose symbolic name is SPEED, into accumulator 1 .

Table 2-4 shows how you use a data block and a location within the data block as the address of an instruction.

Table 2-4 Addresses That Point to a Data Block and a Location within the Data Block

Statement Instruction Address

Description Data Block and

Location

Descr pt on

L DB4.DBD10 Load data double word DBD10 from data block DB4 into accumulator 1.

A DB10.DBX4.3 Perform an And logic operation on data bit DBX4.3 from data block DB10.

Symbolic Name

A Data Block and a Location within the Data Block

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Table 2-5 shows how you use a function (FC), function block (FB),

integrated system function (SFC), or integrated system function block (SFB) and the number of the function or block as the address of an instruction.

Table 2-5 Addresses That Point to a Function, Function Block, System Function, or System Function Block

Statement Instruction Address D i ti FC, FB, SFC, SFB and Number Description

CALL FB10, DB10 Call function block FB10 with instance data block DB10.

CALL SFC43 Call integrated system function SFC43.

Some addresses include an address identifier and a location within the memory area indicated by the address identifier. An address identifier can be one of the following three basic types (see Tables 2-6 through 2-8):

 An address identifier that indicates the memory area and the size of a data object in that area as follows (see Table 2-6):

– The memory area in which an instruction finds a value (data object) on which to perform an operation (for example, “I” for the process image input area of memory)

– The size of the value (data object) on which the instruction is to perform its operation (for example, B for “byte,” W for “word,” and D for “double word”)

 An address identifier that indicates a memory area but no size of a data object in that area (for example, an identifier that indicates the area T for “timer,” C for “counter,” or DB or DI for “data block,” plus the number of that timer, counter, or data block, see Table 2-7)

 An address identifier that indicates the size of a data object but no memory area. The memory area is encoded in the memory location that follows the address identifier (see Table 2-8).

FCs, FBs, SFCs, and SFBs

Address Identifiers

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Table 2-6 Address Identifier That Indicates Memory Area and Size of Data Object

Type of Addressing Instruction Address Identifier Memory Location Memory Area Size of Data Object (If no

size is indicated, a bit is implied.)

Direct A I 0.0

Direct L I B 10

Memory indirect A I [MD2]

Memory indirect L I B [DID4]

Area-internal register indirect A I [AR1, P#4.3] Area-internal register indirect T L D [AR2, P#53.0]

Table 2-7 Address Identifier That Indicates Memory Area, but No Size of Data Object

Type of Addressing Instruction Address Identifier: Memory Area Number or Location of Number Direct OPN DB 5 Direct SP T 7

Memory indirect OPN DB [LW2]

Memory Indirect S C [MW44]

Table 2-8 Address Identifier That Indicates Size of Data Object, but No Memory Area

Type of Addressing Instruction Size of Data Object (If no size is indicated, a bit is

implied.) Memory Location Area-crossing register indirect A [AR1, P#4.3] Area-crossing register indirect L B [AR1, P#100.0]

Table 2-9 Addresses That Include Address Identifier and Location

Statement Instruction Address D i ti Address Identifier Location in Memory Area or Register Description

A I 1.0 Perform an And logic operation on input bit 1.0.

A I [MD2] Perform an And logic operation on the input bit whose exact location is in memory double word MD2.

L C 1 Load the count value of counter 1 into accumulator 1.

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If you are working with an instruction whose address identifier indicates a memory area of your programmable logic controller and a data object that is either a word or a double word in size (see Table 2-6), you need to be aware of the fact that the memory location is always referenced as a byte location. This byte location is the number of the most significant byte within the word or double word. For example, the address in the statement shown in

Figure 2-2 references four successive bytes in memory area M, starting at byte 10 (MB10) and going through byte 13 (MB13).

Statement: L MD10

Address identifier Byte location

Figure 2-2 Example of Memory Location Referenced as Byte Location

Figure 2-3 illustrates data objects of the following sizes:  Double word: memory double word MD10

 Word: memory words MW10, MW11, and MW13  Byte: memory bytes MB10, MB11, MB12, and MB13

When you use absolute addresses that are a word or a double word in width, make sure that you do not create any byte assignments that overlap.

MB10 MB11 MB12 MB13 MW11 MD10 MW10 MW12 15 015 0 1615 0 31 MSB LSB

Figure 2-3 Referencing a Memory Location as a Byte Location

Most addresses inSTL refer to memory areas. The following table lists the memory areas and describes the function of each area.

Working with Word or Double Word as Data Object

Memory Areas and their Functions

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Table 2-10 Memory Areas and Their Functions

Name of Area Function of Area Access to Area Name of Area Funct on of Area

via Units of the Following Size: Abbrev. Process image

input

At the beginning of the scan cycle, the operating system reads the inputs from the process and records the values in this area. The program can use these values in its cyclic processing.

Input bit Input byte Input word Input double word

I IB IW ID Process image output

During the scan cycle, the program calculates output values and places them in this area. At the end of the scan cycle, the operating system reads the calculated output values from this area and sends them to the process outputs.

Output bit Output byte Output word Output double word

Q QB QW QD

Bit memory This area provides storage for interim results calculated in the program.

Memory bit Memory byte Memory word Memory double word

M MB MW MD I/O: external input

This area enables your program to have direct access to input and output modules (that is, peripheral inputs and outputs).

Peripheral input byte Peripheral input word Peripheral input double word

PIB PIW PID I/O:

external output

Peripheral output byte Peripheral output word Peripheral output double word

PQB PQW PQD Timer Timers are function elements of STL

programming. This area provides storage for timer cells. In this area, clock timing accesses time cells to update them by decrementing the time value and timer instructions access time cells.

Timer (T) T

Counter Counters are function elements of STL programming. This area provides storage for counters. Counter instructions access them here.

Counter (C) C

Data block This area contains data that can be accessed from any block. If you need to have two different data blocks open at the same time, you can open one with the statement “OPN DB” and one with the statement “OPN DI”. In this way, the CPU can distinguish which of the two data blocks your program wants to access while both data blocks are open.

Data block opened with the statement “OPN DB”:

Data bit Data byte Data word Data double word

DBX DBB DBW DBD are open.

While you can use the “OPN DI” statement to open any data block, the principal use of this statement is to open instance data blocks that are associated with function blocks (FBs) and system function blocks (SFBs). For more information on FBs, SFBs, and instance data blocks, see the

STEP 7 Online Help.

Data block opened with the statement “OPN DI”:

Data bit Data byte Data word Data double word

DIX DIB DIW DID Local data This area contains temporary data that is used

within a logic block (OB, FB, or FC). These data are also called dynamic local data. They serve as an intermediate buffer. When the logic block is finished, these data are lost. The data are contained in the local data stack (L stack).

Temporary local data bit Temporary local data byte Temporary local data word Temporary local data double word

L LB LW LD

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Table 2-11 lists the maximum address ranges for various memory areas. For the address range possible with your CPU, refer to the technical data of the CPU. For an explanation of the functions of the memory areas, see Table 2-10.

Table 2-11 Memory Areas and Their Address Ranges

Name of Area

Access to Area

M i Add R Name of Area

via Units of the Following Size: Abbrev. Maximum Address Range Process image input Input bit

Input byte Input word Input double word

I IB IW ID 0.0 to 65,535.7 0 to 65,535 0 to 65,534 0 to 65,532 Process image output Output bit Output byte Output word Output double word

Q QB QW QD 0.0 to 65,535.7 0 to 65,535 0 to 65,534 0 to 65,532 Bit memory Memory bit

Memory byte Memory word Memory double Word

M MB MW MD 0.0 to 255.7 0 to 255 0 to 254 0 to 252 I/O: external input

Peripheral input byte Peripheral input word Peripheral input double word

PIB PIW PID 0 to 65,535 0 to 65,534 0 to 65,532 I/O: external output

Peripheral output byte Peripheral output word Peripheral output double word

PQB PQW PQD 0 to 65,535 0 to 65,534 0 to 65,532 Timer Timer (T) T 0 to 255 Counter Counter (C) C 0 to 255

Data block Data block opened with the statement “OPN DB”: Data bit

Data byte Data word Data double word

DBX DBB DBW DBD 0.0 to 65,535.7 0 to 65,535 0 to 65, 534 0 to 65,532 Data block opened with the statement “OPN DI”:

Data bit Data byte Data word Data double word

DIX DIB DIW DID 0.0 to 65,535.7 0 to 65,535 0 to 65, 534 0 to 65,532

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2.2

Meaning of the CPU Register in Statements

The two 32-bit accumulators are general purpose registers that you use to process bytes, words, and double words. You can load constants or values from the memory as addresses into the accumulator and perform logic operations on them. You can also transfer the result of an operation from accumulator 1 to a memory location. Figure 2-4 identifies the areas of an accumulator.

The stack mechanism for accumulator administration is as follows:  A load instruction always acts on accumulator 1 and saves the old

contents to accumulator 2.

 A transfer instruction does not change the accumulators (with the exception of instructions TAR1 and TAR2).

 The TAK instruction swaps the contents of accumulators 1 and 2. For information on accumulator administration for math instructions, see Section 9.1. 0 7 8 15 16 23 24 31

Accumulator (1 or 2) Low word High word

Low byte High byte

Low byte High byte

Figure 2-4 Areas of an Accumulator

The nesting stack is a storage area that is one byte wide. This storage area is used by the nesting instructions A(, O(, X(, AN(, ON(, XN(. These

instructions save the current result of logic operation (RLO) to the nesting stack and start a new logic string.

The nesting stack can accommodate seven entries. A nesting stack entry consists of the RLO, BR, and OR bits of the status word, and a function code to indicate which of the Boolean logic operations is to be used (A, AN, O, ON, X, or XN).

The “)” instruction closes a nesting expression by performing the following functions:

 Fetches an entry from the nesting stack  Restores the OR and BR bits

 Defines the new RLO by logically combining the current RLO (that is, the RLO from the expression nested in parentheses) with the RLO of the stack entry according to the function code (see Section 5.4)

Accumulators

Nesting Stack

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Figure 2-5 shows the structure of an entry in the nesting stack. Below Figure 2-5 you can see an explanation of the bits in the nesting stack byte.

24

27 26 25 23 22 21 20

BR OR

0 0 RLO Function code

Figure 2-5 Structure of an Entry in the Nesting Stack

The nesting stack byte contains the following bits (see Figure 2-5):  Non-assigned bits (bits 7 and 6 with signal state “0”)

 The stored binary result (BR)

 The stored result of logic operation (RLO)  The stored OR bit in the functions A( and AN(

Zero is stored in all other functions  The function code (in bits 2, 1 and 0)

Function code

With the help of the function code, the instruction “)” defines the function which is to be used for the combination of the current RLO (that is the RLO from the expression nested in parentheses) with the RLO of the nesting stack entry. Table 2-12 shows the bit combinations of the function code for each function type:

Table 2-12 Function Codes of Nesting Stack Byte

Instruction Function Code 2 Function Code 1 Function Code 0

A( 0 0 0 AN( 0 0 1 O( 0 1 0 ON( 0 1 1 X( 1 0 0 XN( 1 0 1

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Nesting Stack with Entries and Pointer

The nesting stack and the nesting stack pointer must be stored either in the interrupt stack or they must be fetched from it, when the batches change. The number in the nesting stack pointer indicates the number of entries available in the nesting stack (see Figure 2-6).

15 7 0

Rising addresses Nesting stack pointer

Nesting stack entry 7 Nesting stack entry 5 Nesting stack entry 3 Nesting stack entry 1

Nesting stack entry 6 Nesting stack entry 4 Nesting stack entry 2

Figure 2-6 Structure of a Nesting Stack with Entries and Pointer

The status word contains bits that you can reference in the address of bit logic and word logic instructions. Figure 2-7 shows the structure of the status word. The sections that follow the figure explain the significance of bits 0 through 8.

28

215... ...29 27 26 25 24 23 22 21 20

BR CC 1 CC 0 OV OS OR STA RLO FC

Figure 2-7 Structure of the Status Word

Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-8). The signal state of 0 in the FC bit indicates that, following this point in your program, the next logic instruction begins a new logic string. (The bar over the FC indicates that it is negated.)

Each logic instruction checks the signal state of the FC bit as well as the signal state of the location it addresses. If the FC bit is 0, the instruction stores the result of the signal state check in the result of logic operation bit of the status word (RLO bit, see next section) and sets the FC bit to 1. This process is called a first check (see Figure 2-8 and Section 5.6).

If the signal state of the FC bit is equal to 1, an instruction combines the result of its signal state check on the contact it addresses with the value stored in the previous RLO bit (see Figure 2-8).

A string of logic instructions always ends with an output instruction (S, R, or =, see Sections 5.7 and 5.8), a jump instruction related to the result of logic operation (JC, see Section 16), or one of the nesting instructions A(, O(, X(, AN(, ON(, or XN( (see Section 5.4). Such an output, jump instruction, or nesting instruction resets the FC bit to 0 (see Figure 2-8).

Status Word

First Check

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Bit 1 of the status word is called the RLO bit (RLO stands for “result of logic operation,” see Figure 2-7). This bit stores the result of a bit logic instruction or math comparison.

For example, the second instruction in a string of bit logic instructions checks the signal state of a contact and produces a result of 1 or 0. Then the

instruction combines this result with the value stored in the RLO bit of the status word according to the principles of Boolean logic (see First Check above and Chapter 5). The result of this logic operation is stored in the RLO bit of the status word, replacing the former value in the RLO bit. Each subsequent instruction in the string performs a logic operation on two values: the result produced when the instruction checks the contact, and the current RLO.

You can set the RLO to 1 unconditionally by using the SET instruction; you can reset the RLO to 0 unconditionally by using the CLR instruction. You can use a Boolean bit logic instruction on a first check to assign the state of the contents of a Boolean bit memory location to the RLO. You can use the RLO to trigger jump instructions.

Result of check is combined with previous RLO according to AND truth table. FC bit remains 1. Statement List Program Signal State of Input (I) or Output (Q) A I 1.0 AN I 1.1 = Q 4.0 RLO Bit Result of Check

1 1 Result of first check is stored in

RLO bit. FC bit is set to 1.

0 1

1 RLO is assigned to output

coil. FC bit is reset to 0. 1 1 Explanation FC Bit 0 1 1 0

FC bit = 0 indicates that next instruction begins logic string

Figure 2-8 Effect of Signal State of FC Bit on Logic Instructions

The status bit (STA bit) stores the value of a bit that is referenced. The status of a bit instruction that has read access to the memory (A, AN, O, ON, X, XN) is always the same as the value of the bit that this instruction checks (the bit on which it performs its logic operation). The status of a bit instruction that has write access to the memory (S, R, =) is the same as the value of the

Result of Logic Operation

Status Bit

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The OR bit is needed if you use the O instruction to perform a logical AND before OR operation. An AND function may contain the following

instructions: A, AN A(, AN(, ), and NOT. The OR bit shows these instructions that a previously executed AND function has supplied the value 1, thus forestalling the result of the logical OR operation. Any other bit-processing command resets the OR bit (see Section 5.4).

The overflow bit (OV bit) indicates a fault. It is set by a math instruction or a floating-point comparison instruction after a fault occurs (overflow, illegal operation, illegal floating-point number). This bit is set according to the result of the next math instruction or comparison instruction.

The stored overflow bit (OS bit) is set together with the OV bit when a fault occurs. Because the OS bit remains set after the fault has been eliminated, it stores the OV bit status and indicates whether or not a fault occurred in one of the previously executed instructions. The following commands reset the OS bit: JOS (jump after stored overflow), the block call commands, and the block end commands.

The CC 1 and CC 0 bits (condition codes) provide information on the following results or bits:

 Result of a math operation  Result of a comparison  Result of a digital operation

 Bits that have been shifted out by a shift or rotate command

Tables 2-13 through 2-18 list the significance of CC 1 and CC 0 after your program executes certain instructions.

Table 2-13 CC 1 and CC 0 after Math Instructions, without Overflow

CC 1 CC 0 Explanation

0 0 Result = 0

0 1 Result < 0

1 0 Result > 0

Table 2-14 CC 1 and CC 0 after Integer Math Instructions, with Overflow

CC 1 CC 0 Explanation

0 0 Negative range overflow in +I and +D 0 1 Negative range overflow in I and D

Positive range overflow in +I, –I, +D, –D, NEGI, and NEGD 1 0 Positive range overflow in I, D, /I, and /D

Negative range overflow in +I, –I, +D, and –D 1 1 Division by 0 in /I, /D, and MOD

OR Bit Overflow Bit Stored Overflow Bit Condition Code 1 and Condition Code 0

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Table 2-15 CC 1 and CC 0 after Floating-Point Math Instructions, with Overflow

CC 1 CC 0 Explanation

0 0 Gradual underflow 0 1 Negative range overflow 1 0 Positive range overflow 1 1 Invalid floating-point number

Table 2-16 CC 1 and CC 0 after Comparison Instructions

CC 1 CC 0 Explanation

0 0 Accumulator 2 = accumulator 1 0 1 Accumulator 2 < accumulator 1 1 0 Accumulator 2 > accumulator 1

1 1 Accumulator 1 or accumulator 2 is an invalid floating-point number

Table 2-17 CC 1 and CC 0 after Shift and Rotate Instructions

CC 1 CC 0 Explanation

0 0 Last bit shifted out = 0 1 0 Last bit shifted out = 1

Table 2-18 CC 1 and CC 0 after Word Logic Instructions

CC 1 CC 0 Explanation

0 0 Result = 0

1 0 Result <> 0

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The binary result bit (BR bit) forms a link between the processing of bits and words. It is an efficient means of interpreting the result of a word operation as a binary result and integrates this result in a binary logic string. Viewed in this way, the BR bit represents a machine-internal memory bit to which the RLO is saved prior to a word operation that changes the RLO, so that the RLO will be available again after the operation to continue the interrupted bit string.

For example, the BR bit makes it possible for you to write a function block (FB) or a function (FC) in statement list (STL) and then call the FB or FC from ladder logic (LAD, see the Reference Manual /233/).

When writing a function block or function that you want to call from LAD, no matter whether you write the FB or FC in STL or LAD, you are responsible for managing the BR bit. The BR bit corresponds to the enable output (ENO) of a LAD box. You should use the SAVE instruction (in STL, see Section 5.9) or the –––(SAVE) coil (in LAD) to store an RLO in the BR bit according to the following criteria:

 Store an RLO of 1 in the BR bit for a case where the FB or FC is executed without error.

 Store an RLO of 0 in the BR bit for a case where the FB or FC is executed with error

You should program these instructions at the end of the FB or FC so that these are the last instructions that are executed in the block.

When you call a system function block (SFB) or a system function (SFC) in your program, the SFB or SFC indicates whether the CPU was able to execute the function with or without errors by providing the following information in the binary result bit:

 If an error occurred during execution, the BR bit is 0.  If the function was executed with no error, the BR bit is 1.

Binary Result Bit

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Addressing

Section Description Page

3.1 Immediate Addressing 3-2

3.2 Direct Addressing 3-2

3.3 Memory Indirect Addressing 3-3

3.4 Address Registers 3-6

3.5 Area-Internal Register Indirect Addressing 3-7 3.6 Area-Crossing Register Indirect Addressing 3-11

Chapter Overview

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3.1

Immediate Addressing

With immediate addressing, the address is coded directly in the instruction; that is, it directly follows the value with which the instruction is to work (for example, Load). An instruction can also provide its own value (for example, SET, see Table 3-1).

Table 3-1 Immediate Addressing

Example Description

SET Set the RLO to 1. OW W#16#A320 Or Word.

L 27 Load the integer value 27 into accumulator 1. L ’ABCD’ Load the ASCII characters ABCD into accumulator 1. L B#(100,12) Load the two bytes 100 and 12 into accumulator 1. L C#0100 Load the BCD value 0000 into accumulator 1.

3.2

Direct Addressing

An instruction that uses direct addressing has the following two-part address that indicates the location of the value that the instruction is going to process:  An address identifier (for example, “IB” for “input byte”)

 An exact location within the memory area that is indicated by the address identifier

The address points directly to the location of the value.

Table 3-2 Direct Addressing

Example Description

A I 0.0 Perform an AND logic operation on input bit I 0.0. S L 20.0 Set the local data bit L 20.0.

= M 115.4 Assign the RLO to memory bit M 115.4 L IB0 Load input byte IB0 into accumulator 1. L MW64 Load memory word MW64 into accumulator 1. T DBD12 Transfer the contents from accumulator 1 into data

double word DBD12. Description Examples Description Examples Addressing

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3.3

Memory Indirect Addressing

An instruction that uses memory indirect addressing has the following two-part address that indicates the location of the value that the instruction is going to process:

 An address identifier (for example, “IB” for “input byte”)  One of the following pointers:

– A word that contains the number of a timer (T), counter (C), data block (DB), function (FC), or function block (FB)

– A double word that contains the exact location of a value within the memory area that is indicated by the address identifier

The address indicates the location of the value or number indirectly via the pointer. This word or double word can be in one of the following areas:  Bit memory (M)

 Data block (DB)  Instance data block (DI)  Local data (L)

The advantage of memory indirect addressing is that you can modify the statement address dynamically during program execution.

When working with a memory indirect address that is stored in the data block area of memory, first you must open the data block by using the Open a Data Block (OPN) instruction. Then you can use the data word or data double word as an indirect address, as shown in the following example:

OPN DB10 L IB [DBD20]

Table 3-3 Memory Indirect Addressing

Example Description

A I [MD2] or

A I [anna]

Perform an And logic operation on the input bit whose exact location is in memory double word MD2 or in the location designated by “anna” in the symbol table, as a reference to MD2.

Description

Using the Right Syntax

Examples

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There are two possible pointer formats: word and double word. The abbreviation for a pointer in word format ends in W (for example, DBW). Figure 3-1 shows the pointer format for a word. The abbreviation for a double word format ends in D (for example, DBD). Figure 3-2 shows the pointer format for a double word.

15.. ..8 7.. ..0

n n n n n n n n

Bits 0 to 15 (nnnn nnnn nnnn nnnn): number (range 0 to 65,535) of a timer (T), counter (C), data block (DB), function (FC), or function block (FB)

n n n n n n n n

Figure 3-1 Word Pointer Format for Memory Indirect Addressing

The following two examples show how to work with the word pointer format:

STL Explanation

L +5

T MW2

OPN DB[MW2]

Load the value 5 as an integer into accumulator 1.

Transfer the contents of accumulator 1 to memory word MW2. Open data block 5.

STL Explanation

OPN DB10

L +20

T DBW10

A T[DBW10]

Open data block DB10.

Load the value 20 as an integer into accumulator 1. Transfer the contents of accumulator 1 to data word DBW10 Check the signal state of timer T 20.

Pointer Format

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31.. ..24 23.. ..16 15.. ..8 7.. ..0 0 0 0 0 0 0 0 0 0 0 0 0 0 b b b b b b b b b b b b b b b b x x x Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of the addressed byte

Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit

Figure 3-2 Double Word Pointer Format for Memory Indirect Addressing

Note

If you access a byte, word, or double word, be sure that the bit number of your pointer is 0.

The following two examples show you how to work with the double word pointer format: STL Explanation L P#8.7 T MD2 A I [MD2] = Q [MD2]

Load 2#0000 0000 0000 0000 0000 0000 0100 0111 (binary value) into accumulator 1.

Store the exact location 8.7 in memory double word MD2. The controller checks input bit I 8.7 and assigns its signal state to output bit Q 8.7.

STL Explanation

L P#8.0 T MD2 L IB [MD2] T MW [MD2]

Load 2#0000 0000 0000 0000 0000 0000 0100 0000 (binary value) into accumulator 1.

Store the exact location 8 in memory double word MD2.

The controller loads input byte IB8 and transfers the contents to memory word MW8. The exact location 8 comes from memory double word MD2.

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3.4

Address Registers

Some types of indirect addressing in statement list programming require the use of certain registers in the CPU. These registers are described below.

Address registers 1 and 2 (AR1 and AR2) are 32-bit registers that accept an area-internal or area-crossing pointer for commands that use register-indirect addressing (see Sections 3.5 and 3.6).

Pointers are used in register-indirect addressing (see Sections 3.5 and 3.6). The following two types are available:

 Area-internal: used for area-internal access to bits, bytes, words, and double words in memory areas P, I, Q, M, DBX, DIX, and L

 Area-crossing: used for area-crossing access to bits, bytes, words, and double words in memory areas P, I, Q, M, DBX, DIX, and L

Explanation

Address Registers 1 and 2

Pointers

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3.5

Area-Internal Register Indirect Addressing

An instruction that uses area-internal register indirect addressing has the following two-part address that indicates the memory location of the value that the instruction is going to process:

 An address identifier (for example, “LD” for “local data double word,” see Table 2-6)

 An address register and a pointer to specify byte and bit. The byte and bit indicate an offset, which, when added to the contents of the register, indicate the memory location of the value that the instruction is to process.

The address points to the memory location of the value indirectly via the address register plus offset.

A statement that uses area-internal register indirect addressing does not change the value in the address register.

The address of an instruction points to the value that the instruction is going to process. Where area-internal register indirect addressing is concerned, the address points to the memory location of the value indirectly via the address register plus offset. Figure 3-3 shows how you calculate the memory location for the address of the Assign (=) instruction in the following statement:

= Q [AR1, P#1.1]

Contents of address register AR1: 8.7 byte 8, bit 7

Offset P#: 1.1 byte 1, bit 1

Memory location: output byte Q 10.0 bytes: 9, bits: 8 (= 1 byte) (9 bytes + 1 byte = 10 bytes) +

Byte Bit

Figure 3-3 Calculating the Memory Location of Output Q [AR1, P#1.1]

You calculate the memory location of the address by adding the byte portion

Description

Calculating the Memory Location of the Address

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Table 3-4 Area-Internal Register Indirect Addressing

Example Description

A I [AR1, P#4.3] Perform an And logic operation on the input bit whose memory location is calculated by the contents of address register AR1 plus 4 bytes, plus 3 bits. = DIX [AR2, P#0.0] Assign the RLO bit to the instance data bit whose

memory location is in address register AR2. L IB [AR1, P#100.0] Load the input byte whose memory location is

calculated by the contents of address register AR1 plus 100 bytes into accumulator 1.

T LD [AR2, P#56.0] Transfer the contents of accumulator 1 into local data double word LD whose memory location is calculated by the contents of address register AR2 plus 56 bytes. With reference to addressing local data, please read the Warning below.

!

WarningPossible overwriting of the data that is used by the compiler.

When you use absolute addressing to access temporary local data, there is no guarantee that there will be no conflict between the data used by the

compiler and the local data that you are attempting to access by means of absolute addressing. It is possible that you overwrite some of the data that the compiler uses. (For example, the compiler uses local data for transferring formal parameters.) Local data that the compiler needs are attached to the symbolic data that are defined by the person doing the programming.

When accessing temporary local data, you are advised to choose symbolic addressing over absolute addressing.

Examples

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Area-internal register indirect addressing has only one possible pointer format: double word. This double word contains an address encoded as a bit address. The abbreviation for a double word format ends in D (for example, DBD). Figure 3-4 shows the pointer format for a double word.

31.. ..24 23.. ..16 15.. ..8 7.. ..0

0 0 0 0 0 0 0 0 0 0 0 0 0 b b b b b b b b b b b b b b b b x x x

Bit 31 = 0 to indicate area-internal register indirect addressing

Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of the addressed bit

Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit

Figure 3-4 Double Word Pointer Format for Area-Internal Register Indirect Addressing

Note

If you access a byte, word, or double word, be sure that the bit number of your pointer is 0.

Pointer Format

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The following two examples show you how to work with the double word pointer format: STL Explanation L P#8.7 LAR1 A I [AR1, P#0.0] = Q [AR1, P#1.1]

Load a double word pointer to bit address location 8.7 into accumulator 1.

Store a double word pointer to bit address location 8.7 in address register AR1.

The CPU adds the offset (P#0.0) to the contents of address register AR1 (8.7) and uses this address as the location of an And bit logic instruction. The contents of AR1 remain

unchanged.

The CPU assigns the result of the And bit logic operation (RLO) to an address (Q 10.0). The CPU calculates this address by adding the contents of address register AR1 (8.7) and the offset (P#1.1). STL Explanation L P#8.0 LAR2 L IB [AR2, P#2.0] T MW [AR2, P#200.0]

Load a double word pointer to bit address location 8.0 into accumulator 1.

Store a double word pointer to bit address location 8.0 in address register AR2.

The CPU loads input byte IB10 into accumulator 1.

The CPU transfers the contents of accumulator 1 to memory word MW208.

The location 208 comes from 8 (AR2) plus 200 (offset), which is 208.

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3.6

Area-Crossing Register Indirect Addressing

An instruction that uses area-crossing register indirect addressing has the following two-part address that indicates the memory location of the value that the instruction is going to process:

 An address identifier that indicates the size of a data object (for example, “B” for “byte,” see Table 2-8). The memory area is indicated in bits 24, 25, and 26 of the address register.

 An address register and a pointer that indicate an offset which, when added to the contents of the address register, indicates the memory location of the value that is to be processed by the instruction. The pointer is indicated by P#byte.bit.

The address points to the memory location of the value indirectly via the address register plus offset.

A statement that uses area-crossing register indirect addressing does not change the value in the address register.

The address of an instruction points to the value that the instruction is going to process. Where area-crossing register indirect addressing is concerned, the address points to the memory location of the value indirectly via the address register plus offset. Figure 3-5 shows how you calculate the memory location for the address of the Assign (=) instruction in the following statement:

= [AR1, P#1.1]

Contents of address register AR1: 8.7 byte 8, bit 7

Offset P#: 1.1 byte 1, bit 1

Memory location: byte 10.0 bytes: 9, bits: 8 (= 1 byte) (9 bytes + 1 byte = 10 bytes) +

Byte Bit

Figure 3-5 Calculating the Address [AR1, P#1.1]

Description

Calculating the Memory Location of the Address

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Table 3-5 provides examples of area-crossing register indirect addressing. The address must contain an additional area identification in bits 24, 25, and 26 of the pointer. The addressed information is in the address register.

Table 3-5 Area-Crossing Register Indirect Addressing

Example Description

A [AR1, P#4.3] Perform an And logic operation on the bit whose memory location is calculated by the contents of address register AR1, plus 4 bytes plus 3 bits. The memory area of the bit is indicated in bits 24, 25, and 26 of address register AR1.

= [AR2, P#0.0] Assign the RLO bit to the bit whose memory location is in address register AR2. The memory area of the bit is indicated in bits 24, 25, and 26 of address register AR2.

L B [AR1, P#100.0] Load into accumulator 1 the byte whose memory location is calculated in address register AR1 plus 100 bytes. The memory area of the byte is indicated in bits 24, 25, and 26 of address register AR1. T D [AR2, P#56.0] Transfer the contents of accumulator 1 into the

double word whose memory location is calculated by the contents of address register AR2 plus 56 bytes. The memory area of the double word is indicated in bits 24, 25, and 26 of address register AR2.

Table 3-6 lists the binary code in bits 24, 25, and 26 of the pointer that identifies the area.

Table 3-6 Area Identification for Area-Crossing Register Indirect Addressing

Area Identification (Memory Area) Binary Contents of Bits 26, 25, and 24

P (I/O, external inputs and outputs) 000

I (process-image input) 001

Q (process-image output) 010

M (bit memory) 011

DBX (data block) 100

DIX (data block) 101

(previous local data, that is, the local data of the previous incompleted block)

111

Example

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Area-crossing register indirect addressing has only one possible pointer format: double word. The abbreviation for a double word format ends in D (for example, DBD). Figure 3-6 shows the pointer format for a double word.

31.. ..24 23.. ..16 15.. ..0

1 0 0 0 0 r r r 0 0 0 0 0 b b b b b b b b b b b b b b b b x x x

Bit 31 = 1 to indicate area-crossing register indirect addressing

Bits 24, 25, and 26 (rrr): area identification (memory area, see Table 3-6) Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of the addressed bit

Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit 3.. ..8 7..

Figure 3-6 Double Word Pointer Format for Area-Crossing Register Indirect Addressing

Note

If you access a byte, word, or double word, be sure that the bit number of your pointer is 0.

You cannot access local data using area-crossing register indirect addressing!

Pointer Format

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The following two examples show you how to work with the double word pointer format: STL Explanation L P#I 8.7 LAR1 L P#Q 8.7 LAR2 A [AR1, P#0.0] = [AR2, P#1.1]

Load a double word pointer to bit address location I 8.7 into accumulator 1.

Store a double word pointer to bit address location I 8.7 in address register AR1.

Load a double word pointer to bit address location Q 8.7 into accumulator 1.

Store a double word pointer to bit address location Q 8.7 in address register AR2.

The CPU adds the contents of address register AR1 (P#I 8.7) and the offset (P#0.0) and uses the address pointed to by the result (I 8.7) as the address of an And bit logic instruction. The contents of AR1 remain unchanged.

The CPU assigns the result of the And bit logic operation (RLO) to an address (Q 10.0). The CPU calculates this address by adding the contents of address register AR2 (P#Q 8.7) and the offset (P#1.1) and dereferencing the pointer. The contents of AR2 remain unchanged.

STL Explanation L P#I 8.0 LAR2 L P#M 8.0 LAR1 L B [AR2, P#2.0] T W [AR1, P#200.0]

Load a double word pointer to bit address location I 8.0 into accumulator 1.

Store a double word pointer to bit address location I 8.0 in address register AR2.

Load a double word pointer to bit address location M 8.0 into accumulator 1.

Store a double word pointer to bit address location M 8.0 in address register AR1.

The CPU loads input byte IB10.

The CPU transfers the contents to memory word MW208. Input byte 10 comes from 8 (AR2) plus 2 (offset).

Memory word 208 comes from 8 (AR1) plus 200 (offset), which is 208.

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Accumulator Operations and Address

Register Instructions

Section Description Page

4.1 Overview 4-2

4.2 ENT and LEAVE 4-3

4.3 Incrementing and Decrementing 4-6 4.4 +AR1 und +AR2: Adding a Constant to Address Register 1

or Address Register 2

4-7

Chapter Overview

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4.1

Overview

The following instructions are available to you for handling the contents of one or both accumulators:

Mnemonic Instruction Explanation

TAK Toggle Accumulator 1 with Accumulator 2

This instruction exchanges the contents of accumulator 1 with the contents of accumulator 2.

PUSH with 2 ACCUs

Accumulator 1 to Accumulator 2 This instruction copies the contents of accumulator 1 to accumulator 2.

POP

with 2 ACCUs

Accumulator 2 to Accumulator 1 This instruction copies the contents of accumulator 2 to accumulator 1.

PUSH with 4 ACCUs

Copy ACCU 3 to ACCU 4, ACCU 2 to ACCU 3, ACCU 1 to ACCU 2

This instruction copies the contents of accumulator 3 to accumulator 4, the contents of accumulator 2 to accumula-tor 3 and the contents of accumulaaccumula-tor 1 to accumulaaccumula-tor 2. POP

with 4 ACCUs

Copy ACCU 2 to ACCU 1, ACCU 3 to ACCU 2, ACCU 4 to ACCU 3

This instruction copies the contents of accumulator 2 to accumulator 1, the contents of accumulator 3 to accumula-tor 2 and the contents of accumulaaccumula-tor 4 to accumulaaccumula-tor 3. ENT Enter accumulator stack This instruction copies the contents of accumulator 3 to

accumulator 4 and the contents of accumulator 2 to accu-mulator 3.

LEAVE Leave accumulator stack This instruction copies the contents of accumulator 3 to accumulator 2 and the contents of accumulator 4 to accu-mulator 3.

INC Increment Accumulator 1 This instruction increases the contents of the low byte of the low word of accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255.

DEC Decrement Accumulator 1 This instruction decreases the contents of the low byte of the low word of accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255.

+AR1, +AR2 Add Accumulator 1 to Address Register

This instruction adds the contents of the low word of ac-cumulator 1 to address register 1 or 2.

+AR1 P#Byte.Bit, +AR2 P#Byte.Bit

Add Constant to Address Register

This instruction adds a constant to the contents of address register 1 or 2.

BLD Program Display Instruction ”This instruction does not carry out any function and does not influence the status bits. The instruction is only rele-vant to the programming device (PG) when a program is displayed. The address <number> is the ID of the instruc-tion BLD and is generated by the programming device.” NOP 0

NOP 1

Null Instruction 0 Null Instruction 1

”These instructions do not carry out any function, nor do they influence the contents of the status word. The instructions NOP 1 and NOP 0 are required for decompil-ing. The instruction code contains a bit pattern with either 16 zeroes or 16 ones.”

For information on reversing the order of bytes in accumulator 1, see Section 12.3.

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4.2

ENT and LEAVE

With the instructions ENT (Enter Accumulator Stack) and LEAVE (Leave Accumulator Stack) you can carry out the following functions:

 The instruction ENT copies the contents of Accumulator 3 to Accumulator 4 and the contents of Accumulator 2 to Accumulator 3. If you program the ENT instruction directly before a load instruction, it SHIFTS

Accumulator 2 and Accumulator 3 further in the stack.

 The instruction LEAVE copies the contents of Accumulator 3 to Accumulator 2 and the contents of Accumulator 4 to Accumulator 3. If you program the LEAVE instruction directly before a shift and rotate instruction, which combines accumulators, then the LEAVE instruction will function like a math operation.

Figure 4-1 shows how the ENT instruction works.

0 31 ACCU 3 ACCU 3 ACCU 4 ACCU 4 0 31 0 31 31 0 I II III IV V VI VII VIII V VI VII VIII ENT IX X XI XII 0 31 ACCU 1 ACCU 1 ACCU 2 ACCU 2 0 31 0 31 31 0 IX X XI XII

XIII XIV XV XVI XIII XIV XV XVI

IX X XI XII

Description

ENT

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Figure 4-2 shows how the LEAVE instruction works. 0 31 ACCU 3 ACCU 3 ACCU 4 ACCU 4 0 31 0 31 31 0 I II III IV V VI VII VIII 0 31 ACCU 1 ACCU 1 ACCU 2 ACCU 2 0 31 0 31 31 0 IX X XI XII

XIII XIV XV XVI

LEAVE

I II III IV

I II III IV

V VI VII VIII

XIII XIV XV XVI

Figure 4-2 Copying the contents of Accumulator 3 to Accumulator 2 and the contents of Accumulator 4 to Accumulator 3 in the LEAVE instruction

The following program extract shows the use of the ENT instruction. The floating points in the data double words DBD0 and DBD4 should be added together. The sum should then be divided by the difference of the floating points of the data double words DBD8 and DBD12.

DBD16 = DBD0 + DBD4 DBD8 – DBD12

The quotient of the above division should be stored in DBD16.

In this example, the purpose of the ENT instruction is to take the interim result (DBD0+DBD4), which is located in Accumulator 2 and save it in Accumulator 3. The subtraction command (-R) copies the interim result back to Accumulator 2 following the subtraction.

LEAVE

Example

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STL Explanation L DBD0 L DBD4 +R L DBD8 ENT L DBD12 –R /R T DBD16

Load the value from data double word DBD0 in ACCU1 (the value must be in floating-point format).

Copy the value from ACCU1 to ACCU2.Load the value from data double word DBD4 in ACCU1 (the value must be in floating-point format).

Add the contents of ACCU1 and ACCU2 as floating-point numbers (32 bits, IEEE-FP) and store the result in ACCU1.

Copy the value from ACCU1 to ACCU2.

Load the value from data double word DBD8 to ACCU1. Copy the contents of ACCU3 to ACCU4.

Copy the contents of ACCU2 (interim result) to ACCU3. Copy the contents of ACCU1 to ACCU2.

Load the contents from data double word DBD12 to ACCU1. Subtract the contents of ACCU1 from the contents of ACCU2. Store the result in ACCU1.

Copy the contents of ACCU3 to ACCU2.

Divide the contents of ACCU 2 by the contents of ACCU1. Save the quotient in ACCU1.

Transfer the result (ACCU1) to the data double word DBD16. Accumulator Operations

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4.3

Incrementing and Decrementing

You can use the Increment Accumulator 1 (INC) and Decrement Accumulator 1 (DEC) instructions to perform the following functions:  INC increases the contents of the low byte of the low word of

accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255.

 DEC decreases the contents of the low byte of the low word of accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255.

The CPU always executes the INC and DEC instructions, regardless of the result of logic operation. These instructions do not affect the RLO nor do they change any of the bits in the status word.

Note

These instructions are not suitable for 16-bit or 32-bit math because no carry is made from the low byte of the low word of accumulator 1 to the high byte of the low word of accumulator 1. For 16-bit or 32-bit math, use the +I or +D instruction, respectively.

The following sample program provides an example of how the INC instruction works within a loop triggered by a conditional jump.

STL Explanation L 1 T MB10 M1: L MB10 INC 1 T MB10 . . L B#16#5 <= I SPB M1

Body of a loop operation Set the loop counter to 1.

Load the contents of memory byte MB10 into accumulator 1. Increment the loop counter by 1.

Transfer the contents of accumulator 1 to memory byte MB10.

Instruction section which is processed five times. If the program has not run through the loop five times, then return to LOOP.

Description

Example

Figure

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References

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